this document is a general product descript ion and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 0.2 / apr. 2008 1 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 16gb nand flash H27UAG8T2M http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 2 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash document title 16gbit (2gx8bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. feb. 18. 2008 preliminary 0.1 1) add ulga package - figures & text are added. mar. 27. 2008 preliminary 0.2 1) add the text relating to the multi-plane copyback function - multi-plane copyback function must be used in the block which has been programmed with multi-plane page program. 2) correct the ball config uration of the lga package. apr. 14. 2008 preliminary http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 3 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications multi-plane architecture - array is split into two independent planes. parallel operations on both planes are available, halving program, read and erase time. nand interface - x8 bus width - multiplexed address/ data - pinout compatibility for all densities supply voltage -3.3v device : vcc = 2.7 v ~3.6 v memory cell array - (4k + 128 ) bytes x 128 pages x 4096 blocks page size - x8 device : (4096+128 spare) bytes : H27UAG8T2M block size - x8 device : (512k+16k) bytes page read / program - random access: 60us (max) - sequential access: 25ns (min) - page program time: 800us (typ) - multi-plane page program time : 800us (typ) copy back program -fast page copy fast block erase - block erase time: 2.5ms (typ) - multi-plane block erase time (2blocks) : 2.5ms(typ) status register electronic signature - 1st cycle: manufacturer code - 2nd cycle: device code - 3rd cycle: internal chip number, cell type, number of simultaneously programmed pages. - 4th cycle: page size, block size, organization, spare size - 5th cycle: multi-plane information chip enable don?t care -simple interface with microcontroller hardware data protection - program/erase locked during power transitions. data retention - 10k program / erase cycles (with 4bit/512byte ecc) - 10 years data retention package - H27UAG8T2Mtr : 48-pin tsop1(12 x 20 x 1.2 mm) - H27UAG8T2Mtr (lead & halogen free) - H27UAG8T2Mur : 52-ulga (12 x 17 x 0.65 mm) - H27UAG8T2Mur (lead & halogen free) http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 4 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 1.summary description the H27UAG8T2M is a 2048mx8bit with spare 64mx8 bit capacity . the device is offered in 3.3v vcc core power supply, 3.3v input-output power supply. its nand cell provides th e most cost-effective solution for the solid state mass stor - age market. the memory is divided into blocks that can be er ased independently so it is po ssible to preserve valid data while old data is erased. the device contains 4096 blocks, composed by 128 pages cons isting in two nand structures of 32 series connected flash cells. every cell holds two bits. like all other 4kb page nand flash devices, a program operation allows to write the 4224-byte page in typical 800us and an erase operation can be performed in typical 2.5ms on a 512k-byte block. in addition to this, thanks to multi-plane architecture, it is possible to pr ogram 2 pages a time (one per each plane) or to read 2 pages a time (one per each plane) to erase 2 bl ocks a time (again, one per each plane). as a consequence, multi-plane architecture allows program ti me reduction and erase time reduction. data in the page can be read out at 25ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migrat ion towards different densities, without any rearrangement of footprint. commands, data and addresses are synchr onously introduced using ce, we, ale and cle input pin. the on-chip program/erase controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. the modify op erations can be locked using the wp input. the output pin r/b (open drain buffer) signals th e status of the device during each operation. in a system with multiple me mories the r/b pins can be connected all to gether to provide a global status signal. even the write-intensive systems can take advantage of the H27UAG8T2M extended reliability of 10k program/erase cycles by providing ecc (error correcting co de) with real time mapping-out algorithm. the chip supports ce don?t care function . this function allows the direct down load of the code from the nand flash memory device by a microcontroller, since the ce transitions do not stop the read operation. this device includes also extra features like otp/unique id area. the H27UAG8T2M series are available in 48 - tsop1 12 x 20 mm, 52 - ulga 12 x 17 mm package. 1.1 product list part number organization vcc range package H27UAG8T2M x8 2.7~3.6 volt 48-tsop1, 52-ulga http://www..net/ datasheet pdf - http://www..net/
rev 0.2 / apr. 2008 5 1 preliminary H27UAG8T2M 16gbit (2gx8bit) nand flash 9 & |