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order number: 317505-003us october 2008 intel ? z-p140 pata solid state drive SSDPAPS0002G1, ssdpaps0004g1 product manual product features ? capacities ? 2 gb (extensible to 4 gb using intel sd54b nand flash memory components) ? 4 gb (extensible to 16 gb using intel sd58b nand flash memory components) ? pata compatibility ? ata-5 compatible ? pio mode 0-4 supported ? mwdma mode 0-2 supported ?udma mode 0-4 supported ? performance (slc components) ? sustained sequential read bandwidth: 38 mb/s (typ) ? sustained sequential write bandwidth: 29 mb/s (typ) ? pata controller flash memory interface ? four integrated 512 byte buffers ? dual channel flash interface ? flash memory power down logic ? flash memory write protect ? form factor: package on package technology ? total package volume: 12 x 18 x 1.8 mm ? top nand package: 12 x 18 x 1.39 mm, using a 122 ball grid array (bga) ? bottom pata controller: 12 x 12 mm, using a 168 ball grid array (bga) ? compliances ? halogen free ? lead free ?rohs ? power supply voltage: 3.3 v ? power consumption (vcc=3.3 v) ? sd54b package on package ? standby: 340 a; 1.12 mw (typ) ? active: 145 ma; 479 mw (typ) ? sd58b package on package ? standby: 385 a; 1.27 mw (typ) ? active: 165 ma; 545 mw (typ) ? power control features ? automatic power down during wait periods ? automatic sleep mode during host inactivity ? power loss protection: both hardware and software help prevent data corruption in the event of a power down during a write cycle ? operating temperature ? SSDPAPS0002G1, pf29f16g32panc1: 0 o c to 70 o c ? ssdpaps0004g1, pf29f32g32panc1: -40 o c to 85 o c ? non-operating: -65 o c to 150 o c ? shock (operating and non-operating): 1,500 g/0.5 ms ? vibration: 3.13 g, 5-500 hz ? nand management ? error correction code (ecc): 4 symbol ? active wear leveling algorithm (static and dynamic) ? reliability ? mean time between failure (mtbf) 2,500,000 hours ? 5 years useful life
intel? z-p140 pata ssd product manual october 2008 2 order number: 318890-003us ordering information nformation in this document is provided in connection with in tel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by th is document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pa tent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining, critical contro l or safety systems, or in nuclear facility applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. important - please read before installing or using intel? pre-release products. please review the terms at http://www.intel.com/netcomms/prerelease_terms.htm carefully before using any intel? pre-release product, including any evaluation, development or reference hardware and/or software product (collectively, ?pre-release product?). by using the pre-r elease product, you indicate your acceptance of these terms, which constitute the agreement (the ?agreement?) between you and intel corporation (?i ntel?). in the event that you do not agree with any of these terms and conditions, do not use or install the pre-release product and promptly return it unused to intel. designers must not rely on the absence or ch aracteristics of any features or instructio ns marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. this document contains information on products in the design ph ase of development. the informatio n here is subject to change wi thout notice. do not finalize a design with this information. this preliminary datasheet as well as the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. the information in this manual is furnished for informational use only, is subject to change without notice, an d should not be construed as a commitment by intel corporation. intel corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be prov ided in association with this document. except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted i n any form or by any means without the express written consent of intel corporation. copies of documents which have an order number and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . *other names and brands may be claimed as the property of others. copyright ? 2008, intel corporation. all rights reserved. intel solid state drive decoder intel z-p140 pata solid stat e drive ordering information part number mm# tape & reel (1000 pieces) mm # tray media (1 piece) device nomenclature SSDPAPS0002G1 893478 893479 intel pata value solid state drive, 2 gb, package on package (pop), single-level cell (slc) ssdpaps0004g1 893476 893477 intel pata value solid state drive, 4 gb, package on package (pop), single-level cell (slc) pf29f16g32panc1 893459 893458 intel nand flash memory sd54b 16 gb, x32, 3 v, ball grid array (bga) pf29f32g32panc1 893457 893460 intel nand flash memory sd58b 32 gb, x32, 3 v, ball grid array (bga) s d p a p 0 2 s 0 g s 0 product type designator ssd = solid state disk density 001g = 1 gb 002g = 2 gb 004g = 4 gb 008g = 8 gb 016g = 16 gb 032g = 32 gb product generation 1-9 generations bus architecture pa = pata us = universal serial bus form factor m = module p = package on package (pop) product technology type s = single level cell 1 reserved for future use
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 3 intel? z-p140 pata ssd contents 1.0 overview ................................................................................................................... 5 1.1 product overview ................................................................................................ 5 1.2 block diagram .................................................................................................... 7 1.3 architecture........................................................................................................ 7 2.0 compliance ................................................................................................................ 9 3.0 operating conditions ................................................................................................. 9 3.1 capacity .......................................................................................................... 10 3.2 performance ..................................................................................................... 10 4.0 electrical characteristics ......................................................................................... 10 4.1 power consumption ........................................................................................... 10 4.2 environmental conditions ................................................................................... 11 4.2.1 temperature.......................................................................................... 11 4.2.2 altitude................................................................................................. 11 4.3 shock and vibration........................................................................................... 12 4.4 acoustics ......................................................................................................... 12 4.5 electrostatic discharge ....................................................................................... 12 4.6 reliability ................. ............ ........... .......... ........... ........... ............ ......... ............ 12 4.7 error correction code (ecc) retries..................................................................... 13 4.8 power failure protection ..................................................................................... 13 5.0 mechanical information ........................................................................................... 14 6.0 ball assignments and signal descriptions ................................................................ 15 6.1 bottom pata controller ball assignments and locations ......................................... 15 6.2 signal descriptions ............................................................................................ 17 6.2.1 bga nand signals ................................................................................. 17 6.2.2 controller signals ................................................................................... 18 6.2.3 pata signals ......................................................................................... 18 7.0 command sets ........................................................................................................ 20 7.1 ata general feature command set ..................................................................... 20 7.1.1 identify device data .......................................................................... 21 7.2 host protected area command set ...................................................................... 23 7.3 power management command set....................................................................... 23 8.0 additional product information and references ...................................................... 24 9.0 glossary .................................................................................................................. 25 10.0 revision history ...................................................................................................... 25
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 4 order number: 318890-003us
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 5 intel? z-p140 pata ssd 1.0 overview the intel? z-p140 pata solid-state drive (ssd) is an ultra-small, complete solution for mobile computing, digital entertainmen t, and embedded applications, offering low power, high-performance, and durability. using the industry standard pata (ide) interface, the intel z-p140 pata ssd delivers the storage capacity and performance to accelerate the trend towards greater mobility. specifically designed to meet small form factor requirements, the intel z-p140 is an ideal solution for next generation mobile computing. using the standard pata interface, chip- scale package-on-package (pop) technology, and a form-factor significantly smaller than hard-disk drives, the intel z-p140 enables smaller industrial designs. with 2gb and 4gb capacities?expandable to 16gb?the intel z-p140 comfortably stores most co mputing or embedded operating systems, applications, and data, meeting mainstream capacity requirements for most ultra- mobile devices. solid-state disk technology delivers fast boot, load, and execution of applications, with no moving parts, leading to faster system responsiveness, durability, and longer battery life. 1.1 product overview offering flexible capacity of either 2 gb and 4 gb, the intel z-p140 pata solid state drives (ssds) utilize a stacked pop configuration combining a parallel advanced technology attachment (pata) controller with intel high performance nand flash memory for a compact, cost effective high performance ssd. the intel z-p140 ssds also feature flexible capacity options by adding additional intel pf29f16g32panc1 2 gb and pf29f32g32panc1 4 gb nand flash memory components all controlled by a single pop controller. for example, a 2 gb pop (SSDPAPS0002G1)can be combined with one pf29f16g32panc1 devices for a total of 4 gb of contiguous ssd storage. similarly, a 4 gb pop (ssdpaps0004g1)can be combined with one or three pf29f32g32panc 1 devices for a total of 8 or 16 gb of contiguous ssd storage. however, the in tel sd54b and sd58b nand flash memory packages cannot be mixed because the pata controller requires homogeneous memory that matches the pop memory device. this flexible capacity feature allows system designers to allow stuffing options at time of manufacture to meet market demands.
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 6 order number: 318890-003us intel? z-p140 pata ssd figure 1. front view of the intel z-p140 pata ssd figure 2. back view of the intel z-p140 pata ssd
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 7 intel? z-p140 pata ssd 1.2 block diagram 1.3 architecture the pata controller in the intel ? z-p140 pata solid state drive utilizes a 32-bit risc architecture which provides for direct conn ection of one, two or four nand flash memory devices (2 per channel). an on-chip error correction code (ecc) and cyclic redundancy check (crc) unit generates the required code bytes facilitating error detection and correction of up to four random bytes per 512 byte data sector. on the fly code byte generation for read and writ e operations minimizes ecc performance impacts. two 8-bit channels exist to interface to the flash memories that are managed through a direct flash access mechanism which alleviates the main controller from data transfer tasks. both channels can operate in parallel and each channel has 512 byte sector buffers for data transfer between the host and flash memory. intel ? z-p140 pata solid state drives use single level cell (slc) intel nand flash memory devices. a pop device consists of a nand bga component plus a pata controller. the nand packages not on th e pop are referred to as the bga nand packages in this document. sd54b based pop device can connect with one additional 2gb nand package to achieve up to 4gb of ssd storage space whereas sd58b based pop can connect up to additional 1 or 3 na nd packages to achieve 8gb and 16gb of ssd storage space respectively. see figure 3 and figure 4 on page 8 . the 2 gb intel ? z-p140 pata solid state drive uses intel sd54b nand flash memory, while the 4 gb intel ? z-p140 pata solid state drive uses intel sd58b nand flash memory. combining 2 gb packages with 4 gb packages on a single ssd design is not allowed. details about these nand devices are availabl e in their respective datasheets. please see section 8.0, ?additional product information and references? on page 24 for more information. 40 pin pata i/f 40 pin pata i/f pata controller channel 0 data 0 [0-7] channel 0 data 0 [0-7] channel 1 data 1 [0-7] channel 1 data 1 [0-7] nand flash memory
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 8 order number: 318890-003us intel? z-p140 pata ssd intel slc nand uses an industry-standard basic nand flash memory command set along with enhanced capabilities of progra m page cache mode, page read cache mode, two plane commands and interleaved die op erations. the nand write protect (wp#) feature is managed through the pata controller and can be brought out to a jumper pin for whole ssd system write protect. a single nand package has the maximum capab ility of four sets of 8-bit i/o. however, the intel z-p140 pata ssd configuration only uses two sets. each set is associated with its own set of control signals (ale, cle, etc.) figure 3. 2 gb configuration usin g intel sd54b nand flash memory 2 gb intel z-p140 only 2 gb bga nand 2 gb pop 2 gb pop 4 gb ssd 1 intel z-p140 + 1 sd54b nand device + figure 4. 4 gb configuration usin g intel sd58b nand flash memory 4 gb intel z-p140 only 4 gb bga nand 4 gb pop 4 gb pop 4 gb pop 4 gb bga nand 4 gb bga nand 4 gb bga nand 8 gb ssd 1 intel z-p140 + 1 sd58b nand device 16 gb ssd 1 intel z-p140 + 3 sd58b nand devices 8 gb ssd + +++
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 9 intel? z-p140 pata ssd 2.0 compliance since the intel z-p140 pata ssd is a component (or a set of components depending on the configuration) on the motherboard, syst em certifications are the responsibility of the oem or odm. 3.0 operating conditions notes: 1. at 4 ma. 2. at 1 ma. 3. sampled. not tested. 4. applies only to pop design. table 1. device compliance compliance supported description pb free yes components and materials are lead free. halogen free yes components and materials are halogen free. rohs yes restriction of hazardous substance directive table 2. recommended operating voltage parameter/condition symbol min typ max unit vcc supply voltage vcc 3.0 3.3 3.6 v ground vss 0 0 0 v table 3. dc characteristics (pop configuration) symbol parameter min typ max units notes v il input low voltage -0.3 +0.8 v v ih input high voltage 2.0 3.6 v v ol output low voltage 0.45 v 1 v oh output high voltage 2.4 v 2 i cc operating current sd54b sleep / standby mode 340 a 4 active mode 133 ma 4 sd58b sleep / standby mode 385 a 4 active mode 165 ma 4 i li input leakage current 10 a 4 i lo output leakage current 10 a 4 c i / o input/output capacitance 10 pf 4
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 10 order number: 318890-003us intel? z-p140 pata ssd 3.1 capacity 3.2 performance note: 450 ms is added for ata specification compliance. 4.0 electrical characteristics 4.1 power consumption table 4. user addressable sectors nand flash component unformatted capacity to tal user addressable sectors in lba mode intel sd54b nand flash memory 2 gb 3,908,016 4 gb 7,821,072 intel sd58b nand flash memory 4 gb 7,821,072 8 gb 15,650,208 16 gb 31,347,792 table 5. read and write bandwidth product access type typ unit sd54b sustained sequential read 37 mb/s sustained sequential write 26 mb/s sd58b sustained sequential read 38 mb/s sustained sequential write 29 mb/s table 6. power on specification definition typ max condition time between 0 v to when the host can read the first data 100 ms + 450 ms 500 ms + 450 ms in master configuration with no slave driver.* table 7. typical power consumption mode configuration typ unit active current* sd54b pop 145 ma sd54b pop + 1 bga nand 170 sd58b pop 165 ma sd58b pop + 1 bga nand 185 sd58b pop + 3 bga nand 185
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 11 intel? z-p140 pata ssd note: using udma 4 program mode, calculation based on worst casework load condition. 4.2 environmental conditions 4.2.1 temperature notes: 1. operating temperature gradient is 20 o c per hour without condensation. 2. non-operating temperature gradient is 30 o c per hour without condensation. 4.2.2 altitude since there are no moving parts, this device is not susceptible to a lack of air molecules and will operate correctly to 50,000 feet above sea level. active power* sd54b pop 479 mw sd54b pop + 1 bga nand 561 sd58b pop 545 mw sd58b pop + 1 bga nand 611 sd58b pop + 3 bga nand 611 sleep / standby current sd54b pop 340 ua sd54b pop + 1 bga nand 380 sd58b pop 385 ua sd58b pop + 1 bga nand 415 sd58b pop + 3 bga nand 505 sleep / standby power sd54b pop 1.12 mw sd54b pop + 1 bga nand 1.25 sd58b pop 1.27 mw sd58b pop + 1 bga nand 1.37 sd58b pop + 3 bga nand 1.66 table 7. typical power consumption (continued) mode configuration typ unit table 8. temperature related specifications mode part number min max unit operating temperature SSDPAPS0002G1, pf29f16g32panc1 0 70 o c ssdpaps0004g1, pf29f32g32panc1 -40 85 o c non-operating temperature - -65 150 o c humidity - 5 95 %
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 12 order number: 318890-003us intel? z-p140 pata ssd 4.3 shock and vibration notes: 1. shock specifications assumes that the ssd is mounted securely with the input vibration applied to the drive mounting screws. vibration may be applied in the x, y or z axis. 2. vibration specifications assumes that the ssd is mounted se curely with the input vibratio n applied to the drive mounting screws. vibration may be applied in the x, y or z axis. 3. sine wave sweeping 1 oct/min. 4.4 acoustics the drive has no moving or noise-emitting parts; therefore, it produces negligible sound (0 db) in all modes of operation. 4.5 electrostatic discharge notes: 1. performance criteria a = the device shall continue to operate as intended, i.e., normal unit operation with no degradation of performance. 2. performance criteria b = the device shall continue to operate as intended after completion of the test. however, during the test, some degradation of performance is allowed as long as there is no data loss operator intervention to restore device function. 3. performance criteria c = temporary loss of function is allowed. operator intervention is acceptable to restore device function. 4.6 reliability note: based on a sequential workload of 5 gb/day. table 9. shock and vibration specifications mode timing max unit shock 1 operating at .5 msec 1,500 g non-operating at .5 msec 1,500 g vibration 2 operating 3.13 g 5-500 hz non-operating 5 g 10-500 hz 3 table 10. esd specifications test description performance criteria reference standard ? 2 kv human body model b jedec standard jesd22-a114e ? 500 v charge device model b je dec standard jes d22-c101c table 11. reliability specifications parameter value non-recoverable read errors 1 sector per 10 15 bits read, max mean time between failure (mtbf) 2,500,000 hours useful life 5 years*
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 13 intel? z-p140 pata ssd 4.7 error correction code (ecc) retries when the controller encounters an uncorrectable ecc error while reading data from the flash device, the controller will repeat the read command to the flash device up to three times. if the process is unsuccessful, th e ecc failure will be reported back to the host and both aborted (abrt) and uncorrectab le data error (unc) bits will be set in the error register. this process enables the intel z-p140 pata ssd device to recover from a single disturbance such as an esd event, but not incorrectly report a block as bad. the device will still be able to mana ge ecc for true persistent uncorrectable errors. 4.8 power failure protection the device uses both hardware and software protection to prevent data corruption during power failures. a flash write protect line activates hardware protection should the controller?s v cc voltage level fall below 2.7 v. a flash write buffering scheme writes data to flash memory to provide software protection. a target user block writes all new data to an associated flash buffer block. on power-up, the controller scans the buffer blocks (which could contain new data that is in the process of being written) for ecc errors to prevent data corruption. so, although a page written to during a power off could be lost, no data corruption occurs.
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 14 order number: 318890-003us intel? z-p140 pata ssd 5.0 mechanical information figure 5. combined top and bottom mechanical drawings note: all dimensions in millimeters.
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 15 intel? z-p140 pata ssd 6.0 ball assignments and signal descriptions 6.1 bottom pata controller ba ll assignments and locations the following table depicts the ball out assignment and locations for the 168 bga bottom controller, which includes 156 active balls and 12 outriggers. due to space limitations the 12 outriggers are not shown. please see figure 5, ?combined top and bottom mechanical drawings? on page 14 to view the location of the outriggers. table 12. ball assignments and lo cations viewed from the top 12 3456789101112131415 1617 a dnu dnu dq01-0 dq02-0 dq03-0 we#-0 ale-0 cle-0 ce0#-0 ce1#-0 re#-0 r/b0#-0 dq04-0 dq05-0 dq06-0 dnu dnu b dnu dq00-0 dq01-2 dq02-2 dq03-2 we#-2 ale-2 cle-2 ce0#-2 ce1#-2 re#-2 r/b0#-2 dq04-2 dq05-2 dq06-2 dq07-0 dnu c vss dq00-2 vccf wp#-2 wp#-0 cfg-0 vccf vss cfg-4 v ss vccf cfg-2 r/b1#-0 r/b1#-2 vccf dq07-2 vss d gnd dnu (busrq#) rfu nb nb nb nb nb nb nb nb nb nb nb cfg-6 dnu (test) gnd e vddf xtalr (xtalsel) xtalin (xtali) nb nb nb nb nb nb nb nb nb nb nb dnu (uart_rx) dnu (uart_tx) vddc f vddf xtalc (io3) iocs16# nb nb nb nb nb nb nb nb nb nb nb hreset# dnu (uart_clk) vddc g fadj (ibias) pdiag# dasp# nb nb nb nb nb nb nb nb nb nb nb reset# pwe# cadj (int4) h vddf_0 da0 dmack# nb nb nb nb nb nb nb nb nb nb nb intrq psync_ csel# vddc_o j vddf_0 da1 dmarq nb nb nb nb nb nb nb nb nb nb nb diow# dior# vddc_o k gnd da2 iordy nb nb nb nb nb nb nb nb nb nb nb cs3fx# cs1fx# gnd l gnd dd11 dd3 nb nb nb nb nb nb nb nb nb nb nb dd4 dd12 gnd m vcc dd10 dd2 nb nb nb nb nb nb nb nb nb nb nb dd5 dd13 vcc n gnd dd9 dd1 nb nb nb nb nb nb nb nb nb nb nb dd6 dd14 gnd p vcc dd8 dd0 nb nb nb nb nb nb nb nb nb nb nb dd7 dd15 vcc r vss dq00-3 vccf wp#-3 wp#-1 cfg-1 vccf vss cfg-5 v ss vccf cfg-3 r/b1#-1 r/b1#-3 vccf dq07-3 vss t dnu dq00-1 dq01-3 dq02-3 dq03-3 we#-3 ale-3 cle-3 ce0#-3 ce1#-3 re#-3 r/b0#-3 dq04-3 dq05-3 dq06-3 dq07-1 dnu u dnu dnu dq01-1 dq02-1 dq03-1 we#-1 ale-1 cle-1 ce0#-1 ce1#-1 re#-1 r/b0#-1 dq04-1 dq05-1 dq06-1 dnu dnu
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 16 order number: 318890-003us intel? z-p140 pata ssd table 13. signal locator signal name bga location signal name bga location signal name bga location ale-0 a7 dd5 m15 dq03-2 b5 ale-1 u7 dd6 n15 dq03-3 t5 ale-2 b7 dd7 p15 dq04-0 a13 ale-3 t7 dd8 p2 dq04-1 u13 cadj / int4 g17 dd9 n2 dq04-2 b13 ce0#-0 a9 dd10 m2 dq04-3 t13 ce0#-1 u9 dd11 l2 dq05-0 a14 ce0#-2 b9 dd12 l16 dq05-1 u14 ce0#-3 t9 dd13 m16 dq05-2 b14 ce1#-0 a10 dd14 n16 dq05-3 t14 ce1#-1 u10 dd15 p16 dq06-0 a15 ce1#-2 b10 dior# j16 dq06-1 u15 ce1#-3 t10 diow# j15 dq06-2 b15 cfg-0 c6 dmack# h3 dq06-3 t15 cfg-1 r6 dmarq j3 dq07-0 b16 cfg-2 c12 dnu a1, a2, a16, a17, b1, b17, t1, t17, u1, u2, u16, u17 dq07-1 t16 cfg-3 r12 dnu / busrq# d2 dq07-2 c16 cfg-4 c9 dnu / test d16 dq07-3 r16 cfg-5 r9 dnu / uart_clk f16 fadj / ibias g1 cfg-6 d15 dnu / uart_rx e15 gnd d1, d17, k1, k17, l1, l17, n1, n17 cle-0 a8 dnu / uart_tx e16 hreset# f15 cle-1 u8 dq00-0 b2 intrq h15 cle-2 b8 dq00-1 t2 iocs16# f3 cle-3 t8 dq00-2 c2 iordy k3 cs1fx# k16 dq00-3 r2 pdiag# g2 cs3fx# k15 dq01-0 a3 psync_csel# h16 da0 h2 dq01-1 u3 pwe# g16 da1 j2 dq01-2 b3 r/b0#-0 a12 da2 k2 dq01-3 t3 r/b0#-1 u12 dasp# g3 dq02-0 a4 r/b0#-2 b12 dd0 p3 dq02-1 u4 r/b0#-3 t12 dd1 n3 dq02-2 b4 r/b1#-0 c13 dd2 m3 dq02-3 t4 r/b1#-1 r13 dd3 l3 dq03-0 a5 r/b1#-2 c14 dd4 l15 dq03-1 u5 r/b1#-3 r14
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 17 intel? z-p140 pata ssd 6.2 signal descriptions 6.2.1 bga nand signals re#-0 a11 vddc_0 h17, j17 wp#-0 c5 re#-1 u11 vddf e1, f1 wp#-1 r5 re#-2 b11 vddf_0 h1, j1 wp#-2 c4 re#-3 t11 vss c1, c8, c10, c17, r1, r8, r10, r17 wp#-3 r4 reset# g15 we#-0 a6 xtalc / io3 f2 rfu d3 we#-1 u6 xtalin / xtali e3 vcc m1, m17, p1, p17 we#-2 b6 xtalr / xtalsel e2 vddc e17, f17 we#-3 t6 table 13. signal locator (continued) signal name bga location signal name bga location signal name bga location table 14. bga nand signal descriptions symbol type description ale-0, ale-1 ale-2, ale-3 input address latch enable (channels 0, 1, 2 and 3): during the time ale is high, address information is transferred from i/o[7:0] into the on-chip address register on the rising edge of we#. when address information is not being loaded, ale should be driven low. ce0#-0, ce1#-0 ce0#-1, ce1#-1 ce0#-2, ce1#-2 ce0#-3, ce1#-3 input chip enable (channels 0, 1, 2 and 3): gates transfers between the host system and the nand flash device. after the device starts a program or erase operation, ce# can be de-asserted. for the 8 gb configuration, ce0# controls the first 4 gb of memory; ce1# controls the second 4 gb of memory. for the 16 gb configuration, ce0# controls the first 8 gb of memory; ce1# controls the second 8 gb. see the bus operation section, starting on page 15 , for additional operational details. cle-0, cle-1 cle-2, cle-3 input command latch enable (channels 0, 1, 2 and 3): when cle is high, information is transferred from i/o[7:0] to the on-chip command register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re#-0, re#-1 re#-2, re#-3 input read enable: gates transfers from the nand flash device to the host system. we#-0, we#-1 we#-2, we#-3 input write enable: gates transfers from the host system to the nand flash device. wp#-0, wp#-1 wp#-2, wp#-3 input write protect: protects against inadvertent program and erase operations. all program and erase operations are disabled when wp# is low. dq[00...07]-0 dq[00...07]-1 dq[00...07]-2 dq[00...07]-3 input / output data inputs/outputs: the bidirectional i/os transfer address, data, and instruction information between the pop pata controller and the additional bga nand devices. data is output only during read operations; at other times the i/os are inputs.
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 18 order number: 318890-003us intel? z-p140 pata ssd 6.2.2 controller signals 6.2.3 pata signals r/b0#-0, r/b1#-0 r/b0#-1, r/b1#-1 r/b0#-2, r/b1#-2 r/b0#-3, r/b1#-3 output ready/busy: an open-drain , active-low output. r/b# is used to indicate when the chip is processi ng a program or erase operation. it is also used during read operations to indicate wh en data is being transferred from the array into the serial data register. wh en these operations have completed, r/b# returns to the high-z state. in the dual die per channel configurations, r/b0# is for the memory enabled by ce 0#; r/b1# is for the memory enabled by ce1#. vccf supply power supply for flash (nand) that is regulated by the pata controller. vss supply ground connection. table 14. bga nand signal descriptions (continued) symbol type description table 15. controller signal descriptions symbol type description cadj / int4 not used. cfg-0, cfg-1, cfg-2, cfg-3, cfg-4, cfg-5, cfg-6 input configuration signals used by the controller to manage the configuration options on the bga nand devices. all configuration signals must be connected per the intel z-p140 pata ssd reference schematics . dnu do not use. must be left unconnected. gnd supply ground connection. rfu reserved for future use. vcc supply power supply for pata controller. vddc, vddc_0 supply 2.5 v core power supply for pata cont roller. this voltage is generated internally by the controller, so there?s not a need for an external supply. vddf, vddf_0 supply controller regulated flash voltage supply . this voltage is generated internally by the controller, so there?s not a need for an external supply. fadj / ibias input ibias requires a 33 k 1% resistor for unit to work properly. xtalc / io3 input / output general purpose input and output. xtalin / xtali input test clock input. xtalr / xtalsel output test clock select. table 16. pata signal descriptions symbol type description cs1fx# input drive chip select 0 is used by host to select command block registers. cs3fx# input drive chip select 1 is used by host to select command block registers. da0...2 input drive address signals. dasp# output drive active, drive 1 present, or dma request / true-ide dasp. dd0-15 input / output data and address bus.
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 19 intel? z-p140 pata ssd dior# input i/o data read enable is the strobe signal asserted by the host to read device registers or the data port. diow# input i/o data write enable is the strobe signal asserted by the host to write device registers or the data port. diow shall be negated by the host prior to the initiation of an ultra dma burst. stop shall be negated by the host before the data is transferred in an ultra dma burst. the assertion of stop by the host during an ultra dma burst signals the termination of the ultra dma burst. dmack# input dma acknowledge, used by the host in response to dmarq to either acknowledge that data has been accepted, or that the data is available. dmarq output dma request. this signal , used for dma data transfers between host and device, shall be asserted by the device wh en it is ready to transfer data to or from the host. for multi word dma transfer s, the direction of data transfer is controller by dior# and diow#. this signal is used in a ?handshake? manner with dmack#. for example, the device shall wait until the host asserts dmack# before negating dmarq and re -asserting dmarq if there is more data to transfer. when a dms operation is enabled, cs0# and cs1# shall not be asserted and transfers shall be 16 bits wide. this signal shall be release when the device is not selected. hreset# input host reset. iocs16# output 16-bit i/o transfer. intrq output drive interrupt request. iordy input / output i/o channel ready. pdiag# input / output passed diagnostics. psync_csel# input cable select for master/s lave, spindle synch, or true-ide chip. pwe# input memory write enable or service mode select. reset# input refers to the hardware reset that is used by the host to reset the device. table 16. pata signal descriptions (continued) symbol type description
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 20 order number: 318890-003us intel? z-p140 pata ssd 7.0 command sets the intel z-p140 pata ssd device supports all the mandatory ata commands defined in the ata/atapi-5 specification. 7.1 ata general fe ature command set the intel z-p140 pata ssd device suppor ts the ata general feature command set (non-packet). table 17. ata general feature commands command name code erase sector(s) c0h execute device diagnostic 90h format track 50h flush cache e7h identify device ech identify device dma eeh initialize drive parameters 91h media lock deh media unlock deh nop 00h read buffer e4h read dma c8h, c9h read long 22h, 23h read multiple c4h read sector(s) 20h, 21h read verify sector(s) 40h, 41h recalibrate 1xh request sense 03h seek 7xh set features efh set multiple mode c6h translate sector 87h write buffer e8h write dma cah, cbh write long 32h, 33h write multiple c5h write multiple without erase cdh write sector(s) 30h, 31h write sector(s) without erase 38h write verify 3ch
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 21 intel? z-p140 pata ssd 7.1.1 identify device data the following table details the data retu rned after issuing an identify device command. table 18. returned sector data word sd54b default value sd58b default value bytes description 0 045ah 045ah 2 general configuration bit-significant information: 848ah = in pcmcia mode 045ah = in true-ide mode 1 2 gb: 0e98h 4 gb: 1d3ah 4 gb: 1e4fh 8 gb: 3ca6h 2 reserved 2 0000h 0000h 2 unique configuration 3 0010h 0010h 2 reserved 4 0000h 0000h 2 reserved 5 0200h 0200h 2 reserved 6 003fh 003fh 2 reserved 7-8 2 gb: 0039h, 8250h 4 gb: 0073h, 1460h 4 gb: 0077h, 5710h 8gb: 00eeh, cda0h 4 reserved 9 0000h 0000h 2 reserved 10-19 xxxxx xxxxx 20 intel unique identifier (serial number): reserved 20-21 0002h 0002h 4 reserved 22 0004h 0004h 2 reserved 23-26 3038h,3038h, 3139h,2e31h 3038h,3038h, 3139h,2e31h 8 firmware revision (8 ascii characters) 080819.1 27-46 2 gb: 5353h, 4450h, 4150h, 5330h, 3030h, 3247h, 3100h, 0000h, 0000h, 0000h 4 gb: 5353h, 4450h, 4150h, 5330h, 3030h, 3447h, 3120h, 2020h, 2020h, 2020h 40 model number (40 ascii characters) 2 gb: SSDPAPS0002G1 4 gb: ssdpaps0004g1 47 8002h 8002h 2 reserved 48 0000h 0000h 2 reserved 49 0f00h 0f00h 2 capabilities: dm a, lba, iordy supported 50 0000h 0000h 2 reserved 51 0200h 0200h 2 obsolete 52 0000h 0000h 2 obsolete 53 0007h 0007h 2 data fields 54 to 58, 64 to 70 and 88 are valid 54 2 gb: 0e9bh 4 gb: 1d3ah 4 gb: 1e4fh 8 gb: 3ca6h 2 reserved 55 0010h 0010h 2 reserved 56 003fh 003fh 2 reserved
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 22 order number: 318890-003us intel? z-p140 pata ssd 57-58 2 gb: 8250h, 0039h 4 gb: 1460h, 0073h 4 gb: 5710h, 0077h 8 gb: cda0h, 00eeh 4 reserved 59 0102h 0102h 2 reserved 60-61 2 gb: 8250h, 0039h 4 gb: 1460h, 0073h 4 gb: 5710h, 0077h 8 gb: cda0h, 00eeh 4 total number of user addressable logical sector 62 0000h 0000h 2 reserved 63 0007h 0007h 2 multi-word dma transfer mode 2 and below are supported 64 0003h 0003h 2 advanced pio modes: modes 3 and 4 supported 65 0078h 0078h 2 minimum multiword dma transfer cycle time per word 66 0078h 0078h 2 recommended multiword dma transfer cycle time 67 0078h 0078h 2 minimum pio transfer cycle time without flow control 68 0078h 0078h 2 minimum pio transfer cycle time with iordy flow control 69-70 0000h 0000h 4 reserved 71-74 0000h 0000h 8 reserved for identify packet device command 75 0000h 0000h 2 queue depth 76-79 0000h 0000h 8 reserved for sata 80 0020h 0020h 2 major version number, ata-5 support 81 0000h 0000h 2 minor version number, not reported 82 7408h 7408h 2 command sets supported: nop, read buffer, write buffer, host protected area (hpa) and mandatory power management feature set 83 5000h 5000h 2 command set supported: flush cache 84 4000h 4000h 2 command set/feature supported extension 85 7408h 7408h 2 command set enabled: nop, re ad buffer, write buffer, host protected area (hpa) and mandatory power management feature set 86 1000h 1000h 2 command set enabled: flush cache 87 4000h 4000h 2 command set/feature default 88 101fh 101fh 2 udma mode 4 89-92 0000h 0000h 8 reserved 93 604fh 604fh 2 hardware reset result 94-128 0000h 0000h 70 reserved 129-159 xxxx xxxx 62 vendor specific 160-175 000hh 000hh 32 reserved 176-254 0000h 0000h 158 reserved 255 2 gb: 6aa5h 4 gb: 73a5h 2 gb: e9a5h 4 gb: fea5h 2 integrity word (checksum) table 18. returned sector data (continued) word sd54b default value sd58b default value bytes description
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 23 intel? z-p140 pata ssd 7.2 host protected area command set the intel z-p140 pata ssd device supports the following host protected area commands: 7.3 power management command set the intel z-p140 pata ssd device supports the power management command set. table 19. host protected area commands command name code read native max address f8h set max address f9h table 20. power management commands command name code check power mode e5h, 98h idle e3h, 97h idle immediate e1h, 95h set sleep mode e6h, 99h standby e2h, 96h standby immediate e0h, 94h
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 24 order number: 318890-003us intel? z-p140 pata ssd 8.0 additional product information and references for detailed information about a product ment ioned in this document, please refer to the corresponding datasheet or application note. note: customers who request access to advanced datasheets must have a a non-disclosure agreement (nda) with intel. we release advanced datasheets prior to preliminary datasheets, which are released around the time a product is sampled. production datasheets become available when the part is mass produced. to obtain a copy of these documents, please contact your intel field sales representative. this document also references standards and specifications defined by a variety of organizations. please use the following information to identify the location of an organization?s standards information. table 21. addition product information order number title type* 318531-003us intel? sd54b nand flash memory datasheet production 318906-002us intel? sd58b nand flash memory datasheet production 319743-001us intel? z-p140 pata solid state drive configuration tool 319541-001us intel? z-p140 pata solid state drive reference schematic table 22. standards references date or revision number title location february 2000 ata-5 http://www.t13.org/documents/ uploadeddocuments/project/d1321r3-ata- atapi-5.pdf january 2007 jedec standard: electrostatic discharge (esd) sensitivity testing human body model (hbm) http://www.jedec.org/download/search/ default2.cfm december 2004 jedec standard jesd22-c101c: field-induced charged-device model test method for electrostatic- discharge-withstand thresholds of microelectronic components http://www.jedec.org/download/search/ default2.cfm 1995 international electrotechnical commission env 50204 (radiated electromagnetic field from digital radio telephones) http://www.iec.ch 1995 1996 1995 1995 1997 1994 international electrotechnical commission en 61000 4-2 (personnel electrostatic discharge immunity) 4-3 (electromagnetic compatibility (emc)) 4-4 (electromagnetic compatibility (emc)) 4-5 (electromagnetic compatibility (emc)) 4-6 (electromagnetic compatibility (emc)) 4-11 (voltage variations) http://www.iec.ch december 2006 open nand flash interface specificati on (onfi) 1.0 http://www.onfi. org/docs/onfi_1_0_gold.pdf
intel? z-p140 pata ssd october 2008 product manual order number: 318890-003us 25 intel? z-p140 pata ssd 9.0 glossary this document incorporates many industry- and device-specific words. use the following list to define a variety of terms and acronyms. 10.0 revision history table 23. glossary of terms and acronyms term definition ata advanced technology attachment cfa compactflash association cprm content protection for recordable media crc cyclic redundancy check dma direct memory access ecc error correction code esd electrostatic discharge hdd hard disk drive hpa host protected area ide integrated device electronics lba logical block addressing mtbf mean time between failure mwdma multi-word dma odm original design manufacturer oem original equipment manufacturer pata parallel ata pcmcia personal computer memory card international association pio programmable input / output pop package on package sata serial ata ssd solid state drive udma ultra dma, also know ultra ata date revision description october 2008 003 on the cover page, modified performance and power consumption values, edited the values for extended temperature coverage on 4gb and 8 egb. updated values in table 18, ?returned sector data? on page 21 updated figure figure 1, ?front view of the intel z-p140 pata ssd? on page 6 modified the mm numbers for each product listed in the ?ordering information? on page 2 . modified values lba in table 4, ?user addressable sectors? on page 10 modified values and notes in table 3, ?dc characteristics (pop configuration)? on page 9 modified values of current and power in table 7, ?typical power consumption? on page 10 .
intel? z-p140 pata ssd intel? z-p140 pata ssd product manual october 2008 26 order number: 318890-003us intel? z-p140 pata ssd june 2008 002 on the cover page, modified the total number of extensible memory from 8 gb to 4 gb when using 2 gb configuration, modified performance and power consumption values, inserted the values for extended temperature and added a reference for halogen free compliance. update the mm numbers for each product listed in the ?ordering information? on page 2 . modified content in the following sections: ? section 1.0, ?overview? on page 5 ? section 1.1, ?product overview? on page 5 removed the pop + 3 bga nand configuration from figure 3, ?2 gb configuration using intel sd54b nand flash memory? on page 8 . added ?halogen free? to table 1, ?device compliance? on page 9 . added the values for ?ground? to table 2, ?recommended operating voltage? on page 9 . modified values and notes in table 3, ?dc characteristics (pop configuration)? on page 9 . updated values in table 4, ?user addressable sectors? on page 10 and table 5, ?read and write bandwidth? on page 10 . removed former table 7, operating voltage because information al ready contained in ta b l e 2 , ?recommended operating voltage? on page 9 . modified values and format of current table 7, ?typical power consumption? on page 10 . modified table 8, ?temperature related specifications? on page 11 and notes. added note to figure 5, ?combined top and bottom mechanical drawings? on page 14 . added definition of useful life to table 11, ?reliability specifications? on page 12 . updated the following tables: ? table 12, ?ball assignments and locations viewed from the top? on page 15 ? table 13, ?signal locator? on page 16 modified description for ready/busy (r/b#) in table 14, ?bga nand signal descriptions? on page 17 merged the content from former table 18, f3-specific signal descriptions with ta b l e 1 5 , ?controller signal descriptions? on page 18 . updated the following tables ? table 16, ?pata signal descriptions? on page 18 ? table 18, ?returned sector data? on page 21 added section 8.0, ?additional product information and references? on page 24 . added the ordering information for the intel z- p140 pata ssd configuration tool and updated the ordering number for intel z-p 140 pata ssd reference schematic in table 21, ?addition product information? on page 24 . added mwdma, hpa and corresponding definitions to section 9.0, ?glossary? on page 25 . december 2007 001 initial pre-release date revision description

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