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| d a t a sh eet product speci?cation file under integrated circuits, ic24 2002 feb 26 integrated circuits 74ALVC373 octal d-type transparent latch; 3-state
2002 feb 26 2 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 features wide supply voltage range from 1.65 to 3.6 v complies with jedec standard: jesd8-7 (1.65 to 1.95 v) jesd8-5 (2.3 to 2.7 v) jesd8b/jesd36 (2.7 to 3.6 v). 3.6 v tolerant inputs/outputs cmos low power consumption direct interface with ttl levels (2.7 to 3.6 v) power-down mode latch-up performance exceeds 250 ma esd protection: 2000 v human body model (jesd22-a114-a) 200 v machine model (jesd22-a115-a). description the 74ALVC373 is a high-performance, low-power, low-voltage, si-gate cmos device and superior to most advanced cmos compatible ttl families. the 74ALVC373 is an octal d-type transparent latch featuring separate d-type inputs for each latch and 3-state outputs for bus oriented applications. a latch enable (le) input and an output enable ( oe) input are common to all internal latches. the 74ALVC373 consists of eight d-type transparent latches with 3-state true outputs. when le is high, data at the d n inputs enters the latches. in this condition the latches are transparent, i.e. a latch output will change state each time its corresponding d-input changes. when le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when oe is low, the contents of the 8 latches are available at the outputs. when oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. the 373 is functionally identical to the 573, but the 573 have a different pin arrangement. quick reference data gnd = 0 v; t amb =25 c. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i +(c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts. 2. the condition is v i = gnd to v cc and the latch is in transparent mode. symbol parameter conditions typ. unit t phl /t plh propagation delay inputs d n to output q n v cc = 1.8 v; c l = 30 pf; r l =1k w 3.0 ns v cc = 2.5 v; c l = 30 pf; r l = 500 w 2.3 ns v cc = 2.7 v; c l = 50 pf; r l = 500 w 2.4 ns v cc = 3.3 v; c l = 50 pf; r l = 500 w 2.2 ns c i input capacitance 3.5 pf c pd power dissipation capacitance per buffer v cc = 3.3 v; notes 1 and 2 outputs enable 35 pf outputs disabled 14 pf 2002 feb 26 3 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 ordering information function table see note 1. note 1. h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; l = low voltage level one set-up time prior to the high-to-low le transition; x = dont care; z = high-impedance off-state. pinning type number packages pins package material code 74ALVC373d 20 so plastic sot163-1 74ALVC373pw 20 tssop plastic sot360-1 operating modes input internal latches outputs oe le d n q 0 to q 7 enable and read register (transparent mode) lhlll lhhhh latch and read register l l l l l llhhh latch register and disable outputs hxxxz hlhhz pin symbol description 1 oe output enable input (active low) 2, 5, 6, 9, 12, 15, 16, 19 q 0 to q 7 3-state latch output 3, 4, 7, 8, 13, 14, 17, 18 d 0 to d 7 data input 10 gnd ground (0 v) 11 le latch enable input (active high) 20 v cc supply voltage 2002 feb 26 4 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 fig.1 pin configuration. handbook, halfpage oe q 0 d 0 d 1 q 1 q 2 d 2 d 3 q 3 gnd v cc q 7 d 7 d 6 q 5 d 5 q 6 d 4 q 4 le 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 373 mna185 handbook, halfpage mna186 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 oe le q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 11 1 19 16 15 12 9 6 5 2 18 17 14 13 8 7 4 3 fig.2 logic symbol. handbook, halfpage mna187 19 16 15 12 9 6 5 11 c1 1 en 1d 2 18 17 14 13 8 7 4 3 fig.3 iee/iec logic symbol. handbook, halfpage mna184 3-state outputs latch 1 to 8 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 19 16 15 12 9 6 5 2 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 le oe 18 11 1 17 14 13 8 7 4 3 fig.4 function diagram. 2002 feb 26 5 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 handbook, halfpage q le d le le le mna692 fig.5 logic diagram (one latch). handbook, full pagewidth mna199 q 4 d 4 d le q q 3 d 3 d le q q 2 d 2 d le q q 1 d 1 d le le le q q 0 d 0 d latch 1 latch 2 latch 3 latch 4 latch 5 q le oe le le le le q 5 d 5 d le q latch 6 le q 6 d 6 d le q latch 7 le q 7 d 7 d le q latch 8 le fig.6 logic diagram. 2002 feb 26 6 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. when v cc = 0 v (power-down mode), the output voltage can be 3.6 v in normal operation. symbol parameter conditions min. max. unit v cc supply voltage 1.65 3.6 v v i input voltage 0 3.6 v v o output voltage enable mode; v cc = 1.65 to 3.6 v 0 v cc v disable mode; v cc = 1.65 to 3.6 v 0 3.6 v power-down mode; v cc = 0 v 0 3.6 v t amb operating ambient temperature - 40 +85 c t r ,t f input rise and fall times v cc = 1.65 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +4.6 v i ik input diode current v i <0 -- 50 ma v i input voltage - 0.5 +4.6 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage enable mode; notes 1 and 2 - 0.5 v cc + 0.5 v disable mode - 0.5 +4.6 v power-down mode; note 2 - 0.5 +4.6 v i o output diode current v o =0tov cc - 50 ma i gnd , i cc v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation per package so package above 70 c derate linearly with 8 mw/k - 500 mw tssop package above 60 c derate linearly with 5.5 mw/k - 500 mw 2002 feb 26 7 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). notes 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. 2. for transceivers, the parameter i oz includes the input leakage current. symbol parameter test conditions t amb ( c) unit other v cc (v) - 40 to +85 min. typ. (1) max. v ih high-level input voltage 1.65 to 1.95 0.65 v cc -- v 2.3 to 2.7 1.7 -- v 2.7 to 3.6 2 -- v v il low-level input voltage 1.65 to 1.95 -- 0.35 v cc v 2.3 to 2.7 -- 0.7 v 2.7 to 3.6 -- 0.8 v v ol low-level output voltage v i =v ih or v il ; i o = 100 m a 1.65 to 3.6 -- 0.2 v v i =v ih or v il ; i o = 6 ma 1.65 - 0.11 0.3 v v i =v ih or v il ; i o = 12 ma 2.3 - 0.17 0.4 v v i =v ih or v il ; i o = 18 ma 2.3 - 0.25 0.6 v v i =v ih or v il ; i o = 12 ma 2.7 - 0.16 0.4 v v i =v ih or v il ; i o = 18 ma 3.0 - 0.23 0.4 v v i =v ih or v il ; i o = 24 ma 3.0 - 0.30 0.55 v v oh high-level output voltage v i =v ih or v il ; i o = - 100 m a 1.65 to 3.6 v cc - 0.2 -- v v i =v ih or v il ; i o = - 6 ma 1.65 1.25 1.51 - v v i =v ih or v il ; i o = - 12 ma 2.3 1.8 2.10 - v v i =v ih or v il ; i o = - 18 ma 2.3 1.7 2.01 - v v i =v ih or v il ; i o = - 12 ma 2.7 2.2 2.53 - v v i =v ih or v il ; i o = - 18 ma 3.0 2.4 2.76 - v v i =v ih or v il ; i o = - 24 ma 3.0 2.2 2.68 - v i i input leakage current v i = 3.6 v or gnd 3.6 - 0.1 5 m a i oz 3-state output off-state current v i =v ih or v il ; v o = 3.6 v or gnd; note 2 1.65 to 3.6 - 0.1 10 m a i off power off leakage current v i or v o = 0 to 3.6 v 0.0 - 0.1 10 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 3.6 - 0.2 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o = 0 3.0 to 3.6 - 5 750 m a 2002 feb 26 8 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 ac characteristics note 1. all typical values are measured at t amb =25 c. symbol parameter test conditions t amb ( c) unit waveforms v cc (v) - 40 to +85 min. typ. (1) max. t phl /t plh propagation delay d n to q n see figs 7 and 11 1.65 to 1.95 1.0 2.5 5.4 ns 2.3 to 2.7 1.0 2.0 3.5 ns 2.7 1.0 2.3 3.6 ns 3.0 to 3.6 1.0 2.2 3.3 ns t phl /t plh propagation delay le to q n see figs 8 and 11 1.65 to 1.95 1.0 2.8 6.0 ns 2.3 to 2.7 1.0 2.1 3.8 ns 2.7 1.0 2.4 3.7 ns 3.0 to 3.6 1.0 2.3 3.3 ns t pzh /t pzl 3-state output enable time oe to q n see figs 9 and 11 1.65 to 1.95 1.5 3.0 6.4 ns 2.3 to 2.7 1.0 2.4 4.5 ns 2.7 1.5 3.0 4.6 ns 3.0 to 3.6 1.0 2.3 4.0 ns t phz /t plz 3-state output disable time oe to q n see figs 9 and 11 1.65 to 1.95 1.5 3.4 7.0 ns 2.3 to 2.7 1.0 2.2 4.4 ns 2.7 1.5 2.8 4.4 ns 3.0 to 3.6 1.0 2.7 4.4 ns t w le pulse with high see figs 8 and 11 1.65 to 1.95 3.8 1.0 - ns 2.3 to 2.7 3.3 0.8 - ns 2.7 3.3 2.0 - ns 3.0 to 3.6 3.3 2.2 - ns t su set-up time d n to le see figs 10 and 11 1.65 to 1.95 0.8 0.1 - ns 2.3 to 2.7 0.8 0.1 - ns 2.7 0.8 0.1 - ns 3.0 to 3.6 0.8 0.1 - ns t h hold time d n to le see figs 10 and 11 1.65 to 1.95 0.8 - 0.1 - ns 2.3 to 2.7 0.8 - 0.2 - ns 2.7 0.8 - 0.3 - ns 3.0 to 3.6 0.7 - 0.1 - ns 2002 feb 26 9 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 ac waveforms handbook, halfpage mna693 d n input q n output t phl t plh gnd v i v m v m v oh v ol fig.7 input d n to output q n propagation delay times. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns handbook, full pagewidth mna694 le input q n output t phl t plh t w 1/f max v m v oh v i gnd v ol v m fig.8 latch enable (le) input pulse width and latch enable input to output (q n ) propagation delays. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns 2002 feb 26 10 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 handbook, full pagewidth mna395 t plz t phz outputs disabled outputs enabled v y v x outputs enabled q n output low-to-off off-to-low q n output high-to-off off-to-high oe input v i v ol v oh v cc v m gnd gnd t pzl t pzh v m v m fig.9 3-state enable and disable times. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns v ol and v oh are typical output voltage drop that occur with the output load. v x =v ol + 0.3 v at v cc 3 2.7 v; v x =v ol + 0.15 v at v cc < 2.7 v; v y =v oh - 0.3 v at v cc 3 2.7 v; v y =v oh - 0.15 v at v cc < 2.7 v. 2002 feb 26 11 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 handbook, full pagewidth mna695 t h t su t h t su v m v m v i gnd v i gnd le input d n input fig.10 the data set-up and hold times for d n input to le input. the shaded areas indicate when the input is permitted to change for predictable output performance. v cc v m input v i t r =t f 1.65 to 1.95 v 0.5 v cc v cc 2.0 ns 2.3 to 2.7 v 0.5 v cc v cc 2.0 ns 2.7 v 1.5 v 2.7 v 2.5 ns 3.0 to 3.6 v 1.5 v 2.7 v 2.5 ns handbook, full pagewidth v ext v cc v i v o mna616 d.u.t. c l r t r l r l pulse generator fig.11 load circuitry for switching times. r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. v cc v i c l r l v ext t plh /t phl t pzh /t phz t pzl /t plz 1.65 to 1.95 v v cc 30 pf 1 k w open gnd 2 v cc 2.3 to 2.7 v v cc 30 pf 500 w open gnd 2 v cc 2.7 v 2.7 v 50 pf 500 w open gnd 6 v 3.0 to 3.6 v 2.7 v 50 pf 500 w open gnd 6 v 2002 feb 26 12 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 97-05-22 99-12-27 2002 feb 26 13 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1.0 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 95-02-04 99-12-27 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.10 2002 feb 26 14 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2002 feb 26 15 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable 2002 feb 26 16 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2002 feb 26 17 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 notes 2002 feb 26 18 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 notes 2002 feb 26 19 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ALVC373 notes ? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 613508/01/pp 20 date of release: 2002 feb 26 document order number: 9397 750 09437 |
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