n3001rm(ot)no.7143-1/9 any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. preliminary overview the lc72311w, lc72312w, and LC72313W are low-voltage single-chip fm/am electronic tuning microcontrollers that include a built-in pll circuit for frequencies up to 230 mhz, a 1/4 duty 1/2 bias lcd controller, and a small eeprom. these microcontroller also provide a low-power standby mode that reduces power consumption by switching the system clock frequency. furthermore, since these devices include a low-pass filter amplifier required for the electronic tuning system and a tuning voltage generator circuit, they can contribute to reduced end product costs through lower parts counts. these ics are optimal for use in low-voltage portable audio equipment that includes a radio receiver. functions ? program memory (rom): ? 8192 16 bits (16 kb) lc72311w ? 16,384 16 bits (32 kb) lc72312w ? 24,576 16 bits (48 kb) LC72313W ? data memory (ram): ? 512 4 bits (ram) ? 512 4 bits (eeprom) ? cycle time: 0.71 s (at 4.2336 mhz) (all 1-word instructions) 40 s (at 75 khz) (all 1-word instructions) ? stack: 8 levels ? lcd driver: 48 to 96 segments (1/4 duty 1/2 bias drive) ? interrupts: two external interrupt systems internal timer interrupts: two systems (1, 5, 10, and 50 ms) serial i/o interrupt (sio0 only) ? a/d converter: four-input 8-bit converter ? input ports: 9 or 10 ports (ports pa, pf, and hctr) the pf port is shared with the a/d converter, and hctr is shared with the if counter. ? output ports: 8 ports (ports pb and pe) pe3 is shared with the beep pin, pe0 to pe2 are open-drain ports, and the pb port can be switched to function as an open-drain port. continued on next page. package dimensions unit: mm 3220-sqfp80 [lc72311w, 72312w, 72313w] 14.0 12.0 1.25 1.25 0.5 14.0 12.0 1.25 1.25 0.5 120 21 40 41 60 61 80 0.1 0.5 1.6max 1.4 0.5 0.2 0.135 sanyo: sqfp80 low-voltage etr-controller lc72311w, 72312w, 72313w cmos ic ordering number : enn ? 7143
lc72311w, 72312w, 72313w no.7143-2/9 continued from preceding page. ? i/o ports: 22 ports (ports pc, pd, pl, pi, pg, and ph) port pd is shared with the interrupt function, ports pc and pk are shared with the serial i/o function, and ports pi, pg, and ph are shared with the lcd segment driver function. ? pll: provides dead band control (4 settings) reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 khz ? input frequencies: fm band: 10 to 230 mhz am band: 0.5 to 10 mhz ? input sensitivity: fm band: 35 mvrms (130 mhz to 50 mvrms) am band: 35 mvrms ? hctr: if counter (0.4 to 15 mhz) ? external reset pin: starts the pc from address 0 during cpu and pll operation. ? built-in power-on reset circuit: starts the pc from address 0 at power on. ? halt mode: temporarily slows the microcontroller operating clock and reduces power consumption. ? backup mode: stops the crystal oscillator circuit. ? static power on: backup mode can be cleared with the pf port. ? beep: seven alarm tones: 0.75, 1.25, 1.5, 2.08, 2.5, 3.125, and 6.25 khz. ? serial i/o: two channels (these functions use the pc and pk port pins.) the internal serial transfer clock provides three frequencies: 12.5, 25, and 75 khz. ? on-chip low-pass filter amplifier: reduces end product parts counts and costs. ? tuning voltage generator circuit: obviates the need for an external tuning power supply circuit for reduced end product parts counts and costs. ? memory retention voltage: over 0.9 v. ? vdd voltage: pll circuit: 1.8 to 3.6 v cpu and a/d converter: 1.6 to 3.6 v (for a 40 s instruction cycle) 2.4 to 3.6 v (for a 0.71 s instruction cycle) ? option selections: ph0 to ph3/s13 to s16 pg0 to pg3/s17 to s20 pi0 to pi3/s21 to s24 vsense circuit present/absent ? package: sqfp80 (0.5 mm lead pitch)
lc72311w, 72312w, 72313w no.7143-3/9 tuning voltage generator circuit 71 67 73 1 80 72 68 1/2 xin xout vdd amin tu fm am pll instruction 1/256 14 v 100 h vddp
lc72311w, 72312w, 72313w no.7143-4/9 specifications absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit v dd max ? 0.3 to +4.0 v maximum supply voltage vddpmax ? 0.3 to +16.0 v input voltage v in all input pins ? 0.3 to v dd + 0.3 v v out 1 aout, pe0 to 2, tu ? 0.3 to +15 v output voltage v out 2 all output pins other than v out 1 ? 0.3 to v dd + 0.3 v i out 1 pc, pd, pe3, pg, ph, pi, pk, pl, eo 0 to 3 ma i out 2 pb 0 to 1 ma i out 3 aout, pe0 to 2, tu 0 to 2 ma i out 4 s1 to s24 300 a output current i out 5 com1 to com4 3 ma allowable power dissipation pdmax ta = ? 20 to + 70 c 300 mw operating temperature topr ? 20 to +70 c storage temperature tstg ? 45 to +125 c allowable operating ranges at ta = ? ? ? ? 20 to + + + + 70 c, v dd = = = = 1.8 to 3.6 v ratings parameter symbol conditions min typ max unit v dd 1 pll operating voltage 1.8 3.0 3.6 v dd 2 memory retention voltage 1.0 v dd 3 cpu operating voltage 1.6 3.0 3.6 v dd 4 a/d converter operating voltage 1.6 3.0 3.6 supply voltage vddp1 voltage applied to the vddp pin 13 14 15 v v ih 1 input ports other than v ih 2, v ih 3, amin, fmin, hctr, xin, and din (with amplifier circuit) 0.7 v dd v dd v v ih 2 bres 0.8 v dd v dd v high-level input voltage v ih 3 the pf port 0.6 v dd v dd v v il 1 input ports other than v il 2, v il 3, amin, fmin, hctr, xin, and din (with amplifier circuit) 0 0.3 v dd v v il 2 bres 0 0.2 v dd v low-level input voltage v il 3 the pf port 0 0.2 v dd v v in 1 xin 0.5 0.6 vrms v in 2 fmin,amin 0.035 0.35 vrms v in 3 fmin 0.05 0.35 vrms input amplitude v in 4 hctr and din (with amplifier circuit) 0.035 0.35 vrms input voltage range v in 6 adi0, adi1, adi2, adi3 0 v dd v f in 1 xin ci 35 k ? 70 75 80 khz f in 2 fmin: v in 2, v dd 1 10 130 mhz f in 3 fmin: v in 3, v dd 1 130 230 mhz f in 4 amin (h): v in 2, v dd 1 2 40 mhz f in 5 amin (l): v in 2, v dd 1 0.5 10 mhz f in 6 hctr: v in 4, v dd 1 0.4 12 mhz f in 7 din (with amplifier circuit): v in 4, v dd 1 2 18 mhz input frequency f in 8 din (without amplifier circuit): v ih 1, v dd 1 2 18 mhz
lc72311w, 72312w, 72313w no.7143-5/9 electrical characteristics in the allowable operating ranges ratings parameter symbol conditions min typ max unit i ih 1 xin: vi = v dd = 3.0 v 3 a i ih 2 fmin, amin, hctr, din (with amplifier circuit): vi = v dd = 3.0 v 3 8 20 a high-level input current i ih 3 the pa/pf (without pull-down resistors), pc, pd, pg, ph, pi, pk, and pl ports, bres, and din (without amplifier circuit): vi = v dd = 3.0 v 3 a i il 1 xin: vi = v dd = v ss ? 3 a i il 12 fmin, amin, hctr, din (with amplifier circuit): vi = v dd = v ss ? 3 -8 ? 20 a low-level input current i il 13 the pa/pf (without pull-down resistors), pc, pd, pg, ph, pi, pk, and pl ports, bres, and din (without amplifier circuit): vi = v dd = 3.0 v ? 3 a input floating voltage v if the pa and pf ports with pull-down resistors 0.05 v dd v r pd 1 the pa and pf ports with pull-down resistors: v dd = 3.0 v 75 100 200 k ? pull-down resistors r pd 2 the test1 and test2 resistor 10 k ? hysteresis v h bres 0.1 v dd 0.2 v dd v voltage doubler reference voltage dbr4 v dd reference c (3) = 0.47 f, ta = 25c (note 1) 1.3 1.5 1.7 v voltage doubler step-up voltage dbr1, 2, 3 c (1) = 0.47 f c (2) = 0.47 f no output load, ta = 25c (note 1) 2.7 3.0 3.3 v v oh 1 pb:io = ? 1 ma v dd ? 0.7 v dd v dd ? 0.3 v dd v v oh 2 pc, pd, pg, ph,pi, pk, pl:io = ? 1 ma v dd ? 0.3 v dd v v oh 3 eo: io = ? 500 a v dd ? 0.3 v dd v v oh 4 xout: io = ? 200 a v dd ? 0.3 v dd v v oh 5 s1 to s24: io = ? 20 a ? 1 2.0 v high-level output voltage v oh 6 com1, com2, com3, com4: io = ? 100 a ? 1 2.0 v v ol 1 pb: io = ? 50 a 0.3 v dd 0.7 v dd v v ol 2 pc, pd, pe3, pg, ph, pi, pk, pl:io = ? 1 ma 0.3 v dd v v ol 3 eo: io = ? 500 a 0.3 v dd v v ol 4 xout: io = ? 200 a 0.3 v dd v v ol 5 s1 to s24: io = ? 20 a ? 1 1.0 v v ol 6 com1, com2, com3, com4: io = ? 100 a ? 1 1.0 v v ol 7 pe0 to 2: io = 2 ma 1.0 v low-level output voltage v ol 8 aout, tu: io = 1 ma ain = 1.3 v v dd = 3 v 0.5 v i off 1 ports pb, pc, pd, pe3, pg, ph, pi, pk, pl, and eo ? 3 +3 a output off leakage current i off 2 aout, tu, and pe0 to pe2 ? 100 +100 na a/d converter error adi0, adi1, adi2, adi3 ? 3/2 +3/2 lsb voltage drop detection voltage v sense 1 ta = 25 c ? 2 1.6 1.75 1.9 v voltage rise detection voltage v sense 2 ta = 25 c ? 2 (1) min + 0.1 (1) max + 0.2 v i dd 1 v dd 1: fin (2) 130 mhz ta = 25 c 10 ma i dd 2 v dd 2: halt mode, ta = 25c ? 3 0.1 ma i dd 3 v dd = 3.6 v, with the oscillator stopped,ta = 25 c ? 4 1 a current drain i dd 4 v dd = 2.4 v, with the oscillator stopped,ta = 25 c ? 4 0.5 a with the halt mode current, this ic can execute 20 instruction steps every 125 ms.
lc72311w, 72312w, 72313w no.7143-6/9 pin assignment vss pe0 pl3 pl2 pl1 pl0 pk0 pi0/s21 pi1/s22 adi3/pf3 adi2/pf2 adi0/pf0 adi1/pf1 pi3/s24 pi2/s23 si1/pk3 so1/pk2 sck1/pk1 pg3/s20 pg2/s19 general-purpose inputs general-purpose unbalanced outputs, od outputs general-purpose i/o and serial i/o od outputs general-purpose inputs, a/d converter inputs general-purpose i/o 1 2 3 4 5 6 7 8 9 10 11 14 15 12 16 13 17 20 18 19 33 32 35 34 36 21 22 23 24 25 28 30 31 29 27 26 37 40 39 38 43 53 47 45 46 44 41 42 49 55 51 52 48 50 54 57 60 58 56 59 61 75 64 62 65 73 66 67 69 68 71 63 72 74 70 77 76 79 78 80 beep/pe3 xout test2 pa3 pa2 pa1 pa0 pb3 pb2 pb1 pb0 pc3/si0 din pc2/so0 pc1/sck0 pc0 pe1 int1/pd1 int0/pd0 pe2 s11 test1 agnd aout ain eo vss amin fmin vdd hctr tu vddp dbr2 dbr1 xin bres dbr3 dbr4 com1 com2 general- purpose i/o general-purpose i/o and serial i/o general-purpose i/o and segment outputs general-purpose output s2 s4 s6 s3 s1 s5 s7 s18/pg1 s17/pg0 s16/ph3 s8 s15/ph2 s13/ph0 s14/ph1 s10 s12 s9 com3 com4 general-purpose i/o and segment outputs general-purpose i/o and segment outputs
lc72311w, 72312w, 72313w no.7143-7/9 pin functions pin no. pin i/o function 80 1 xin xout i o connections for a 75 khz crystal oscillator 79 2 test1 test2 i i ic testing. these pins must be tied to ground. 4 5 6 7 pa3 pa2 pa1 pa0 i general-purpose inputs with built-in pull-down resistors. the pull-down resistors are selected using the ios instruction (ios 2, b1). note that the pull-down resistors cannot be selected individually for each pin. when these inputs are used in conjunction with port pb (unbalanced outputs) to form a key matrix circuit, multiple key presses of up to up to 3 keys can be detected. 8 9 10 11 pb3 pb2 pb1 pb0 o the ios instruction (ios 2, b0, b2, b3) is used to select between the unbalanced output and open drain output circuit types. when the unbalanced type output circuit is selected, these outputs can be used in conjunction with port pa to form a key matrix circuit that can detect multiple key presses. if the general-purpose output function is selected, care is required to prevent problems related to impedance. if the open-drain output circuit is selected, the maximum output voltage will be vdd, and pull-up resistors will be required. 12 13 14 15 pc3/si0 pc2/so0 pc1/sck0 pc0 i/o general-purpose i/o ports and serial i/o ports. the i/o direction of these general-purpose ports can be selected in 1-bit units with the ios instruction (ios 4, b0 to b3). the ios instruction (ios 3, b2) is used to switch between the general-purpose input and the serial i/o functions. 16 17 int1/pd1 int0/pd0 i/o i/o the i/o directions of the pd port pins can be selected in 1-bit units with the ios instruction (ios 5, b1, b2). the pd port pins can be used as interrupt input pins. for this use, the pin i/o direction must be set to input. 18 beep/pe3 o beep output and general-purpose output. the beep instruction is used to switch the pin function. the output circuit is a cmos push-pull circuit. 19 20 21 pe2 pe1 pe0 o n-channel open-drain port. these port pins require pull-up resistors. 22 23 24 25 adi3/pf3 adi2/pf2 adi1/pf1 adi0/pf0 i general-purpose input/a/d converter input shared function port. the ios instruction (ios f, b0 to b3) is used to switch between the general-purpose input and a/d converter input functions. all of these ports can be used to recover from backup mode. the ios instruction (ios 0, b0 to b3) is used to select which ports are used for recovery from backup mode. the a/d converter is an 8-bit successive approximation a/d converter and vdd is the full-scale voltage. 27 28 29 30 pl3 pl2 pl1 pl0 i/o pl0 is a general-purpose i/o port. the i/o direction of these general-purpose port pins can be selected in 1-bit units with the ios instruction (ios b, b0 to b3). 31 32 33 34 si1/pk3 so1/pk2 sck1/pk1 pk0 i/o general-purpose i/o ports. the i/o direction of these general-purpose port pins can be selected in 1-bit units with the ios instruction (ios c, b0 to b3). pk1 to pk3 are general-purpose input or serial i/o ports. the ios instruction (ios 3, b3) is used to switch between the general-purpose input and serial i/o port functions. 35 36 37 38 39 40 41 42 43 44 45 46 pi3/s24 pi2/s23 pi1/s22 pi0/s21 pg3/s20 pg2/s19 pg1/s18 pg0/s17 ph3/s16 ph2/s15 ph1/s14 ph0/s13 i/o lcd driver segment output and general-purpose i/o shared function ports. the ios instruction is used to set the i/o direction for these pins used as general-purpose i/o pins. port pi: ios 8, b0 to b3 port ph: ios 7, b0 to b3 port pg: ios 6, b0 to b3 a combination of mask options and the ios instruction are used to select the segment output and general-purpose port functions. the function can be selected in 1-bit units. port pi: ios d, b0 to b3 port ph: ios c, b0 to b3 port pg: ios b, b0 to b3 continued on next page.
lc72311w, 72312w, 72313w no.7143-8/9 continued from preceding page. pin no. pin i/o function 47 to 58 s12 to s1 o lcd driver segment outputs. this circuit implements a 1/4 duty 1/2 bias lcd drive technique. the frame frequency is 75 hz. an output voltage of 3 v is maintained for vdd in the range 1.8 to 3.6 v. 59 60 61 62 com4 com3 com2 com1 o lcd driver segment outputs. this circuit implements a 1/4 duty 1/2 bias lcd drive technique. the frame frequency is 75 hz. an output voltage of 3 v is maintained for vdd in the range 1.8 to 3.6 v. 63 64 65 66 dbr4 dbr3 dbr2 dbr1 lcd power supply step-up voltage outputs 69 bres i system reset. a system reset is applied if a low level is applied to this pin for at least 1 machine cycle in either cpu operating mode or halt mode. the pc is set to 0 and program execution is started. in backup mode, applying a low level to this pin clears backup mode. 67 tu ? tuning voltage generation circuit. this ic provides an internal transistor, and a circuit that generates the tuning voltage (12 to 14 v) can be formed on this pin with external coil, zener diode, and capacitor components. 72 fmin i fm vco (local oscillator) input. this pin is selected with cw1 in the pll instruction. the input must be capacitor coupled. the input frequency is 10 to 230 mhz. 73 amin i am vco (local oscillator) input. this pin is selected with cw1 in the pll instruction. the input must be capacitor coupled. the input frequency is 0.5 to 10 mhz. 70 hctr i if counter input and general-purpose input shared function pin. the ios instruction (ios 1, b3) is used to switch between these functions. if the if counter is used, use a capacitor-coupled input, and use the ucc instruction to start and stop the counter. the input frequency range is 0.4 to 12 mhz. if the general-purpose input function is used, use the inr instruction to acquire the input data. 75 eo o main charge pump output. if the frequency created by dividing the local oscillator frequency by n is higher than the reference frequency, a high level is output. if that frequency is lower than the reference, a low level is output. if the frequencies match, this pin goes to the high-impedance state. 3 din i clock input from a cd dsp or other ic. the input frequency can be switched between 1/1, 1/2, and 1/4. a frequency range of from 4 to 4.5 mhz is used for the internal clock frequency. this pin can be used to form a self-oscillating circuit by connecting a capacitor. these functions are all switched with the din instruction. 68 vddp the internal eeprom power supply. if the eeprom is used, apply a 14 v level to this pin. the tu pin output can be used for this 14 v level. 76 77 78 ain aout agnd ? connections for the low-pass filter amplifier transistor. connect agnd to ground. 71 26 74 v dd v ss v ss ? power supply.
lc72311w, 72312w, 72313w no.7143-9/9 this catalog provides information as of november, 2001. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo electric co., ltd. strives to s upply high-quality high-reliability products. however, any and all semiconductor products fail with some probability . it is possible that these pr obab ilistic failures could give rise to accidents or events that could endanger human lives , that could give rise to smoke or fire, or that could cause damage to other property. when designing equipmen t, adopt safety measures so tha t these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, of otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subjec t to c hange without notice due to produc t/tec hnology improvemen t, etc. w hen designing equipmen t, refer to the "delivery specification" for the sanyo produc t that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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