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vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 1 of 14 preliminary 48 v input v? chip prm vin range 36 ?75 vdc high density ?438 w/in 3 small footprint ?110 w/in 2 low weight ?0.5 oz (14 g) adaptive loop feedback zvs buck-boost regulator 1.5 mhz switching frequency 96% efficiency 125?c operation p048f048t12al vin = 36 ?75 v v f = 26 ?55 v p f = 120 w i f = 2.5 a v? chip tm ?prm-al pre-regulator module product description the v? chip pre-regulator module (prm) is a very efficient non-isolated regulator capable of both boosting and bucking a wide range input voltage. it is specifically designed to provide a controlled factorized bus distribution voltage for powering downstream v? chip voltage transformation modules (vtms) fast, efficient, isolated, low noise point-of-load (pol) converters. in combination, prms and vtms form a complete dc-dc converter subsystem offering all of the unique benefits of vicors factorized power architecture (fpa): high density and efficiency; low noise operation; architectural flexibility; extremely fast transient response; and elimination of bulk capacitance at the point-of-load (pol). in fpa systems, the pol voltage is the product of the factorized bus voltage delivered by the prm and the "k-factor" (the fixed voltage transformation ratio) of a downstream vtm. the prm controls the factorized bus voltage to provide regulation at the pol. because vtms perform true voltage division and current multiplication, the factorized bus voltage may be set to a value that is substantially higher than the bus voltages typically found in "intermediate bus" systems, reducing distribution losses and enabling use of narrower distribution bus traces. a prm-vtm chip set can provide up to 100 a, or 115 w at a fpa system density of 200 a/in 3 , or 230 w/in 3 ?and because the prm can be located, or "factorized," remotely from the pol, these power densities can be effectively doubled. the prm described in this data sheet features a unique "adaptive loop" compensation feedback: a single wire alternative to traditional remote sensing and feedback loops that enables precise control of an isolated pol voltage without the need for either a direct connection to the load or for noise sensitive, bandwidth limiting, isolation devices in the feedback path. actual size parameter values unit +in to -in -1.0 to 85.0 vdc pc to -in -0.3 to 6.0 vdc pr to -in -0.3 to 9.0 vdc il to -in -0.3 to 6.0 vdc vc to -in -0.3 to 18.0 vdc +out to -out -0.3 to 59 vdc sc to -out -0.3 to 3.0 vdc vh to -out -0.3 to 9.5 vdc os to -out -0.3 to 9.0 vdc cd to -out -0.3 to 9.0 vdc sg to -out 100 ma continuous output current 2.5 adc continuous output power 120 w operating junction temperature (m-grade) -55 to 125 ? (t-grade) -40 to 125 ? storage temperature (m-grade) -65 to 150 ? (t-grade) -40 to 150 ? case temperature during reflow: 208 ? -in pc vc tm +in -out +out vtm +out -out k ro +out ?out +in ?in vc pc tm il vh pr nc sg sc prm-al os nc cd factorized bus (v f ) vin vout the p048f048t12al is used with any 048 input series vtm to provide a regulated and isolated output. dc-dc converter absolute maximum ratings prm
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 2 of 14 preliminary overview of adaptive loop compensation adaptive loop compensation, illustrated in figure 1, contributes to the bandwidth and speed advantage of factorized power. the prm monitors its output current and automatically adjusts its output voltage to compensate for the voltage drop in the output resistance of the vtm. r os sets the desired value of the vtm output voltage, vout; r cd is set to a value that compensates for the output resistance of the vtm (which, ideally, is located at the point of load). for selection of r os and r cd , refer to table 1 below or page 9. the v? chips bi-directional vc port : 1. provides a wake up signal from the prm to the vtm that synchronizes the rise of the vtm output voltage to that of the prm. 2. provides feedback from the vtm to the prm to enable the prm to compensate for the voltage drop in vtm output resistance, r o . -in pc vc tm +in -out +out vtm +out -out k ro +out ?out +in ?in vc pc tm il vh pr nc sg sc prm-al os nc cd l o a d factorized bus (v f ) vo = v l 1.0% ( io?ro ) k v f = v l + k vin r os r cd output power designator (=p f /10) p 048 f 048 t 12 al pre-regulator module input voltage designator product grade temperatures (?) grade storage operating t -40 to150 -40 to125 m -65 to150 -55 to125 configuration (fig.21) nominal factorized bus voltage al = adaptive loop desired load voltage (vdc) vtm p/n (1) max vtm output current (a) (2) r os (k ) (3) r cd ( ) (3) 1.0 v048f015t100 100 3.57 26.1 1.2 v048f015t100 100 2.94 32.4 1.5 v048f015t100 100 2.37 39.2 1.8 v048f020t080 80 2.61 35.7 2.0 v048f020t080 80 2.37 39.2 3.3 v040f033t060 60 2.89 32.6 5.0 v048f060t040 40 2.87 33.2 10 v048f120t025 25 2.86 32.9 12 v048f120t025 25 2.37 39.2 15 v048f160t019 18.8 2.49 37.4 24 v048f240t012 12.5 2.37 39.2 28 v048f320t009 9.4 2.74 35.7 36 v048f480t006 6.3 3.16 30.1 48 v048f480t006 6.3 2.37 39.2 table 1 ?configure your chip set using the prm-al note: (1) verify the configuration option and product grade temperature before ordering as shown above. (2) see ?rm output power vs. vtm output power?on page 10 (3) 1% precision resistors recommended figure 1 ?with adaptive loop control, the output of the vtm is regulated over the load current range with only a single interconnect be tween the prm and vtm and without the need for isolation in the feedback path. general specifications v? chip pre-regulator module part numbering
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 3 of 14 preliminary parameter min typ max unit note input voltage range 36 48 75 vdc input dv/dt 1 v/? input undervoltage turn-on 33.8 35.3 vdc input undervoltage turn-off 30.5 31.8 vdc input overvoltage turn-on 75.8 77.3 vdc input overvoltage turn-off 78.8 81.0 vdc input quiescent current 0.5 1 ma pc low input current 2.6 adc input reflected ripple current 280 ma p-p see figures 4 & 5 no load power dissipation 2 4 w internal input capacitance 5 f ceramic recommended external input capacitance 100 ? see figure 5 for input filter circuit. source impedance dependent input specs (conditions are at 48 vin, 48 vf, full load, and 25? ambient unless otherwise specified) figure 3 ?vf turn-on waveform with inrush current ?pc enabled at full load, 48 vin figure 2 ?vf and pc response from power up figure 4 ?input reflected ripple current at full load and 48 vin input waveforms +in ?in +out ?out +in ?in vc pc tm il vh pr nc sg sc prm-al os nc cd 100 f al-electrolytic reflected ripple measurement 2.37 k + out ? out 10 a figure 5 ?input filter capacitor recommendation electrical specifications v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 4 of 14 preliminary parameter min typ max unit note output voltage range 26 48 55 vdc factorized bus voltage (vf) set by r os output power 0 120 w output current 0 2.5 adc dc current limit 2.6 3.0 3.3 adc i l pin floating average short circuit current 0.5 a auto recovery set point accuracy 1.5 % line regulation 0.1 0.2 % low line to high line load regulation 0.1 0.2 % no cd resistor load regulation (at vtm output) 1.0 2.0 % adaptive loop current share accuracy 5 10 % efficiency full load 95.6 % see figure 6,7 & 8 output overvoltage set point 56 59.4 vdc output ripple voltage no external bypass 1.0 2.0 % factorized bus, see figure 13 with 10 ? capacitor 0.5 1.0 % factorized bus, see figure 14 switching frequency 1.35 1.45 1.55 mhz fixed frequency output turn-on delay from application of power 200 300 ms see figure 2 from pc pin high 100 ? see figure 3 internal output capacitance 5 f ceramic factorized bus capacitance 47 ? output specs (conditions are at 48 vin, 48 vf, full load, and 25? ambient unless otherwise specified) electrical specifications (continued) v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 5 of 14 preliminary efficiency vs. output current 60 65 70 75 80 85 90 95 100 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 output current (a) efficiency (%) 36v 48v 75v vin figure 8 ?efficiency vs. output current at 26 vf electrical specifications (continued) v? chip pre-regulator module efficiency vs. output current 75 80 85 90 95 100 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 output current (a) efficiency (%) 36v 48v 75v vin figure 6 ?efficiency vs. output current at 48 vf efficiency vs. output current 70 75 80 85 90 95 100 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 output current (a) efficiency (%) 26v 48v 75v vin figure 7 ?efficiency vs. output current at 36 vf efficiency graphs
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 6 of 14 preliminary figure 10 ?transient response; prm alone, 36 vin, 0 2.5 ?0 a no load capacitance. local loop figure 9 ?transient response; prm alone, 48 vin, 0 2.5 ?0 a no load capacitance. local loop figure 11 ?transient response; prm alone, 26 vin, 0 2.5 ?0 a no load capacitance. local loop figure 12 ?pc during fault ?frequency will vary as a function of line voltage. figure 14 ?output ripple full load 10? bypass capacitance. vf = 48 vdc figure 13 ?output ripple full load no bypass capacitance. vf = 48 vdc
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 7 of 14 preliminary auxiliary pins (conditions are at 48 vin, 48 vf, full load, and 25? ambient unless otherwise specified) parameter min typ max unit note vc (vtm control) peak voltage 12 14 18 v referenced to ?ut pc (primary control) dc voltage 4.8 5.0 5.2 vdc referenced to ?n module disable voltage 2.3 2.4 vdc referenced to ?n module enable voltage 2.5 2.6 vdc disable hysteresis 100 mv source only after start up; not to be used for current limit 1.75 1.90 ma aux. supply; 100 k minimum load impedance to assure start up. enable delay time 100 ? disable delay time 1 s il (current limit adjust) voltage 1 v accuracy 15 % based on dc current limit set point pr (parallel port) voltage 0.6 7.5 v referenced to sg source current 1 ma external capacitance 100 pf vh (auxiliary voltage) range 8.7 9.0 9.3 vdc maximum source = 5 ma, referenced to sg regulation 0.04 %/ma sc (secondary control) voltage 1.22 1.24 1.26 vdc referenced to sg internal capacitance 0.1 ? external capacitance 0.7 ? os (output set) set point accuracy 1.5 % includes 1% external resistor reference offset 4 mv cd (compensation device) external resistance 20 omit resistor for regulation at output of prm parameter min typ max unit note mtbf mil-hdbk-217f 2.2 mhrs 25?, gb agency approvals (pending) ct?vus ul/csa 60950, en60950 ce mark low voltage directive mechanical parameters see mechanical drawing, figure 19 weight 0.5 / 14 oz / g dimensions length 1.26 / 32 in / mm width 0.87 / 22 in / mm height 0.25 / 6,2 in / mm general specs electrical specifications (continued) v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 8 of 14 preliminary pin / control functions v? chip pre-regulator module +in / -in dc voltage ports the v? chip maximum input voltage should not be exceeded. prms have internal over / undervoltage lockout functions that prevent operation outside of the specified input range. prms will turn on when the input voltage rises above its undervoltage lockout. if the input voltage exceeds the overvoltage lockout, prms will shut down until the overvoltage fault clears. pc will toggle indicating an out of bounds condition. +out / -out factorized voltage output ports these ports provide the factorized bus voltage output. the ?ut port is connected internally to the ?n port through a current sense resistor. the prm has a maximum power and a maximum current rating and is protected if either rating is exceeded. do not short ?ut to ?n. vc ?vtm control the vtm control (vc) port supplies an initial v cc voltage to downstream vtms, enabling the vtms and synchronizing the rise of the vtm output voltage to that of the prm. the vc port also provides feedback to the prm to compensate for voltage drop due to the vtm output resistance. the prms vc port should be connected to the vtm vc port. a prm vc port can drive a maximum of two (2) vtm vc ports. pc ?primary control the prm voltage output is enabled when the pc pin is open circuit (floating). to disable the prm output voltage, the pc pin is pulled low. open collector optocouplers, transistors, or relays can be used to control the pc pin. when using multiple prms in a high power array, the pc ports should be tied together to synchronize their turn on. during an abnormal condition the pc pin will pulse (fig.12) as the prm initiates a restart cycle. this will continue until the abnormal condition is rectified. the pc should not be used as an auxiliary voltage supply, nor should it be switched at a rate greater than 1 hz. tm ?factory use only il ?current limit adjust the prm has a preset, maximum, current limit set point. the il port may be used to reduce the current limit set point to a lower value. see ?djusting current limit?on page 10. pr ?parallel port the pr port signal, which is proportional to the prm output power, supports current sharing among prms. to enable current sharing, pr ports should be interconnected. bypass capacitance should be used when interconnecting pr ports and steps should be taken to minimize coupling noise into the interconnecting bus. please consult vicor applications engineering regarding additional considerations. vh ?auxiliary voltage vh is a gated, non-isolated, nominally 9 volt, regulated dc voltage (see ?uxiliary pins?specifications, on page 7) that is referenced to sg. vh may be used to power external circuitry having a total current consumption of no more than 5 ma. sc ?secondary control the load voltage may be controlled by connecting a resistor or voltage source to the sc port. the slew rate of the output voltage may be controlled by controlling the rate-of-rise of the voltage at the sc port (e.g., to limit inrush current into a capacitive load). sg ?signal ground this port provides a low inductance kelvin connection to ?n and should be used as reference for the os, cd, sc,vh and il ports. os ?output set the application-specific value of the factorized bus voltage (vf) is set by connecting a resistor between os and sg. resistor value selection is shown in table 1 on page 2, and described on page 9. if no resistor is connected, the prm output will be approximately one volt. if set resistor is not colocated with the prm a load bypass capacitor of ~200 pf may be required. cd ?compensation device adaptive loop control is configured by connecting an external resistor between the cd port and sg. selection of an appropriate resistor value (see equation 2 on page 9 and table 1 on page 2) configures the prm to compensate for voltage drops in the equivalent output resistance of the vtm and the prm-vtm distribution bus. if no resistor is connected to cd, the prm will be in local loop mode and will regulate the +out / ?ut voltage to a fixed value. figure 15 ?prm pin configuration bottom view 4 3 2 1 +out ?out +in ?in vc pc tm il vh pr nc sg sc os nc cd a b c d e f g h j k l m n p al version a b c d e f g h j k l m n p signal name bga designation +in g1-k1,g2-k2 ?n l1-p1, l2-p2 vc a1,a2 pc b1, b2 tm c1, c2 il d1, d2 pr f1, f2 vh a3, a4 sc b3, b4 sg c3, c4 os d3, d4 cd f3, f4 +out g3-k3, g4-k4 ?ut l3-p3, l4-p4
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 9 of 14 preliminary l o a d -in pc vc tm +in -out +out vtm +out -out k ro +out ?out +in ?in vc pc tm il vh pr nc sg sc prm-al os nc cd factorized bus (v f ) ( i l ?ro ) k v f = v l + k vin r os r cd 0.4 h output voltage setting with adaptive loop the equations for calculating r os and r cd to set a vtm output voltage are: 93100 r os = ( v l ? 0.8395 ) ? 1 (1) k r cd = 91238 + 1 (2) r os v l = desired load voltage v out = vtm output voltage k = vtm transformation ratio (available from appropriate vtm data sheet) v f = prm output voltage, the factorized bus (see figure 16) r o = vtm output resistance (available from appropriate vtm data sheet) i l = load current (actual current delivered to the load) output voltage trimming (optional) after setting the output voltage from the procedure above the output may be margined down (26vf min) by a resistor from sc-sg using this formula: r d = 10000 v fd v fs - v fd where v fd is the desired factorized bus and v fs is the set factorized bus. a low voltage source can be applied to the sc port to margin the load voltage in proportion to the sc reference voltage. an external capacitor can be added to the sc port as shown in figure 16 to control the output voltage slew rate for soft start. figure 16 ?adaptive loop compensation with soft start using the sc port. nominal vout vtm range (vdc) k factor 0.8 ? 1.6 1/32 1.1 ? 2.2 1/24 1.6 ? 3.3 1/16 2.2 ? 4.4 1/12 3.3 ? 6.6 1/8 4.3 ? 8.8 1/6 6.5 ? 13.4 1/4 8.7 ? 17.9 1/3 13.0 ? 26.9 1/2 17.4 ? 36.0 2/3 26.0 ? 54.0 1 table 2 ?048 input series vtm k factor selection guide application information v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 10 of 14 preliminary application information (continued) v? chip pre-regulator module ovp ?overvoltage protection the output overvoltage protection set point of the p048f048t12al is factory preset for 56 v. if this threshold is exceeded the output shuts down and a restart sequence is initiated, alos indicated by pc pulsing. if the condition that causes ovp is still present, the unit will again shut down. this cycle will be repeated until the fault condition is removed. the ovp set point may be set at the factory to meet unique high voltage requirements. prm output power versus vtm output power as shown in figure 17, the p048f048t12al is rated to deliver 2.5 a maximum, when it is delivering an output voltage in the range from 26 v to 48 v, and 120 w, maximum, when delivering an output voltage in the range from 48 v to 55 v. when configuring a prm for use with a specific vtm, refer to the appropriate vtm data sheet. the vtm input power can be calculated by dividing the vtm output power by the vtm efficiency (available from the vtm data sheet). the input power required by the vtm should not exceed the output power rating of the prm. the factorized bus voltage should not exceed an absolute limit of 55 v, including steady state, ripple and transient conditions. exceeding this limit may cause the internal ovp set point to be exceeded. parallel considerations the pr port is used to connect two or more prms in parallel to form a higher power array. when configuring arrays, pr port interconnection bypass capacitance must be used at ~1nf per prm. additionally one prm should be designated as the master while all other prms are set as slaves by shorting their sc pin to sg. the pc pins must be directly connected (no diodes) to assure a uniform start up sequence. the factorized bus should be connected in parallel as well. adjusting current limit the current limit can be lowered by placing an external resistor between the i l and sg ports (see figure 18 for resistor values). with the i l port open-circuit, the current limit is preset to be within the range specified in the output specifications table on page 4. input fuse recommendations a fuse should be incorporated at the input to the prm, in series with the +in port. a fast acting fuse, nano2 fuse 451/453 series 10 a 125 v, or equivalent, may be required to meet certain safety agency conditions of acceptability. always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. product safety considerations if the input of the prm is connected to selv or elv circuits, the output of the prm can be considered selv or elv respectively. if the input of the prm is connected to a centralized dc power system where the working or float voltage is above selv, but less than or equal to 75 v, the input and output voltage of the prm should be classified as a tnv-2 circuit and spaced 1.3 mm from selv circuitry or accessible conductive parts according to the requirements of ul60950, csa 22.2 60950, en60950, and iec60950. applications assistance please contact vicor applications engineering for assistance, 1-800-927-9474, or email at apps@vicr.com. 1.00 10.00 100.00 0.5 1 1.5 2 2.5 desired prm output current limit (a) resistance (k ) figure 18 ?calculated external resistor value for adjusting current limit, actual value may vary. 26 30 34 38 42 46 50 54 factorized bus voltage (v f ) 2.30 2.35 2.40 2.45 2.50 2.55 current (a) 28 32 36 40 44 48 52 2.25 2.20 2.15 60 20 ~ ~ 0 22 24 56 58 safe operating area figure 17 ?p048f048t12al rating based on factorized bus voltage
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 11 of 14 preliminary 20,00 0.787 24,00 0.945 28,00 1.102 8,10 0.319 26,00 1.024 30,00 1.181 10,00 0.394 15,99 0.630 3,01 0.118 3,01 0.118 1,10 0.043 22,00 0.866 15,55 0.612 0,45 0.020 bottom view output input 6,2 0.25 22,0 0.87 32,0 1.26 output input top view (component side) (12) x (2) x (2) x (2) x (4) x c l (2) x (2) x (2) x (2) x c l notes: 1- dimensions are . 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] 3- product marking on top surface dxf and pdf files are available on vicorpower.com inch mm figure 19 prm j-lead mechanical outline; onboard mounting notes: 1- dimensions are . 2- unless otherwise specified, tolerances are: .x/[.xx] = +/-0.25/[.01]; .xx/[.xxx] = +/-0.13/[.005] dxf and pdf files are available on vicorpower.com inch mm 20,00 0.787 24,00 0.945 28,00 1.102 8,48 0.334 15,96 0.628 22,00 0.866 26,00 1.024 30,00 1.181 10,00 0.394 15,74 0.620 3,26 0.128 3,26 0.128 1,38 0.054 0,51 0.020 1,48 0.058 -in +in pr nc il tm pc vc -out +out (component side show) recommended land pattern sg sc vh nc os cd typ typ (4) x (4) x (4) x (8) x (4) x (4) x (4) x (4) x (24) x figure 20 ?prm j-lead pcb land layout information; onboard mounting mechanical specifications (continued) v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 12 of 14 preliminary configuration options v? chip pre-regulator module configuration onboard (1) onboard with 0.25" (figure 21) heat sink (2) effective power density 875 w/in 3 437 w/in 3 effective junction-board 2.4 ?/w 2.4 ?/w thermal resistanc effective junction-case 1.1 ?/w n/a thermal resistance effective junction-ambient 6.8 ?/w 5.0 ?/w thermal resistance 300lfm note: (1) surface mounted to a 2" x 2" fr4 board, 4 layers 2 oz cu (2) heat sink available as a separate item standard mount 22.0 0.87 32.0 1.26 6.3 0.25 figure 21 ?tandard mounting ?package f mm in figure 22 ?ole location for push pin heatsink relative to vic symbol parameter min typ max unit note over temperature shutdown 125 135 140 ? junction temperature thermal capacity 0.61 ws/? r jc junction-to-case thermal impedance 1.1 ?/w r jb junction-to-board thermal impedance 2.1 ?/w r ja junction-to-ambient (1) 6.5 ?/w r ja junction-to-ambient (2) 5.0 ?/w thermal notes: (1) p048f048t12al surface mounted to a 2" x 2" fr4 board, 4 layers 2 oz cu, 300 lfm. (2) p048f048t12al with a 0.25"h heatsink surface mounted on fr4 board, 300 lfm.
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 page 13 of 14 preliminary v? chip soldering recommendations v? chip modules are intended for reflow soldering processes. the following information defines the processing conditions required for successful attachment of a v? chip to a pcb. failure to follow the recommendations provided can result in aesthetic or functional failure of the module. storage v? chip modules are currently rated at msl 5. exposure to ambient conditions for more than 48 hours requires a 24 hour bake at 125? to remove moisture from the package. solder paste stencil design solder paste is recommended for a number of reasons, including overcoming minor solder sphere co-planarity i ssues as well as simpler integration into overall smd process. 63/37 snpb, either no-clean or water-washable, solder paste should be used. pb-free development is underway. the recommended stencil thickness is 6 mils. the apertures should be 20 mils in diameter for the inboard (bga) application and 0.9-0.9:1 for the onboard (j-leaded). pick and place modules should be placed within ? mils. to maintain placement position, the modules should not be subjected to acceleration greater than 500 in/sec 2 prior to reflow. reflow there are two temperatures critical to the reflow process; the solder joint temperature and the modules case temperature. the solder joints temperature should reach at least 220?, with a time above liquidus (183?) of ~30 seconds. the modules case temperature must not exceed 208 ? at anytime during reflow. because of the t needed between the pin and the case, a forced-air convection oven is preferred for reflow soldering. this reflow method generally transfers heat from the pcb to the solder joint. the modules large mass also reduces its temperature rise. care should be taken to prevent smaller devices from excessive temperatures. reflow of modules onto a pcb using air-vac-type equipment is not recommended due to the high temperature the module will experience. inspection solder joints should conform to ipc 12.2 properly wetted fillet must be evident. heel fillet height must exceed lead thickness plus solder thickness. removal and rework v? chip modules can be removed from pcbs using special tools such as those made by air-vac. these tools heat a very localized region of the board with a hot gas while applying a tensile force to the component (using vacuum). prior to component heating and removal, the entire board should be heated to 80-100? to decrease the component heating time as well as local pcb warping. if there are adjacent moisture-sensitive components, a 125? bake should be used prior to component removal to prevent popcorning. v? chip modules should not be expected to survive a removal operation. case temperature, 208oc joint temperature, 220oc 23 9 165 9 1 16 degc 183 soldering time figure 22 ?hermal profile diagram figure 23 ?properly reflowed v? chip j-lead application information v? chip pre-regulator module
vicorpower.com 800-735-6200 v? chip pre-regulator module p048f048t12al rev. 1.0 11/05 vicors comprehensive line of power solutions includes high density ac-dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power supplies, and complete custom power systems. information furnished by vicor is believed to be accurate and reliable. however, no responsibility is assumed by vicor for its use. vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. all sales are subject to vicors terms and conditions of sale, which are available upon request. specifications are subject to change without notice. intellectual property notice vicor and its subsidiaries own intellectual property (including issued u.s. and foreign patents and pending patent applications) relating to the products described in this data sheet. interested parties should contact vicor's intellectual property department. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email vicor express: vicorexp@vicr.com technical support: apps@vicr.com warranty vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. this warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. vicor shall not be liable for collateral or consequential damage. this warranty is extended to the original purchaser only. except for the foregoing express warranty, vicor makes no warranty, express or implied, including, but not limited to, the warranty of merchantability or fitness for a particular purpose. vicor will repair or replace defective products in accordance with its own best judgement. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior authorization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all reshipment charges if the product was defective within the terms of this warranty. information published by vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. per vicor terms and conditions of sale, the user of vicor components in life support applications assumes all risks of such use and indemnifies vicor against all damages.

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