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82546GB gigabit ethernet controller specification update june 6, 200 6 the 8254 6gb gi gabit ethernet c ontroller ma y con t ain des ign defects or erro rs kno w n as errata t hat ma y cause the p r oduct to deviate from published specifications. current characte rized errata are d o cument ed in this specification update. i
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te info rmation in thi s documen t i s p r ov ided in conne ction w i th in te l pr oducts. no licen se , ex press or implied , by estoppel or o t he rw ise , to any inte llectual property rights is g r anted by this do cument. ex cept a s prov ided in intel? s terms and conditi ons of sa le for su ch produ cts, in te l assumes no liabi lity w hatsoev er, and intel disclaim s any e x press or implied w a rranty , relating to sale and/o r use of in tel produ cts in cluding liabil ity or w a rranties rela ting to fitne s s fo r a parti cu lar purpo se, mer c h antabili ty , or infring e m ent of any paten t, copy right or othe r intelle ctual proper ty righ t. in tel pro d u c ts are no t in tende d for use in medi cal, l i fe sav i ng, o r li fe su stai ning appli c ati o n s . intel may make cha nges to specifi c a t io ns a nd p r odu ct de scrip t ion s a t any time, w i thou t no ti ce . designer s must no t rely on the absen ce or char acteri sti cs of any feature s or instruction s mar k ed ?reserv ed? or ?und efined .? int el r e se rves th ese for future defini t ion and sha ll hav e no resp onsi b il ity w hatsoev er for confli cts or i n compa t ibilitie s ari s ing from fu ture change s to them. 82546GB g i gabi t etherne t con t roller may contain de si gn defe c ts or erro r s know n as erra ta w h ich may cause the pr oduct to de v i ate from publi s he d spe c ifi c a t ion s . curr ent char acteri zed e rrata are av ailable on reque st. contact y our local intel sale s offi ce or y our distrib u tor to o b ta i n t h e l a t e s t sp ec i f ic at i o ns an d be f o r e p l ac i n g yo u r p r od u c t o rd er. copies o f documen ts w h ich hav e an o r dering n u mber an d are refe r enced in thi s documen t, or other in tel lite r atu r e may be obtain e d b y calling 1-80 0-548 - 4725 or by v i siting intel? s w eb site a t ht tp: //w w w .intel. com . copy right ? 2002 -2 006, in tel corpora t i on. intel ? i s a trademar k o r reg i stered trad emark of in tel corp orat ion or its su bsid iaries in the uni t ed states and o t her co untrie s . * b r and s and name s may be claimed a s the proper ty of others. ii
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te content s con t ents ............................................................................................................................... .......................... 3 pref a c e ............................................................................................................................... ............................. 5 nomen c l a t u re ............................................................................................................................... ............... 5 co mp o n ent i d entifi c a ti on vi a pro g r a mming i n terfa c e .............................................................. 5 gener a l in form a t i o n ............................................................................................................................... .. 6 82546GB comp onent marking in formation .................................................................................................. 6 summ a r y t a b l e of ch a n g e s .................................................................................................................... 7 codes used in summar y tables .................................................................................................................. 7 specific a t ion ch a n ges .............................................................................................................................. 8 err a t a ............................................................................................................................... ............................... 9 1. lso prem ature descriptor write back ............................................................................................... 9 2. xof f from link partner can pa u s e flow-cont rol ( x on/x off ) t r a n smission .................................. 9 3. transmit descriptor use of rs fo r non-d a ta ( c ont ext & null) descr iptors ......................................... 9 4. message signaled interr upt fe atu r e ma y cor r upt write transactio n s ............................................. 10 5. link establishment or co mmu nication problems in fiber mode whe n link partner d oes not full y co mply w i th the ie ee 802.3 specification .............. 10 6. wakeup packet memor y (wupm ) cleared upon re set ...................................................................... 11 7. unexp e cted rm cp ack packets in asf mode ................................................................................ 11 8. exceeding pci p o wer man ageme n t specification limit of 375ma current d u ring r e set and po w e r stat e transitions ...................................................... 11 9. inbound and out bound rea d s not fully decou pled in pci-x mode .................................................... 11 10. hang in pci-x s ystems due to 2k buffer ove rrun d u ring tr ansmit operation .................................. 12 11. crc er rors due t o rate adaptatio n fif o overflo w in fiber mode ................................................... 12 12. pci-x arbitration interaction w i th particul ar bridge s can result in controller ha ng ........................ 13 13. transmit descrip tors ma y be w r itten back to host, even without the rs bit set ........................... 13 14. legac y t r ansmit descriptor write- back may occur before the packe t data associated w i th t he descri p tor is fetched .................................................. 13 15. pci-x burst writ e transactions to memory mapped register s at non- qw or d- aligned offsets f a il ...................................................................... 14 specific a t ion cl a r ific a t i o ns ................................................................................................................ 15 1. 82546GB p o rts can be disabled individually .................................................................................... 15 doc u ment a t i o n c h a n ges ........................................................................................................................ 16 3
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te revisio n histo r y 82546GB gigabit ethernet contro llers s p ecification update date o f re v i sio n descrip tion a p r il 1, 200 4 initial pu blic rel ease. a d d e d errata # 4 ? 6, spe c cha n ge # 3, a nd s p e c clarifica t io ns # 4 ? 5. a ugust 3, 2004 a dded errat a # 7 ? 9. januar y 10, 200 5 a d d e d errata # 1 0 ? 11 an d sp ec clarificati on #6. remo v e d s p ec chan ges #1 an d 2. remo v e d s p ec clarifica t ion s # 1 and 5. a p r il 25, 20 05 a d d e d c o m pon ent marki ng i n f o rmati on for le ad-fre e de v i c e s . remo v e d s p eci ficati on c h an ge #3. remo v e d s p eci ficati on cl arific ation s #3, #4, a nd #6. jul y 7, 20 05 correcte d sp elli ng o f rmcp i n erratum # 7 . a d d e d erratu m #12. oct ober 6, 2005 a d d e d errata # 1 3 and # 14. a d d e d spec ific ation clarifi cati ons #1. june 6, 2006 a d d e d erratu m #15. 4
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te pref ace this document is an update to pu blis hed specif icat ions. specificat io n doc uments for these products include: ? 82546GB gigabit ethernet c ontrol l er datasheet. ? 82545em, 8254 5 g m, 8254 6eb, 8 2546gb gigabit ethernet co ntrollers design guid e, ap-439. ? 8254x famil y of gigabit etherne t controllers soft wa re developer?s manual + appen dices for 82546GB, 82545em, 82540em, 8254 4 e i/gc this document is intended for h a r d ware s y stem m anufactures and softw a r e develop ers of applications, operating s y st ems or tools. it ma y contain s pecification changes, erra ta, a nd specification cla r ifications. all 82546g b pro duct documents are subject to fre quent revision, and ne w o r der n u m bers w ill apply . ne w documents ma y be a dded. be sure y o u hav e the latest infor m ation before fin a lizing y our design. nomencl ature specifica tio n c h ang e s are modi fications to the c u rrent p ublished specificat ions. these changes w ill be incorporated in the nex t release of the sp ecifications. errata are desig n defects or er ror s . errata ma y ca use device behavior to deviate fro m published specificat ions. hardw a re and softw a r e designe d to be used w i th an y given steppi ng must assume that all errata d o c umented for th a t stepping are p r esent on al l devices. specifica tio n cl arificati ons d e scribe a specification in greate r det ail or furt her highlight a specificat ion?s impact to a complex design situation. t hese clar ificatio ns w ill be incor p or ated in the nex t r e leas e of the specifications. docu men t ati on chan ges include t y pos, errors, o r omissions from the cu rrent p ublished specification s . these change s w ill be incorporated in t he next release o f the specificatio ns. component identification vi a programming interface 82546g b cont rol l er steppings w ill be identified b y t he follow i ng regi ster contents: steppi ng vendor i d de v i ce id re v i sio n nu mb er 82546GB a 0 8086h 1079h 00h - - - - these devices also provi de identification data throu gh the test access port. 5
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te general information this section covers the 82546 gb devices. 82546GB c o mp onen t m a r k i ng in f o rm a t i o n produc t steppi ng qdf nu mber top m a rkin g notes 8 2 5 4 6 g b a 0 q 7 8 3 fw82546 g b engineering sam p les 8 2 5 4 6 g b a 0 q 5 4 1 nh82546 g b engineering sam p les (lead-f r ee ) 2 5 4 6 g b a 0 - fw82546 g b production 8 2 5 4 6 g b a 0 - nh82546 g b production (lead -fre e) fw82546GB countr y y yw w ? ?03 tnnnnnnnn i ? nh82546GB ? ?03 e1 countr y y yw w tnnnnnnnn i ? lead -free componen t marking 6
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te summary tabl e of changes the follo w i ng tab l e indicates the s pecification changes, errata, sp e c ificat ion clarifications or docum entation chang e s , w h ich a ppl y to the listed 8254 6gb steppings. i n tel intends to fix some of the er ra ta in a future ste pping of the com ponent, and t o a ccount for the other outstandin g issues through documentati on o r specification changes as noted. th is table uses the follow i ng no ta tions: co des use d i n summ a r y ta bles x: erratum, specification change o r clar ification that applies to this st epping. doc: document chang e or updat e that w ill be implement ed. fix: this erratum is intended to be fi xe d in a future step ping of the comp onent. fixed: this erratum h a s been previousl y fixed. nofix: there a r e no plans to fix this errat u m. (no mark ) or (blank box): this erratu m is fixed in listed stepping or specific at ion change does not appl y to liste d stepping. shaded: this item is eithe r ne w o r modified from the p r evious version of the document. no. a0 plans specific a t ion cl a r ific a t i o ns page notes 1 x nofix 82546GB p o rts can be disabled individually 15 - no. a0 plans err a t a page notes 1 x nofix lso prem ature descriptor write back 9 - 2 x nofix xof f from link partner can pa u s e flow-cont rol ( x on/x off ) transmission 9 - 3 x nofix transmit descrip tor use of rs fo r non-data (cont e x t & null) descr iptor s 9 - 4 x nofix message signaled interr upt fe atu r e ma y cor r upt write transactions 10 - 5 x n o f i x l i n k establishm ent or comm unication problems in fiber mode when link partn e r does not fully compl y w i th th e ieee 802.3 specification 10 - 6 x nofix wakeup packet memor y (wupm ) cleared upon re set 11 - 7 x nofix unexp e cted rm cp ack packets in asf mode 11 - 8 x nofix exceeding pci p o wer man agem e n t specification l i mit of 375 ma current du rin g reset and po we r state transitions 11 - 9 x nofix inbound and out bound rea d s not fully decou pled in pci-x mode 11 - 10 x nofix hang in pci-x s ystems due to 2k buffer over run du ring transmit operation 12 - 11 x nofix crc er rors due t o rate adaptatio n fif o overflo w in fiber mode 12 - 12 x nofix pci-x arbitration interaction w i th particular bridge s can result in controller ha ng 1 3 - 13 x nofix transmit descriptors ma y be w r itten back to host, even without the rs bit set 1 3 - 14 x nofix legac y t r ansmit descriptor write - back ma y occur before the packet data associated w i th the descriptor is fet c hed 1 3 - 15 x nofix pci-x burst writ e transactions to memor y mappe d registers at non- qw o r d-aligned offsets fail 14 ne w 7
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te spe cification changes no specification changes report e d at this time . 8
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te errata 1. lso premature d escriptor write back problem : for larg e send f e tches o n l y (n ot normal or jum bo fr ames) th e internal dma engi ne w ill decompose the large- send data fetch into a series o f individual requests that are co mp leted sequentially . when all r ead dat a associated w i th the first internal dma request has been fetched, the descriptor is flagged as read y fo r wr iteback. t hough all data asso ciated w i th the entir e lso descr iptor w ill eventually be fetched, the descr iptor writeback ma y o ccur prematu r el y. the device sh ould w a it until all b y tes associated w i th the d a ta descriptor have been completel y fetched bef ore w r iting back t he transmit descr iptor. implica t io n: due to p r ematu r e w r ite back, an operating s y st e m ma y release and reallocate th e buffer, potenti a lly causing buffer r e -use and transmission of incorrect data. w o rkarou nd : utilize a second descriptor to point to the last four b y tes of the large-send transmit data, and ensure that the buffer is not free d to the oper ating s y stem/applicati on until the second descriptor h a s been ma rked as complete via a status w r ite back operation. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 2. xoff from link partner can pau se flow -control (xon/xoff) transmis sion problem : when the 8254 6gb tra n smitter is paused (b y h a ving receiv ed an xof f fro m link partner ), not o n ly is th e transmit of norm a l packets paused, but also of outbound x o n/ xof f fram es re sulting from rec e ive packet buffer levels and flo w - c ontr o l th resholds. no rma lly , partne r ?s xoff p a ckets onl y pause the lan c ontroller fo r a finite time int e rval, after w h ich outbound x o n/xof f ?s due to receive packet-buffer fullnes s are again permitted to be s ent. implica t io n: if the transmitter is paused w hen a receive fifo xof f th reshold is reached, the transmission of x o f f frame s does not occur and receive fifo overrun ma y p o t entially occu r, re sulting in lost pa ckets. this is on ly e x pecte d to be seen w i th a n abnormall y high pause time fro m link partner?s xof f packet(s). w o rkarou nd : receive flow-c ontrol th resholds ma y be tune d / lo w e red based on the expected maximum paus e interval expected f r om link partner?s xoff packet in order t o minimize the likelihood of receive fif o over runs. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 3. transmit descriptor use of rs fo r non-data (context & null) descriptors problem : due to an inter nal logic error in the descriptor in ternal queue, if the internal descriptor queu e becomes completely full of pending descriptor status writeb acks, the descrip tor logic may issue a writeback request w i th an incorrect writeback amount. the internal descrip tor queue m a y accumulate pending writebacks if transmit descriptors that do not directl y re fer to transmit da ta bu ffers (e.g. c ontext o r null descriptors) are submitted w i t h a status-w ritebac k request (rs as serted) and leg a c y wr iteback (sta tus b y te writeback only ) is utilized. implica t io n: due to the invalid internal w r iteba ck request size, t he pci logic ma y hang. w o rkarou nd : ensur e that status- w r i teback r e por t ing ( r s ) is not set on contex t or null descr iptor s . alter nativel y , utilize full- descriptor w r iteb acks (txdctl. wthresh >= 1). t he fo rmer wo rkaround is the recommended alt e rnative. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 9
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te 4. message signaled interrupt featur e may corrupt write transactions problem : the pro b lem is w i th the imple m entation of th e message signaled interr upt ( m si) featur e in the etherne t controller. durin g msi w r ites, the controller should us e the msi me ssage data value in pci configurat ion space. at the same time, for nor m al wr ite transactions ( r e ceived pac ket data and/or descr iptor wr itebacks) , the controller tempor arily stores the d a ta for write tran sacti ons in a sm all memor y until it is granted ow ne rship of the pci/pci-x bus. the e rro r condition occu rs w hen during the msi o peration the cont roller incorrectl y pulls data from the mem o r y storing the dat a w a iting to be written. if the r e are an y write tra n sactions w a iting w hen this occurs, these tra n sactions may b e come corrupte d . this , in turn, ma y cause the n e twork controller to lock up and become un r e sponsive. implica t io n: if the affected products are used w i th an o s that ut ilizes message signal interrupts and no accomm odations are made to mitigate the use of these interrupt s, d a ta in tegrit y issues may occur. w o rkarou nd : for pci s y stems , advertisement of the msi capability c an be turn ed off b y setting the msi disable bit in the eepro m (init control word 2, bit 7). for p c i-x s y st e m s where msi s upport is en umer ated as pa rt of th e pci-x specifica t ion, intel is w o rk ing w i th os vendors to ensure that an y futur e implementations of their opera t ing sy stems ca n detect these products an d avoid using the msi mechanism. fu rthe r details will be communica ted as the y b e come available. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 5. link establishment or communicati on problems in fiber mode when link partner does not fully compl y w i th the ie ee 802.3 specification problem : the follo w i ng minor compliance issues have been di scovered bet w een the tbi/serdes m ode s y mbo l sy nch r onization logic and the ieee specificat ion: - when p r esent ed w i th short seq uences of malfor med c ode gro u p s , the receive s y nchronization logic w i thin the ethernet contr o ller ma y acquire & indicate lin k/ sy n c hronization pre m aturel y o r incor r ectl y - when presented w i th cert ain s hort sequences of malfo r med code gro ups, the logic ma y retain link/sy nchronization indication thr ough the erro r s equence instead of immediately d e tecting and droppin g link/sy nchronization - with some sp ecific erroneous sequences of co de gr oups, the auto-nego tiation logi c may establish link in certain ver y spec ific situations w h er e the specification say s it should not - finally , the receive error detection logic may no t det ect and cou n t some sy mbol errors w hen malf ormed idle patterns are rece ived. implica t io n: if a link par tner is not compliant w i th the ieee 80 2.3 specification in certain ve r y specific w a y s , the 82546 gb controller ma y n o t be able to establish link or communicate prop erl y w i th it. if t h e controller is test ed for strict compliance w i th t he ieee 802.3 s pecification, it m a y fail some of th e clause 36 and clause 37 test cases. ho w e ver, intel h a s performed e x t ensive compatibility testi ng as an integral part of c ontroller hw validation, and continues to do so w i th the late st ethernet devices . to date, th ese issues have not been sho w n to caus e interopera b ility p r oblems w i th an y ethernet devices currentl y in p r od uction. w o rkarou nd : none. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 10
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te 6. wakeup packet memor y (wupm) cleared upon reset problem : the 82 546 gb sp ecifications state that the wakeu p packet memor y (w upm) is not cleared on an y r e set. thi s is incor r e ct. any r e set or power- state tr ansit ion w ill clear the contents of these r egister s. implica t io n: because a po w e r-state tra n sition takes place on w a keu p , the wa keup packet memory w ill alwa y s be cleared before it can be read b y soft ware. this makes the memory effe ctively unable to provide the capability for inspecting the wakeup packet content. w o rkarou nd : there is no w o rk around. wupm w ill be considere d to be defeat ure d for the aff e cted controllers. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 7. unexpected rmcp ack packet s in asf mode problem : according to the rmcp protocol, the response to all rmcp comma nds (except ack ) should be an rmcp ack packet. in asf m ode, the ethe rnet controller r e spo nds to rmcp ac k packets w i th a second ack. implica t io n: an y man ageme n t soft w a re shou ld be a w a r e of t h is behavior and not r e spond to the additional r m cp ack packets. w o rkarou nd : none. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 8. exceeding pci pow e r management sp ecification limit of 375ma current during reset and pow er state transitions problem : during resets an d power state tr ansitions the co ntroller ma y brief l y d r a w more th an 375 ma of current as the digital signal pro c essors in the p h y att e mpt to co nver ge. the e x c e ssive current draw persists for appro x imatel y 100 milliseconds. refer to t he "po w e r spec ifications -- mac/ph y " s e ction of this document for specific values. implica t io n: if an application has current limiting ci rcuitry in place, the etherne t contro ller ma y trigger these safeguards in po w e r - up or duri ng transitions betw e en d0 a nd d3 po w e r states. w o rkarou nd : none. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 9. inbound and outbound reads not fu lly decoupled in pci-x mode problem : if the ethernet controller receives a read as a targ et and signals a split response it w ill not deliver a completion to this read until its entire outstanding read r equ ests have been satisfied. the device should not make the completion of a sequence for w h ich it is the comp le ter contingent upon anothe r de vice complet i ng a sequenc e for w h ich it is a requester. implica t io n: there is a slight sy stem p e rfo r ma nce impact due to th is erratum. pr ocessors may be stalled w h ile the read transaction is outstanding, so the ex tra dela y ma y adversel y affect cpu utilization. if and onl y if a ho st bridge also has a simi lar depen denc y , the p o ssibility of a de adlo ck ex ists. a situa t ion ma y arise w h ere th e b r idge is w a iting f o r the contr o ller to re spond to a d w ord read while the controller is w a iting fo r the bridge to co mplete a block read. w o rkarou nd : none. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 11
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te 10. hang in pci-x sy stems due to 2k bu ffer overrun during transmit operation problem : this ethernet de vice has an er ror in the wa y that it st ores data fr om pci-x read tra n s actions. if the c ontroller is operating in pci-x mode and its read data fi fo fills comple tely the n the device can miscal c ulate the amount of free space in the fif o and lose all of this data. this erratum d o e s not appl y to de vices running in pci mode onl y . implica t io n: if this device ent ers this erratum state, the chip loses 2 kiloby tes of data. the t r ans mit and receive units of the chip w ill hang w a iting for this data w h ich w ill never arrive. no data w ill be corrupt ed. o n ce this has occurred, a reset is required to restore th e de vice to normal operation. if using larger m t us (jumbo fr am es), the chance o f reaching this er ratum state also increases. w o rkarou nd : the issue can occur onl y w hen on e packet is being complet ed and the next being st arted. t heref ore , if the first fragment of eve r y packet is limited in size the ove r flow can b e p r e v ented entirel y. drivers can w o rk aroun d this issue by ensu r ing that the size in the firs t descriptor of ever y packet less than 2016 bytes. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 11. crc error s due to rate adaptati on fifo overflow in fiber mode problem : in tbi mode a nd internal-serde s mode this ethernet device uses a small fifo in it s receive path to compensate for minute difference s betw e en the sp eed of the link pa rtner 's clock and the device's local clock. if the link partner h a s a faster clock, this fifo w ill f ill slow l y du ring a p a cket, and then d r ain during inter-f r ame gaps. the device has an erro r in the w a y that this fi fo e m pties, causing it to w a it several cy cles into the int e r-fr a me gap before it beg ins recovering clock drift. this onl y occurs during ope ration in fiber mode. in te rnal ph y mode used for coppe r applications is unaffected b y this erra tum. implica t io n: if the etherne t de vice is linked to a partner w i th a su bstantially faster clock and multiple frames ar rive in sequence w i th minimal inter-fram e spaci ng, then the device ma y n o t have time to r e cover all of the accumulated drift bet w een f r a m es. the s y nchronization fifo w ill overflow and d r op 4 b y tes of th e packet, which w ill be visib l e as a crc error . the large r the dif f erence bet ween the link partner's clo ck and the ethernet controller ' s clock, the few e r back-to- back frames nee d to be received t o see crc e rro rs. in practice, this w ill be a very rare occurrence f o r t w o reasons. first, most ethernet de vices use clock fr equenc ies near t he center of th e allow ed range, s o the difference bet w e en clocks w ill be small. second, l ong stri ngs of pa ckets w i th minimal inter-frame sp acing are rare on most net w o rks. w o rkarou nd : this erratum m a y be w o rked ar ou nd b y setting a la rger in te r-fra me spacing. specifically , s w itches mu st be configured to an i n ter-f rame gap of at least 144 ns ( 18 s y mbols) for mtus less than 10,000 b y tes or at least 160 ns (20 s y mbols) f o r mtus bet wee n 10,001 and 16, 000 b y t e s. alternatively , a n e w board design coul d use a refer ence clock source w i th a frequ ency nea r the high e nd of the 802.3 standar d's allow ed range. t h is w ould create a situation w h e r e the onl y w a y to t r igger the e rrat u m was for the link partner t o have a faster clock w h ich w ould violate the 802.3 standard. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 12
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te 12. pci-x arbitration inter action with particu l ar bridg es can result in controller hang problem : in pci-x mode, t he 82546 gb arbi tration logic de-a sse rts its req# signal briefly bef ore beginning a t r ansaction. this is permitted b y the pc i-x spe c if icat ion but is not optimal behavior. implica t io n: under a ve r y spe c ific set of circum stances, certain pci-x bridge co mponents might respond to this b ehavior in a w a y tha t hangs t he s y stem. if the pci-x bridge se es the 82546 gb de-asserting re q# then it might choose to immediately d e -a ssert g n t#. the 82546 g b w ill then abandon its at tempt to begin a transaction and re-start its arbitration c y cle. if this cy cle hap pens repeate d l y , t he 82546 gb mi ght be unable to i n itiate pci-x tran sactions. the 8254 6gb int e roper ates w e ll w i th the majorit y of pci-x bridge components. ho w e ve r, the int e l? 31154 pci-x-to -pci-x b r idge exhibits th e behavior described above. s y ste m s that use both components in pci-x mode w ill need to implement one of the follow i ng w o rkarounds. w o rkarou nd : this issue can b e addressed in several wa y s : 1. ope r ate the b u s segment containing the 82546 gb in pci mode. the er ratum d o e s not occur in pci mode. 2. configure t he arbiter in the pci - x bridge to cha nge its arbitration behavior. chan ging something as small as the master on w h ich it parks ca n alter timings enough to avoid the problem. 3. add a prog ra mmable logic device (pld) to yo ur app lication to detect this situation and br eak the deadlock b y changing t he duration of t h e 82546 gb's re q# assertion. for fu rther details on these option s , including sam p le code for a pr ogrammable lo g i c device, see t a -176 ("possible sy ste m hang when u s ing an intel? 82 546g b lan con t roller w i th cert ain pci bridges?). status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 13. transmit descriptors may be written back to host, even without the rs bit set problem : if the rs bit is set on at least some transmit descriptors submitted t o the device, it is possible that some other transmit descriptors w i thout the r s bit set w ill be incorrectl y written back to host memory . implica t io n: the unnecessary descriptor w r ite-backs w ill not cause a func tional issue, but the y m a y result in a sm all amount of unnecessar y h o st bus band w i dt h to be consume d . w o rkarou nd : none. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 14. legacy tr ansmit descriptor write-b ack ma y occur before the packet data associated w i th the descriptor is fetched problem : if a l egac y t ra nsmit operation dir e ctly follo w s a t c p segmentatio n offload t r ansmit operation, the logic ma y incor r e ctl y associ ate the successf ul completion of the tso t ransmit w i th the next des criptor. if the ne xt descriptor is a legac y descriptor, under certain timi ng sc enarios it is possible for the legac y descriptor to be incorrectl y w r itte n back to host memory w i t h the d d bit set . this might occur even though the packet data for the legac y descriptor has not yet been fetched . implica t io n: due to the p r em ature write back, an operating s y st em ma y release and reallocate th e transmit buffer, potentially causing buffer re -use or tr ansmission of incorrect d a ta. w o rkarou nd : utilize at least tw o descriptors for an y legac y t r ans mit oper ation. do not reallocate an y buffe rs associa t ed w i th the transmit oper ation until the last descriptor has b een w r itten b a ck. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 13
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te 15. pci-x burst write transaction s to memor y mapped registers at non-qword- aligned offsets fail problem : the device does not prope rl y ha n d le burst (gr eater than 4 b y tes in length) write tran sactions to its m e mor y mapped re gister space. registers w i th add resses ending in 0x0 o r 0x8 w o rk, but r e g i sters w i th add re sses ending in 0x4 o r 0xc cannot be written. fo r exam ple, a pci-x me mor y w r ite block transaction w r iting 16 b y tes to offset 0x28 00 properl y w r ites to locations 0x 280 0 and 0 x 2808; h o wever, locations 0x2804 an d 0x2808 are not updated. implication: the specification for the device states that memor y -map ped re gisters should onl y b e written 32 bits at a time. software should alw a ys be written to follow this rul e . it is particularly important durin g initialization w h en most of the memor y - m apped register a ccesses take p l ace. unfortuna tely, some platform s might perform write combining, w h ich turn consecutive 32-bit w r ites into a single burst tra n saction. in this case, the registers w i th addresses ending in 0x4 o r 0xc a r e not written. c o mmon areas fo r consecutive adjacent register writes include setup of the larg e register ar ra y s (mta, vf ta, an d rar). work aroun d : if there is platform-level control for a w r ite - combining feature, turn it off. alter natel y , softwar e can be wr itten w i th the possibility of wr ite combining in mind: ? writes to consecutive registers can be followed b y a read t r ansaction, w h ich s hould flush the posted write from an y bridge t hat might perfo r m combining. ? initializat ion of large register arra ys (vfta, mta ) can be perf o rmed in reverse, w r itin g the highest location first and w o rking backw ar d to the l o west. this prev ent s write combining from occurri ng since the writes no longer meet the r u les that allow co mbining. status : intel does not pla n to resolve this erratum in a f u tur e stepping of the 82546GB gigabit ethernet c ontrol l er. 14
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te spe cification clarificati o ns 1. 82546GB ports can be disabled individuall y clarifica t ion : the 8254 6gb all o w s po rts to be d i sabled individually . ho w e ver , if only one po rt is disabled (using the lan disable feature) w h ile the ot her p o rt is left operatio nal, ca re must be taken to ensure that the smbus f eature is not enabled on the disabled port. if the smbus is left enabled on a disabled port the 82546GB m a y pr event the s y stem from booting . 1 5
82546GB gig a bit ethe rnet con t r o ller specific a t ion upd a te docume n tation changes no documentatio n changes repo rt ed at this time . 16

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