application note st75c520 hardware power-up AN918/0597 the st75c520 is a monochip fax component which includes a dsp (digital signal processor), memory (program, coefficients, ram), cpu inter- face (dual port ram) and also an afe (analog front end). in a fax application we assume that two main states could happend : - power off state, - power on state. power off state in the power off state we assume that all the hardware of the fax application is turned off and both dv dd and av dd are equal to 0v and the st75c520 digital inputs are equal to 0v. power on state in the power on state we assume that all the hardware of the fax application is turned on and both dv dd and av dd are equal to +5v. we remen- ber that it is possible to set the st75c520 in a sleep mode to reduce the power consumption when the power supply of the fax equipment is turned on. to do that the cpu will have to send the sleep command to the st75c520. take care that in sleep mode the st75c520 stops all the chip, the oscillator (so it means that the clkout signal will not be actived and the extal/exatl pins will not work). to awake the st75c520 the application will have three possibilities : a) use the reset pin : the st75c520 starts as at power up and will set it6 (interupt 6 in itsrcr register) when the full initialization will be done (the st75c520 is ready to accept a command from the cpu). b) send a low level on the ring input : the st75c520 awakes and starts an initialization and then set it5 (interrupt 5 in itsrcr register) when it is ready to accept a command fro the cpu. c) do a dummy write in the dual port ram with the cpu : the st75c520 will do as for case b). special power down state it can be interesting to reduce to the minimum the power consumption of the fax equipment. to do that the dv dd and av dd will not be provided and all the power supply will be turn off (for the st75c520 and but also for some other component as the cpu ...). in such a case if the dv dd and av dd and all the digital inputs of the st75c520 are equal to 0v we are in the power off state already de- scribed above. but if the dv dd , av dd and all the digital inputs are not equal to 0v (for exemple : 0.3v or 0.6v) the st75c520 boundary scan interface could be dis- turbed when the fax equipment will be turn on : we have to consider that the dsp is used by the fax application with the cpu interface (dual port ram) but that the dsp core can also be used by another way : the boundary scan interface. the purpose of the boundary scan interface function is only to provide a way to access to the dsp core (for dsp software debug) and to do some tests in production. but the boundary scan interface must not be used in the fax application. we remenber that the boundary scan signals are (see data sheet page 4/44) : scin input scclk input scout output bos input eos input mco..mc2 input halt input mci output rdys output ebs input clkout output all the boundary scan interface are sampled on the rising edge of the scclk signal (ebs is not sample and is a static signal). mc0, mc1, mc2 will select the operating mode of dsp core : normal mode, dsp core test... mc0 = mc1 = mc2 = 0 will select the normal mode. as in our case the dv dd , av dd and all the boundary scan interface inputs are not equal to 0v (for exemple 0.3v or 0.6v) a digital noise could appear when the application will turn on the power supply. 1/2
so the boundary scan interface could be selected instead of the dual port ram and some special behaviour could be started (as test of the dsp core). in such a case the cpu will not have the possibility to use the st75c520. to avoid this kind of problem the customer has to connect the boundary scan interface input as indi- cated : - scin to the gnd - eos to the gnd - bos to the gnd - mc0 to the gnd - mc1 to the gnd - mc2 to the gnd - halt to the dv dd (+5v) - ebs to the gnd - scclk to the reset pin the rising edge of the r eset signal w ill set up the boundary scan interface in the right mode and the dsp will be ready to run its software and to communi- cate with the cpu using the dual port ram interface. dsp core afe dpr rom program rom coefficient ram oscillator cpu boundary scan interface : (scin, scclk, mc0, mc1, mc2...) dsp clk sleep mode tx rx enable extal xtal clkout reset pin to dsp core and afe dsp bus reset AN918-02.eps figure 2 : simple block diagram scin bos eos mc0 mc1 mc2 ebs reset scclk halt dv dd +5v s t 7 5 c 5 2 0 AN918-01.eps figure 1 : connection of the boundary scan in- terface input in the fax application here after (see figure 2) is given a simple block diagram of the chip which shows the main parts of the st75c520. information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectroni cs. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. st75c520 hardware power-up application note 2/2
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