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data sheet ics8n3pgdambki-025 revision b may 5, 2010 1 ?2010 integrated device technology, inc. programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer ics8n3pgdambki-025 general description the ics8n3pgdambki-025 is a very versatile programmable lvpecl synthesizer that can be used for otn/sonet to ethernet or 10 gb ethernet to otn/sonet ra te conversions. the conversion rate is pin-selectable and one of the four rates is supported at a time. in the default configuration, an input clock of 161.1328mhz is converted to 25mhz output. the device uses idt?s fourth generation femtoclock ng technology to deliver low phase noise clocks combined with low power consumption. the rms phase jitter at 25mhz output frequency is 0.66ps (12khz - 5mhz integration range). frequency select table features ? fourth generation femtoclock ? next generation (ng) technology ? footprint compatible with 5mm x 7mm differential oscillators ? one differential lvpecl output pair ? clk, nclk input pair can accept the following levels: hcsl, lvds, lvpecl, lvhstl and sstl ? output frequencies: 19.44mhz and 25mhz ? vco range: 2.0ghz ? 2.5ghz ? cycle-to-cycle jitter: 30ps (maximum) ? rms phase jitter, 12khz ? 5mhz: 0.66ps (typical) ? full 3.3v or 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package fsel[1:0] input (mhz) ou tput frequency (mhz) 00 161.1328 25 01 156.25 25 10 161.1328 19.44 11 156.25 19.44 (default) 1 2 3 8 7 6 oe reserved v ee fsel0 fsel1 nclk clk 45 10 9 nq v cc q q nq phase detector pre-divider femtoclock vco n pullup pullup fsel[1:0] oe clk nclk pulldown pullup/pulldown m 2 pin assignment ics8n3pgdambki-025 10-lead vfqfn 5mm x 7mm x 1mm package body k package top view block diagram
ics8n3pgdambki-025 revision b may 5, 2010 2 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. p, m, n divider function table number name type description 1 oe pullup output enable. external pullup required for normal operation. lvcmos/lvttl interface levels. 2 reserved reserve reserved pin. 3v ee power negative supply pin. 4 nclk input pullup/ pulldown inverting differential clock input. v cc /2 default when left floating 5 clk input pulldown non-inverting differential clock input. 6, 7 q, nq output differ ential output pair. l vpecl interface levels. 8v cc power power supply pin. 9 fsel0 input pullup feedback control input. sets the output divider value to one of four values. lvcmos/lvttl interface levels. see frequency select table on page 1. 10 fsel1 input pullup feedback control input. sets the output divider value to one of four values. lvcmos/lvttl interface levels. see frequency select table on page 1. symbol parameter test conditions minimum typical maximum units c in input capacitance 3.5 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? fsel[1:0] p m n input frequency (mhz) output frequency (mhz) 0 0 2 26.0653 84 161.1328 25 0 1 2 27.5200 86 156.25 25 1 0 2 27.5071 114 161.1328 19.44 1 1 (default) 2 28.3668 114 156.25 19.44
ics8n3pgdambki-025 revision b may 5, 2010 3 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at th ese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4c. lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma package thermal impedance, ja 39.2 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 3.135 3.3 3.465 v i ee power supply current 189 ma symbol parameter test conditio ns minimum typical maximum units v cc power supply voltage 2.375 2.5 2.625 v i ee power supply current 182 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v cc = 3.465v 2 v cc + 0.3 v v cc = 2.625v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.465v -0.3 0.8 v v cc = 2.625v -0.3 0.7 v i ih input high current fsel[1:0] v cc = v in = 3.465v or 2.625v 5 a i il input low current fsel[1:0] v cc = 3.465v or 2.625v, v in = 0v -150 a
ics8n3pgdambki-025 revision b may 5, 2010 4 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer table 4d. differential dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: common mode input voltage is defined as the crossing point. table 4e. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs termination with 50 ? to v cc ? 2v. symbol parameter test conditions minimum typical maximum units i ih input high current clk, nclk v cc = v in = 3.465v or 2.625v 150 a i il input low current clk v in = 0v, v cc = 3.465v or 2.625v -5 a nclk v in = 0v, v cc = 3.465v or 2.625v -150 a v pp peak-to-peak voltage 0.15 1.3 v v cmr common mode input voltage; note 1 v ee v cc ? 0.85 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cc ? 1.4 v cc ? 0.9 v v ol output low voltage; note 1 v cc ? 2.0 v cc ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v
ics8n3pgdambki-025 revision b may 5, 2010 5 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer ac electrical characteristics table 5a. ac characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: this parameter is defined in accordance with jedec standard 65. note 2: refer to the phase noise plots. note 3: characterized using rhode schwartz sma100a for input clocks. table 5b. ac characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: this parameter is defined in accordance with jedec standard 65. note 2: refer to the phase noise plots. note 3: characterized using rhode schwartz sma100a for input clocks. symbol parameter test conditio ns minimum typical maximum units f max output frequency 19.44 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 18 30 ps t jit(?) rms phase jitter (random); note 2, 3 integration range: 12khz ? 5mhz 0.66 0.83 ps t r / t f output rise/fall time 20% to 80% 100 500 ps odc output duty cycle 49 51 % symbol parameter test conditio ns minimum typical maximum units f max output frequency 19.44 25 mhz t jit(cc) cycle-to-cycle jitter; note 1 18 30 ps t jit(?) rms phase jitter (random); note 2, 3 integration range: 12khz ? 5mhz 0.66 0.83 ps t r / t f output rise/fall time 20% to 80% 100 500 ps odc output duty cycle 49 51 %
ics8n3pgdambki-025 revision b may 5, 2010 6 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer typical phase noise at 25mhz noise power dbc hz offset frequency (hz)
ics8n3pgdambki-025 revision b may 5, 2010 7 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer typical phase noise at 19.44mhz noise power dbc hz offset frequency (hz)
ics8n3pgdambki-025 revision b may 5, 2010 8 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer parameter measurement information 3.3v lvpecl output load ac test circuit differential input level cycle-to-cycle jitter 2.5v lvpecl output load ac test circuit output duty cycle/pulse width/period rms phase jitter scope qx nqx lvpecl v ee v cc 2v -1.3v 0.165v v cmr cross points v pp v cc v ee nclk clk ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nq q scope qx nqx lvpecl v ee v cc 2v -0.5v 0.125v t pw t period t pw t period odc = x 100% nq q offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power
ics8n3pgdambki-025 revision b may 5, 2010 9 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer parameter measurement in formation, continued output rise/fall time application information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requ ires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a diff erential input to accept single-ended levels 20% 80% 80% 20% t r t f v swing nq q
ics8n3pgdambki-025 revision b may 5, 2010 10 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are exam ples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v hcsl driver figure 2b. clk/nclk input driven by a 3.3v lvpecl driver figure 2d. clk/nclk input driven by a 3.3v lvds driver figure 2f. clk/nclk input driven by an sstl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? sstl 2.5v zo = 60 ? zo = 60 ? 2.5v r1 120 r2 120 r3 120 r4 120 clk nclk 3.3v differential input
ics8n3pgdambki-025 revision b may 5, 2010 11 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer recommendations for unused input pins inputs: lvcmos control pins for the control pins that have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics8n3pgdambki-025 revision b may 5, 2010 12 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low im pedance follower outputs that generate ecl/lvpecl compatible signals. therefore, terminating resistors (dc current path to groun d) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination fi gure 4b. 3.3v lvpec l output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics8n3pgdambki-025 revision b may 5, 2010 13 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer termination for 2.5v lvpecl outputs figure 5a and figure 5b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 5b can be eliminated and the termination is shown in figure 5c. figure 5a. 2.5v lvpecl driver termination example figure 5c. 2.5v lvpecl driver termination example figure 5b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 ? r3 250 ? r2 62.5 ? r4 62.5 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 ? 50 ? r1 50 ? r2 50 ? r3 18 ? + ?
ics8n3pgdambki-025 revision b may 5, 2010 14 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer power considerations this section provides information on power dissipation and junction temperature for the ics8n3pgdambki-025. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8n3pgdambki-025 is the sum of the core power plus the power dissipation in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipation in the load. power (core) max = v cc_max * i ee_max = 3.465v * 189ma = 654.885mw power (outputs) max = 30mw/loaded output pair total power_ max (3.3v, with all outputs switching) = 654.885mw + 30mw = 684.885mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bon d pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 39.2c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.685w * 39.2c/w = 111.9c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 10 lead vfqfn, forced convection ja by velocity meters per second 0 multi-layer pcb, jedec standard test boards 39.2c/w
ics8n3pgdambki-025 revision b may 5, 2010 15 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. the lvpecl output driver circuit and termination are shown in figure 6. figure 6. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. for logic high, v out = v oh_max = v cc_max ? 0.9v (v cc_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cc_max ? 1.7v (v cc_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cc v cc - 2v q1 rl 50
ics8n3pgdambki-025 revision b may 5, 2010 16 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer reliability information table 7. ja vs. air flow table for a 10 lead vfqfn transistor count the transistor count for ic s8n3pgdambki-025 is: 42,520 package dimensions table 8. package dimensions for 10-lead vfqfn ja vs. air flow meters per second 0 multi-layer pcb, jedec standard test boards 39.2c/w vnjr-1 all dimensions in millimeters symbol minimum nominal maximum n 10 a 0.80 0.90 1.00 a1 00.020.05 b1 0.35 0.40 0.45 b2 1.35 1.40 1.45 d 5.00 basic d2 1.55 1.70 1.80 e 7.00 basic e2 3.55 3.70 3.80 e1 1.0 e2 2.54 l1 0.45 0.55 0.65 l2 1.0 1.10 1.20 n 10 n d 2 n e 3 aaa 0.15 bbb 0.10 ccc 0.10
ics8n3pgdambki-025 revision b may 5, 2010 17 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer package outline package outline - k suffix for 10-lead vfqfn note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 8. ccc c plane seating 0.08 c 8 a b c bbb c a b 7 4 index area (d/2 xe/2) (d/2 xe/2) 4 index area aaa c 2x top view 9 aaa c 2x side view bottom view pin#1 id d e e1 e2 a1 nx b1 nx b2 bbb c a b 7 e2 d2 a nx l1 nx l2 0.1mm 0.1mm n-1 n chamfer 1 2 n-1 1 2 n radius n-1 1 2 n aa dd cc bb 4 4 4 4 4 4 bottom view w/type b id bottom view w/type c id bottom view w/type a id there are 3 methods of indicating pin 1 corner at the back of the vfqfn package are: 1. type a: chamfer on the paddle (near pin 1) 2. type b: dummy pad between pin 1 and n. 3. type c: mouse bite on the paddle (near pin 1)
ics8n3pgdambki-025 revision b may 5, 2010 18 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking packa ge shipping packaging temperature 8N3PGDAMBKI-025LF icsdambi025l ?lead-free? 10 lead vfqfn tray -40 c to 85 c 8N3PGDAMBKI-025LFt icsdambi025l ?lead-fr ee? 10 lead vfqfn 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics8n3pgdambki-025 revision b may 5, 2010 19 ?2010 integrated device technology, inc. ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer revision history sheet rev table page description of change date b t3 1 2 frequency select table, corrected default to 19.44mhz output frequency. table 3 divider function table, corrected default in fsel column to = 11 from 00. 5/4/10
ics8n3pgdambki-025 data s heet programmable femtoclock ? ng differential-to-3.3v, 2.5v lvpecl synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2010. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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