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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. 5ghz receiver max2852 19-5010; rev 1; 3/10 ordering information general description the max2852 is a single-chip rf receiver ic designed for 5ghz wireless hdmi applications. the ic includes all circuitry required to implement the complete receiver function and crystal oscillator, providing a fully integrated transmit path, vco, frequency synthesis, and baseband/ control interface. it includes a fast-settling, sigma-delta rf fractional synthesizer with 76hz frequency program - ming step size. the ic also integrates on-chip i/q ampli - tude and phase-error calibration circuits. the receiver includes both an in-channel rssi and an rf rssi. the receiver chip is housed in a small, 68-pin thin qfn leadless plastic package with exposed pad. applications 5ghz wireless hdmi k (whdi) 5ghz fdd backhaul and wimax k features s 5ghz single ieee 802.11a receiver 4900mhz to 5900mhz frequency range 4.5db rx noise figure 70db rx gain-control range with 2db step size, digitally controlled 60db dynamic range receiver rssi rf wideband receiver rssi programmable 20mhz/40mhz rx i/q lowpass channel filters sigma-delta fractional-n pll with 76hz resolution monolithic low-noise vco with -35dbc integrated phase noise 4-wire spi? digital interface i/q analog baseband interface on-chip digital temperature sensor readout complete baseband interface s +2.7v to +3.6v supply voltage s small, 68-pin thin qfn package (10mm x 10mm) * ep = exposed pad. + denotes a lead(pb)-free/rohs-compliant package. spi is a trademark of motorola, inc. hdmi is a trademark of hdmi licensing, llc. wimax is a trademark of wimax forum. typical operating circuit appears at end of data sheet. evaluation kit available part temp range pin-package MAX2852ITK+ -25n c to +85nc 68 thin qfn-ep*
5ghz receiver max2852 2 ______________________________________________________________________________________ stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc_ pins to gnd ................................................ -0.3v to +3.9v rf inputs maximum current: rxrf+, rxrf- to gnd ................................................................ -1ma to +1ma rf outputs: txrf+, txrf- to gnd ..................... -0.3v to +3.9v analog inputs: txbbi+, txbbi-, txbbq+, txbbq-, xtal to gnd .............................................................. -0.3v to +3.9v analog outputs: rxbbi+, rxbbi-, rxbbq+, rxbbq-, rssi, clkout2, vcobyp, cpout+, cpout- to gnd ............................................... -0.3v to +3.9v digital inputs: enable, cs , sclk, din to gnd ... -0.3v to +3.9v digital outputs: dout, clkout to gnd ............ -0.3v to +3.9v short-circuit duration analog outputs ................................................................. 10s digital outputs ................................................................... 10s rf input power .............................................................. +10dbm rf output differential load vswr ........................................ 6:1 continuous power dissipation (t a = +85 nc) 68-pin thin qfn (derate 29.4mw/ n c above +70 n c) .... 2352mw operating temperature range .......................... -25n c to +85nc junction temperature ..................................................... +150nc storage temperature range ............................ -65n c to +160nc lead temperature (soldering, 10s) ................................ +300nc soldering temperature (reflow) ...................................... +260nc dc electrical characteristics (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, enable set according to operating mode, cs = high, sclk = din = low, transmitter in maximum gain, t a = -25 n c to +85n c. power matching and termination for the differential rf output pins using the typical operating circuit . 100mv rms differential i and q signals applied to i/q baseband inputs of transmitters in transmit calibration mode. typical values measured at v cc = 2.85v, lo frequency = 5.35ghz, t a = +25 n c. channel bandwidth is set to 40mhz. pa control pins open circuit, v cc_pa_bias is disconnected.) (note 1) absolute maximum ratings parameter conditions min typ max units supply voltage, v cc 2.7 3.6 v supply current shutdown mode, t a = +25 nc 10 fa clock-out only mode 7.4 11 ma standby mode 60 89 receive mode 135 174 transmit calibration mode, one transmitter is on 214 261 receive calibration mode 268 327 rx i/q output common-mode voltage 0.9 1.1 1.3 v tx baseband input common- mode voltage operating range 0.5 1.1 v tx baseband input bias current source current 10 20 fa logic inputs: enable, sclk, din, cs digital input-voltage high, v ih v cc - 0.4 v digital input-voltage low, v il 0.4 v digital input-current high, i ih -1 +1 fa digital input-current low, i il -1 +1 fa caution! esd sensitive device
5ghz receiver max2852 _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, enable set according to operating mode, cs = high, sclk = din = low, transmitter in maximum gain, t a = -25 n c to +85n c. power matching and termination for the differential rf output pins using the typical operating circuit . 100mv rms differential i and q signals applied to i/q baseband inputs of transmitters in transmit calibration mode. typical values measured at v cc = 2.85v, lo frequency = 5.35ghz, t a = +25 n c. channel bandwidth is set to 40mhz. pa control pins open circuit, v cc_pa_bias is disconnected.) (note 1) ac electrical characteristicsrx mode (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, rf frequency = 5.351ghz, t a = -25 n c to +85n c. lo frequency = 5.35ghz. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low, with power matching at rxrf+ and rxrf- differential ports using the typical operating circuit . receiver i/q output at 100mv rms loaded with 10k i differential load resistance and 10pf load capacitance. the rssi pin is loaded with 10k i load resistance to ground. typical values measured at v cc = 2.85v, channel bandwidths of 40mhz, t a = +25 n c.) (note 1) parameter conditions min typ max units logic outputs: dout, clkout digital output-voltage high, v oh sourcing 1ma v cc - 0.4 v digital output-voltage low, v ol sinking 1ma 0.4 v digital output voltage in shutdown mode sinking 1ma v ol v parameter conditions min typ max units receiver section: rf input to i/q baseband loaded output (includes 50 i to 100i rf balun and matching) rf input frequency range 4.9 5.9 ghz peak-to-peak gain variation over rf frequency range at one temperature 4.9ghz to 5.35ghz 0.3 2.6 db 5.35ghz to 5.9ghz 2.2 5.3 rf input return loss all lna settings -6 db total voltage gain maximum gain; main address 1 d7:0 = 11111111 61 68 db minimum gain; main address 1 d7:0 = 00000000 -2 +0.5 rf gain steps relative to maximum gain main address 1 d7:d5 = 110 -8 db main address 1 d7:d5 = 101 -16 main address 1 d7:d5 = 001 -32 main address 1 d7:d5 = 000 -40 baseband gain range from maximum baseband gain (main address 1 d3:d0 = 1111) to minimum baseband gain (main address 1 d3:d0 = 0000) 27.5 30 32.5 db baseband gain step 2 db rf gain-change settling time gain settling to within q 0.5db of steady state; rxhp = 1 400 ns baseband gain-change settling time gain settling to within q 0.5db of steady state; rxhp = 1 200 ns
5ghz receiver max2852 4 ______________________________________________________________________________________ ac electrical characteristicsrx mode (continued) (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, rf frequency = 5.351ghz, t a = -25 n c to +85n c. lo frequency = 5.35ghz. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low, with power matching at rxrf+ and rxrf- differential ports using the typical operating circuit . receiver i/q output at 100mv rms loaded with 10k i differential load resistance and 10pf load capacitance. the rssi pin is loaded with 10k i load resistance to ground. typical values measured at v cc = 2.85v, channel bandwidths of 40mhz, t a = +25 n c.) (note 1) parameter conditions min typ max units dsb noise figure balun input referred, integrated from 10khz to 9.5mhz at i/q base - band output for 20mhz rf bandwidth maximum rf gain (main address 1 d7:d5 = 111) 4.5 db maximum rf gain - 16db (main address 1 d7:d5 = 101) 15 balun input referred, integrated from 10khz to 19mhz at i/q base - band output for 40mhz rf bandwidth maximum rf gain (main address 1 d7:d5 = 111) 4.5 maximum rf gain - 16db (main address 1 d7:d5 = 101) 15 out-of-band input ip3 20mhz rf channel; two-tone jammers at +25mhz and +48mhz frequency offset with -39dbm/tone -65dbm wanted signal; rf gain = max (main address 1 d7:d0 = 11101001) -13 dbm -49dbm wanted signal; rf gain = max - 16db (main address 1 d7:d0 = 10101001) -5 -45dbm wanted signal; rf gain = max - 32db (main address 1 d7:d0 = 00111111) 11 40mhz rf channel; two-tone jammers at +50mhz and +96mhz frequency offset with -39dbm/tone -65dbm wanted signal; rf gain = max (main address 1 d7:d0 = 11101001) -13 -49dbm wanted signal; rf gain = max - 16db (main address 1 d7:d0 = 10101001) -5 -45dbm wanted signal; rf gain = max - 32db (main address 1 d7:d0 = 00101001) 11 1db gain desensitization by alternate channel blocker blocker at q 40mhz offset frequency for 20mhz rf channel -24 dbm blocker at q 80mhz offset frequency for 40mhz rf channel -24 input 1db gain compression max rf gain (main address 1 d7:d5 = 111) -32 dbm max rf gain - 8db (main address 1 d7:d5 = 110) -24 max rf gain - 16db (main address 1 d7:d5 = 101) -16 max rf gain - 32db (main address 1 d7:d5 = 001) 0 output 1db gain compression over passband frequency range; at any gain setting; 1db compression point 0.63 v p-p
5ghz receiver max2852 _______________________________________________________________________________________ 5 ac electrical characteristicsrx mode (continued) (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, rf frequency = 5.351ghz, t a = -25 n c to +85n c. lo frequency = 5.35ghz. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low, with power matching at rxrf+ and rxrf- differential ports using the typical operating circuit . receiver i/q output at 100mv rms loaded with 10k i differential load resistance and 10pf load capacitance. the rssi pin is loaded with 10k i load resistance to ground. typical values measured at v cc = 2.85v, channel bandwidths of 40mhz, t a = +25 n c.) (note 1) parameter conditions min typ max units baseband -3db lowpass corner frequency main address 0 d1 = 0 9.5 mhz main address 0 d1 = 1 19 baseband filter stopband rejection rejection at 30mhz offset frequency for 20mhz channel 57 70 db rejection at 60mhz offset frequency for 40mhz channel 57 70 baseband -3db highpass corner frequency main address 5 d1 = 1 600 khz main address 5 d1 = 0 10 steady-state i/q output dc error with ac-coupling 50f s after enabling receive mode and toggling rxhp from 1 to 0, averaged over many measurements if i/q noise voltage exceeds 1mv rms , at any given gain set - ting, no input signal, 1-sigma value 2 mv i/q gain imbalance 1mhz baseband output, 1-sigma value 0.1 db i/q phase imbalance 1mhz baseband output, 1-sigma value 0.2 degrees sideband suppression 1mhz baseband output (note 2) 40 db receiver spurious signal emissions lo frequency -75 dbm/ mhz 2 x lo frequency -62 3 x lo frequency -75 4 x lo frequency -60 rf rssi output voltage -20dbm input power 1.75 v baseband rssi slope 19.5 26.5 35.5 mv/db baseband rssi maximum output voltage 2.3 v baseband rssi minimum output voltage 0.5 v rf loopback conversion gain tx vga gain at maximum (main address 9 d9:d4 = 111111); rx vga gain at maximum - 24db (main address 1 d3:d0 = 0101) -6 +2 +10 db
5ghz receiver max2852 6 ______________________________________________________________________________________ ac electrical characteristicsfrequency synthesis (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, frequency = 5.35ghz, t a = -25 n c to +85n c. reference fre- quency = 40mhz, enable = high, cs = high, sclk = din = low. typical values measured at v cc = 2.85v, t a = +25 n c, lo fre- quency = 5.35ghz, t a = +25 n c.) (note 1) ac electrical characteristicstx calibration mode (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, rf frequency = 5.351ghz, t a = -25 n c to +85n c. lo frequency = 5.35ghz. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low, with power matching at txrf+ and txrf- differential ports using the typical operating circuit . 100mv rms sine and cosine signal applied to i/q baseband inputs of transmitter (differential dc-coupled). typical values measured at v cc = 2.85v, channel bandwidths of 40mhz, t a = +25 n c.) (note 1) parameter conditions min typ max units frequency synthesizer rf channel center frequency 4.9 5.9 ghz channel center frequency programming step 76.294 hz closed-loop integrated phase noise loop bw = 200khz, integrate phase noise from 1khz to 10mhz -35 dbc charge-pump output current 0.8 ma spur level f offset = 0 to 19mhz -42 dbc f offset = 40mhz -66 reference frequency 40 mhz reference frequency input levels ac-coupled to xtal pin 800 mv p-p clkout signal level 10pf load capacitance v cc - 0.8 v cc - 0.1 v p-p parameter conditions min typ max units tx i/q input impedance (r||c) minimum differential resistance 100 ki maximum differential capacitance 1.2 pf tx calibration ftone level at tx gain code (main address 9 d9:d4) = 100010 and -15dbc carrier leakage (local address 27 d2:d0 = 110 and main address 1 d3:d0 = 0000) -28 dbv rms tx calibration gain range adjust local address 27 d2:d0 35 db
5ghz receiver max2852 _______________________________________________________________________________________ 7 ac electrical characteristicsmiscellaneous blocks (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, t a = -25 n c to +85n c. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low. typical values measured at v cc = 2.85v, t a = +25 n c.) (note 1) ac electrical characteristicstiming (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, frequency = 5.35ghz, t a = -25 n c to +85n c. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low. typical values measured at v cc = 2.85v, lo frequency = 5.35ghz, t a = +25 n c.) (note 1) parameter conditions min typ max units on-chip temperature sensor digital output code read-out at dout pin through main address 3 d4:d0 t a = +25 nc 17 t a = +85 nc 25 t a = -20 nc 9 parameter symbol conditions min typ max units system timing shutdown time 2 fs maximum channel switching time loop bandwidth = 200khz, settling to within q 1khz from steady state 2 ms maximum channel switching time with preselected vco sub-band loop bandwidth = 200khz, settling to within q 1khz from steady state 56 fs rx turn-on time (from standby mode) measured from cs rising edge, rx gain settles to within 0.5db of steady state 2 fs rx turn-off time (to standby mode) from cs rising edge 0.1 fs 4-wire serial-interface timing (see figure 1) sclk rising edge to cs falling edge wait time t cso 6 ns falling edge of cs to rising edge of first sclk time t css 6 ns din to sclk setup time t ds 6 ns din to sclk hold time t dh 6 ns
5ghz receiver max2852 8 ______________________________________________________________________________________ ac electrical characteristicstiming (continued) (operating conditions, unless otherwise specified: v cc = 2.7v~3.6v, frequency = 5.35ghz, t a = -25 n c to +85n c. reference frequency = 40mhz, enable = high, cs = high, sclk = din = low. typical values measured at v cc = 2.85v, lo frequency = 5.35ghz, t a = +25 n c.) (note 1) note 1: the max2852 is production tested at t a = +25 n c; minimum/maximum limits at t a = +25 n c are guaranteed by test, unless specified otherwise. minimum/maximum limits at t a = -25 n c and +85n c are guaranteed by design and characterization. there is no power-on register settings self-reset; recommended register settings must be loaded after v cc is applied. note 2: for optimal rx and tx quadrature accuracy over temperature, the user can utilize the rx calibration and tx calibration circuit to assist quadrature calibration. parameter symbol conditions min typ max units sclk pulse-width high t ch 6 ns sclk pulse-width low t cl 6 ns last rising edge of sclk to rising edge of cs or clock to load enable setup time t csh 6 ns cs high pulse width t csw 50 ns time between rising edge of cs and the next rising edge of sclk t cs1 6 ns sclk frequency f clk 40 mhz rise time t r 2.5 ns fall time t f 2.5 ns sclk falling edge to valid dout t d 12.5 ns
5ghz receiver max2852 _______________________________________________________________________________________ 9 typical operating characteristics (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) rx mode supply current supply voltage (v) supply current (ma) 3.5 3.4 3.2 3.3 2.8 2.9 3.0 3.1 2.7 133 134 135 136 137 138 139 140 141 132 2.6 3.6 max2852 toc01 t a = +85c t a = -20c t a = +25c rx noise figure vs. vga gain settings (balun input referred) max2852 toc02 rx vga gain settings noise figure (db) 13 12 10 11 3 4 5 6 7 8 9 1 2 5 10 15 20 25 30 35 40 45 0 0 1 4 15 max - 40db max - 32db max - 24db max - 16db max - 8db max rx maximum gain vs. frequency max2852 toc03 frequency (ghz) maximum gain (db) 5.7 5.5 5.3 5.1 30 40 50 60 70 80 20 4.9 5.9 lna = max gain lna = max - 8db lna = max - 16db lna = max - 24db lna = max - 32db lna = max - 40db rx maximum gain vs. temperature and frequency max2852 toc04 frequency (ghz) maximum gain (db) 5.7 5.5 5.3 5.1 63 64 65 66 67 68 69 70 71 62 4.9 5.9 t a = -20c t a = +25c t a = +85c rx gain vs. baseband vga gain baseband vga gain code gain (db) 14 12 8 10 4 6 2 0 10 20 30 40 50 60 70 80 -10 0 16 max2852 toc05 lna = max lna = max - 8db lna = max - 24db lna = max - 32db lna = max - 40db lna = max - 16db rx output v 1db vs. gain setting max2852 toc06 baseband vga gain code output v 1db (v rms ) 14 12 2 4 6 8 1 0 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.20 0 t a = -20c t a = +85c t a = +25c rx evm vs. input power (channel bandwidth = 20mhz) input power (dbm) evm (db) -10 -30 -50 -70 -35 -30 -25 -20 -15 -40 -90 10 max2852 toc07 lna = max lna = max = -8db lna = max = -16db lna = max = -24db lna = max = -32db lna = max = -40db rx evm vs. rx baseband output level max2852 toc08 rx baseband output level (dbv rms ) rx evm (%) -5 -10 -15 -20 -25 2 4 6 8 10 12 0 -30 0 vga gain = 0 vga gain = 2/4/6/8/10/12/14 vga gain = 3/5/7/9/11/13/15 rx evm vs. ofdm jammer power at 20mhz and 40mhz offset frequency with wanted signal at -66dbm max2852 toc09 input power (dbm) rx evm (%) 5 0 -5 -10 -15 -20 -25 -30 -35 2 4 6 8 10 12 14 0 -40 10 20mhz offset 40mhz offset
5ghz receiver max2852 10 _____________________________________________________________________________________ typical operating characteristics (continued) (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) rx emission spectrum at lna input (lna = max gain) max2852 toc10 (dbm) 2.65ghz/div -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 -110 0 26.5 2lo 4lo rx input impedance max2852 toc11 rf frequency (ghz) real part (i) imaginary part (i) 5.80 5.60 5.40 5.20 5.00 -10 0 10 20 30 40 -20 -30 -20 -10 0 10 20 -40 4.80 6.00 max - 32db max - 40db max - 40db max gain max gain max - 32db rx input return loss frequency (mhz) rx input return loss (db) 5700 5500 5300 5100 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 -20 4900 5900 max2852 toc12 lna = max lna = max - 32db lna = max - 40db rx rf rssi output max2852 toc13 rf input power (dbm) rf rssi output voltage (v) -5 -10 -15 -20 -25 -30 -35 -40 -45 0.5 1.0 1.5 2.0 2.5 0 -50 0 low gain, t a = -20c low gain, t a = +25c high gain, t a = +25c high gain, t a = +85c low gain, t a = +85c high gain, t a = -20c rx rf rssi attack time (+40db signal step) max2852 toc14 1.0v/div 1.0v/div 0v 0v 400ns/div d: 280ns @: 192ns d: 1.32v @: 1.84v gain control v rssi rx rf rssi delay time (-40db signal step) max2852 toc15 1.0v/div 1.0v/div 0v 0v 400ns/div d: 216ns @: 128ns d: 1.30v @: 460mv gain control v rssi baseband rssi voltage vs. input power max2852 toc16 rf input power (dbm) baseband rssi output voltage (v) 0 -20 -40 -60 -80 0.5 1.0 1.5 2.0 2.5 3.0 0 -100 20 lna = max - 16db lna = max - 8db lna = max - 32db lna = max - 24db lna = max lna = max - 40db rx baseband rssi +40db step response max2852 toc17 2.7v 0.8v 0v 2.4v 1 s/div d: 460ns @: 440ns d: 1.50v @: 2.30v lna gain control rssi output rx baseband rssi -32db step response max2852 toc18 2.7v 0.6v 0v 2.0v 1 s/div d: 1.18 s @: 1.16 s d: 1.62v @: 480mv lna gain control rssi output
5ghz receiver max2852 ______________________________________________________________________________________ 11 typical operating characteristics (continued) (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) max2852 toc20 frequency (hz) response (db) -35 -135 10k 100m rx lpf 40mhz channel bandwidth response rx lpf 20mhz channel bandwidth group delay max2852 toc21 10k 0 100 100m frequency (hz) group delay (ns) rx lpf 40mhz channel bandwidth group delay max2852 toc22 10k 100m frequency (hz) group delay (ns) 0 100 rx dc offset settling response (-30db rx vga gain step) max2852 toc23 50mv/div 0v rx baseband i/q output 200ns/div ch1 peak to peak: 81.9mv gain-control toggle rx dc offset settling response (+8db rx vga gain step) max2852 toc24 10mv/div 0v 200ns/div ch1 peak to peak: 8.60mv gain-control toggle rx baseband i/q output rx dc offset settling response (+16db rx vga gain step) max2852 toc25 10mv/div 0v 200ns/div ch1 peak to peak: 17.3mv gain-control toggle rx baseband i/q output rx dc offset settling response (+32db rx vga gain step) max2852 toc26 50mv/div 0v 200ns/div ch1 peak to peak: 69.0mv gain-control toggle rx baseband i/q output rx baseband dc offset settling response with rxhp = 1 (max - 40db to max lna gain step) max2852 toc27 10mv/div 0v 10s/div gain-control toggle rx baseband i/q output max2852 toc19 baseband frequency (hz) response (db) -35 -135 10k 100m rx lpf 20mhz channel bandwidth response
5ghz receiver max2852 12 _____________________________________________________________________________________ typical operating characteristics (continued) (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) rx baseband dc offset settling response with rxhp = 0 (max to max - 40db lna gain step) max2852 toc28 50mv/div 0v 10s/div gain-control toggle rx baseband i/q output rx baseband dc offset settling response with rxhp = 1 (max - 40db to max lna gain step) max2852 toc29 10mv/div 0v 10s/div gain-control toggle rx baseband i/q output rx baseband dc offset settling response with rxhp = 0 (max - 40db to max lna gain step) max2852 toc30 50mv/div 0v 10s/div gain-control toggle rx baseband i/q output rx baseband vga settling response (-30db baseband vga gain step) max2852 toc31 0.1v/div 0v 100ns/div gain-control toggle rx baseband i/q output ch1 peak to peak : 652mv rx baseband vga settling response (+4db baseband vga gain step) max2852 toc32 0.1v/div 0v 100ns/div gain-control toggle rx baseband output ch1 peak to peak: 568mv rx baseband vga settling response (+16db baseband vga gain step) max2852 toc33 0.1v/div 0v 100ns/div gain-control toggle rx baseband output ch1 peak to peak: 532mv rx baseband vga settling response (+30db baseband vga gain step) max2852 toc34 0.1v/div 0v 100ns/div gain-control toggle rx baseband output ch1 peak to peak: 800mv clipping negative rx lna settling response (max to max - 40db gain step) max2852 toc35 0.1v/div 0v 100ns/div gain-control toggle rx baseband output d: 130mv @: 132mv ch1 rms: 168mv rx lna settling response (max - 8db to max gain step) max2852 toc36 0.1v/div 0v 100ns/div gain-control toggle rx baseband output d: 130mv @: 132mv ch1 rms: 188mv
5ghz receiver max2852 ______________________________________________________________________________________ 13 typical operating characteristics (continued) (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) rx lna settling response (max - 16db to max gain step) max2852 toc37 0.1v/div 0v 100ns/div rx baseband output d: 130mv @: 132mv gain-control toggle ch1 rms: 176mv rx lna settling response (max - 24db to max gain step) max2852 toc38 0.1v/div 0v 100ns/div rx baseband output d: 130mv @: 132mv ch1 rms: 174mv gain-control toggle rx lna settling response (max - 32db to max gain step) max2852 toc39 0.1v/div 0v 200ns/div rx baseband output d: 130mv @: 132mv ch1 rms: 155mv gain-control toggle rx lna settling response (max - 40db to max gain step) max2852 toc40 0.1v/div 0v 200ns/div rx baseband output d: 130mv @: 132mv ch1 rms: 154mv gain-control toggle histogram: rx i/q gain imbalance max2852 toc41 -800.00m 0 800.00m samples = 3413, avg = -0.015db, stdev = 0.042db 108 0 216 324 432 540 648 histogram: rx i/q phase imbalance max2852 toc42 -2.0000 0 2.0000 samples = 3413, avg = -0.015deg, stdev = 0.042db 30 0 60 90 120 150 180 histogram: rx static dc offset max2852 toc43 -15.0000 0 0 15.0000 samples = 3413, avg = -0.5mv, stdev = 2.14m v 22 44 66 88 110 132 power-on dc offset cancellation with input signal max2852 toc44 2v/div 0.1v/div 0v 0v 1s/div rx enable engage 600khz highpass corner d: 2.14 s @: 2.12 s d: 112mv @: 104mv rx baseband output power-on dc offset cancellation without input signal max2852 toc45 50mv/div rxbb_i 500mv/div rxbb_q 400ns/div rx enable turn-on transient
5ghz receiver max2852 14 _____________________________________________________________________________________ typical operating characteristics (continued) (v cc = 2.8v, f lo = 5.35ghz, f ref = 40mhz, cs = high, sclk = din = low, rf bw = 20mhz, tx output at 50i unbalanced output of balun, t a = +25nc, using the max2852 evaluation kit.) lo frequency vs. differential tune voltage at t a = +25c max2852 toc46 differential tune voltage (v) lo frequency (ghz) 2.0 1.5 1.0 0.5 4.5 5.0 5.5 6.0 6.5 7.0 4.0 0 2.5 lo gain vs. differential tune voltage at t a = +25c max2852 toc47 differential tune voltage (v) lo gain (mhz/v) 2.0 1.5 1.0 0.5 100 200 300 400 500 600 0 0 2.5 lo phase noise at 5350mhz and room temperature max2852 toc48 offset frequency (hz) phase noise (dbc/hz) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -150 1k 10m lo phase noise at 5900mhz and hot temperature max2852 toc49 offset frequency (hz) phase noise (dbc/hz) -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -150 1k 10m max2852 toc50 400s/div 25khz -25khz 0s 3.99ms channel switching frequency settling (4900mhz to 5900mhz, automatic vco sub-band selection) frequency (5khz/div) max2852 toc52 10s/div 25khz -25khz 0s 99.22s channel switching frequency settling (4900mhz to 5900mhz, manual vco sub-band selection) frequency (5khz/div) max2852 toc53 10s/div 25khz -25khz 0s 99.22s channel switching frequency settling (5900mhz to 4900mhz, manual vco sub-band selection) frequency (5khz/div) max2852 toc51 400s/div 25khz -25khz 0s 3.99ms channel switching frequency settling (5900mhz to 4900mhz, automatic vco sub-band selection) frequency (5khz/div)
5ghz receiver max2852 ______________________________________________________________________________________ 15 pin configuration top view tqfn 10mm x 10mm txbbq- cs sclk din 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 17 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c. gnd v cc v cc gnd n.c. v cc v cc v cc v cc_ucx v cc gnd n.c. v cc v cc n.c. v cc v cc_vco byp_vco gnd_vco cpout+ cpout- v cc_dig dout clkout rssi n.c. n.c. n.c. n.c. rxbbi+ rxbbi- rxbbq+ rxbbq- txbbi+ txbbi- txbbq+ rxrf+ v cc_mxr v cc_bb2 rxrf- n.c. v cc_lna txrf- n.c. gnd txrf+ enable n.c. xtal v cc_xtal n.c. n.c. n.c. n.c. v cc_bb1 n.c. n.c. n.c. n.c. n.c. v cc n.c. v cc max2852
5ghz receiver max2852 16 _____________________________________________________________________________________ pin description pin name function 1, 2, 5, 6, 9, 10, 12, 13, 16, 66, 67 v cc supply voltage 3, 8, 11, 14, 19, 22, 35C38, 54, 56C59, 61C65, 68 n.c. no connection 4, 7, 15, 18 gnd ground 17 v cc_ucx transmitter upconverter supply voltage. bypass with a capacitor as close as possible to the pin. 20 txrf- transmitter differential outputs. these pins are in open-collector configuration. they hould be biased at supply voltage with differential impedance terminated at 300 w. 21 txrf+ 23 v cc_lna receiver lna supply voltage. bypass with a capacitor as close as possible to the pin. 24 rxrf- receiver lna differential inputs. inputs are dc-coupled and biased internally at 1.2v. 25 rxrf+ 26 v cc_mxr receiver downconverter supply voltage. bypass with a capacitor as close as possible to the pin. 27 v cc_bb2 receiver baseband supply voltage 2. bypass with a capacitor as close as possible to the pin. 28 txbbi+ transmitter baseband i-channel differential inputs 29 txbbi- 30 txbbq+ transmitter baseband q-channel differential inputs 31 txbbq- 32 cs chip-select logic input of 4-wire serial interface 33 sclk serial-clock logic input of 4-wire serial interface 34 din data logic input of 4-wire serial interface 39 rxbbi+ receiver baseband i-channel differential outputs 40 rxbbi- 41 rxbbq+ receiver baseband q-channel differential outputs 42 rxbbq- 43 rssi receiver signal strength indicator output 44 v cc_vco vco supply voltage. bypass with a capacitor as close as possible to the pin. 45 byp_vco on-chip vco regulator output bypass. bypass with an external 1 f f capacitor to gnd_vco with minimum pcb trace. do not connect other circuitry to this pin. 46 gnd_vco vco ground 47 cpout+ differential charge-pump outputs. connect the frequency synthesizers loop filter between cpout+ and cpout- (see the typical operating circuit ). 48 cpout- 49 v cc_dig digital block supply voltage. bypass with a capacitor as close as possible to the pin. 50 dout data logic output of 4-wire serial interface 51 clkout reference clock buffer output 52 v cc_xtal crystal oscillator supply voltage. bypass with a capacitor as close as possible to the pin.
5ghz receiver max2852 ______________________________________________________________________________________ 17 table 1. operating modes * clkout signal is active independent of spi, and is only dependent on the enable pin. detailed description modes of operation the modes of operation for the max2852 are shutdown, clockout, standby, receive, transmit calibration, rf loopback, and baseband loopback. see table 1 for a summary of the modes of operation. the logic input pin enable (pin 55) and spi main address 0 d4:d2 control the various modes. shutdown mode the max2852 features a low-power shutdown mode. all circuit blocks are powered down, except the 4-wire serial bus and its internal programmable registers. clockout mode in clockout mode, only the crystal oscillator signal is active at the clkout pin. the rest of the transceiver is powered down. standby mode in standby mode, pll, vco, and lo generation are on. rx mode can be quickly enabled from this mode. other blocks may be selectively enabled in this mode. receive (rx) mode in receive mode, all rx circuit blocks are powered on and active. antenna signal is applied; rf is downcon - verted, filtered, and buffered at rx baseband i and q outputs. transmit calibration in transmit calibration mode, all tx circuit blocks are powered on and active. the am detector and receiver i/q channel buffers are also on. output signals are routed to rx baseband i and q outputs. pin description (continued) mode-control logic inputs circuit block states mode enable pin spi main address 0, d4:d2 rx path tx path lo path clkout* calibration sections on shutdown 0 xxx off off off off none clkout 1 000 off off off on none standby 1 001 off off on on none rx 1 010 on off on on none tx calibration 1 100 off on on on am detector + rx i/q buffers rf loopback 1 101 on (except lna) on on on rf loopback baseband loopback 1 11x on (except rxrf) off on on tx 4 baseband buffer pin name function 53 xtal crystal oscillator base input. ac-couple crystal unit to this pin. 55 enable enable logic input 60 v cc_bb1 receiver baseband supply voltage 1. bypass with a capacitor as close as possible to the pin. ep exposed paddle. connect to the ground plane with multiple vias for proper operation and heat dissipation. do not share with any other pin grounds and bypass capacitors ground.
5ghz receiver max2852 18 _____________________________________________________________________________________ microwire is a trademark of national semiconductor corp. the am detector multiplies the tx rf output signal with itself. the self-mixing product of the wanted sideband becomes dc voltage and is filtered on-chip. the mixing product between wanted sideband and the carrier leak - age forms ftone at rx baseband output. the mixing product between the wanted sideband and the unwant - ed sideband forms 2ftone at rx baseband output. rf loopback in rf loopback mode, part of the rx and tx circuit blocks (except the lna) are powered on and active. the transmitter 4 i/q input signal is upconverted to rf, and the output of the transmitter is fed to the receiver down - converter input. output signals are delivered to receiver 4 baseband i/q outputs. the i/q lowpass filters in the transmitter signal path are bypassed. baseband loopback in baseband loopback mode, part of the rx and tx baseband circuit blocks are powered and active. the transmitter 4 iq input signal is routed to receiver lowpass filter input. output signals are delivered to receiver 4 baseband i/q outputs. power-on sequence set the enable pin to v cc for 2ms to start th e crystal oscillator. program all spi addresses according to rec - ommended values. set spi main address 0 d4:d2 from 000 to 001 to engage standby mode. to lock the lo frequency, the user can set spi in order of main address 15, main address 16, and then main address 17 to trig - ger vco sub-band autoacquisition; the acquisition will take 2ms. after the lo frequency is locked, set spi main address 0 d4:d2 = 010 and 011 for rx and tx operat - ing modes, respectively. before engaging rx mode, set main address 5 d1 = 1 to allow fast dc offset settling. after engaging rx mode and rx baseband dc offset settles, the user can set main address 5 d1 = 0 to com - plete rx dc offset cancellation. programmable registers and 4-wire spi interface the max2852 includes 60 programmable 16-bit reg - isters. the most significant bit (msb) is the read/write selection bit (r/w in figure 1). the next 5 bits are register address (a4:a0 in figure 1). the 10 least significant bits (lsbs) are register data (d9:d0 in figure 1). register data is loaded through the 4-wire spi/microwire?- compatible serial interface. msb of data at the din pin is shifted in first and is framed by cs . when cs is low, the clock is active, and input data is shifted at the rising edge of the clock at sclk pin. at the cs rising edge, the 10-bit data bits are latched into the register selected by address bits. see figure 1. to support more than a 32-register address using a 5-bit wide address word, the bit 0 of address 0 is used to select whether the 5-bit address word is applied to the main address or local address. the register values are preserved in shutdown mode as long as the power-supply voltage is maintained. there is no power-on spi register self-reset functionality in the max2852, so the user must program all register values after power-up. during the read mode, register data selected by address bits is shifted out to the dout pin at the falling edges of the clock.
5ghz receiver max2852 ______________________________________________________________________________________ 19 figure 1. 4-wire spi serial-interface timing diagram table 2. register summary spi register definition (all values in the register summary table are typical numbers. the max2852 spi does not have a power-on-default self- reset feature; the user must program all spi addresses for normal operation. prior to use of any untested settings, contact the factory.) sclk t cs o t cs s t ds t dh t ch t cl t cs w t cs h t cs 1 a4 r/w a0 d9 d0 don?t care a0 d9 d0 a4 r/w din (spi write) don?t care don?t care d9 dout (spi read ) din (spi read ) d0 don?t care cs t d register read/write and address data main0_ d0 a4:a0 write (w)/ read (r) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 main0 0 00000 w/r reserved reserved reserved reserved reserved mode<2:0> rfbw m/l_sel default 0 1 0 0 0 0 0 0 1 0 main1 0 00001 w/r reserved reserved lna_gain<2:0> rx_vga<4:0> default 0 0 1 1 1 1 1 1 1 1 main2 0 00010 w/r reserved reserved reserved lna_band<1:0> reserved reserved reserved reserved reserved default 0 1 1 0 1 0 0 0 0 0 main3 0 00011 w reserved reserved ts_en ts_trig reserved reserved reserved reserved reserved reserved r reserved reserved reserved ts_read<4:0> default 0 0 0 0 0 0 0 0 0 0
5ghz receiver max2852 20 _____________________________________________________________________________________ table 2. register summary (continued) register read/write and address data main0_ d0 a4:a0 write (w)/ read (r) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 main4 0 00100 reserved 1 1 0 0 0 1 1 1 0 0 main5 0 00101 w/r reserved rssi_mux_sel<2:0> reserved reserved reserved reserved rxhp reserved default 0 0 0 0 0 0 0 0 0 0 main6 0 00110 reserved 1 1 1 1 1 0 1 0 0 0 main7 0 00111 reserved 0 0 0 0 1 0 0 1 0 0 main8 0 01000 w/r 0 0 0 0 0 0 0 0 0 0 main9 0 01001 w/r tx_gain<5:0> reserved reserved reserved reserved default 0 0 0 0 0 0 1 1 1 1 main10 0 01010 reserved 0 0 0 0 0 0 0 0 0 0 main11 0 01011 w/r reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 1 1 0 1 1 0 0 main13 0 01101 reserved 0 0 0 0 0 0 0 0 0 0 main14 0 01110 w/r reserved reserved reserved reserved reserved reserved reserved reserved dout_sel reserved default 0 1 0 1 1 0 0 0 0 0 main15 0 01111 w/r vas_ trig_en reserved syn_config_n<6:0> default 1 0 0 1 0 0 0 0 1 0 main16 0 10000 w/r syn_config_f<19:10> default 1 1 1 0 0 0 0 0 0 0 main17 0 10001 w/r syn_config_f<9:0> default 0 0 0 0 0 0 0 0 0 0 main18 0 10010 w/r reserved reserved xtal_tune<7:0> default 0 0 1 0 0 0 0 0 0 0 main19 0 10011 w/r reserved reserved vas_ relock_ sel vas_ mode vas_spi<5:0> read vas_adc<2:0> vco_band<5:0> default 0 0 0 1 0 1 1 1 1 1 main20 0 10100 reserved 0 1 1 1 1 0 1 0 1 0 main21 0 10101 read reserved reserved die_id<2:0> reserved reserved reserved reserved reserved default 0 0 1 0 1 1 1 1 1 1 main22 0 10110 reserved 0 1 1 0 1 1 1 0 0 0 main23 0 10111 reserved 0 0 0 1 1 0 0 1 0 1 main24 0 11000 reserved 1 0 0 1 0 0 1 1 1 1 main25 0 11001 reserved 1 1 1 0 1 0 1 0 0 0 main26 0 11010 reserved 0 0 0 0 0 1 0 1 0 1 main27 0 11011 w/r die_id_ read reserved reserved reserved vas_vco_ read reserved reserved reserved reserved reserved default 0 1 1 0 0 0 0 0 0 0 main28 0 11100 w/r reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved default 0 0 0 1 1 0 0 0 1 1
5ghz receiver max2852 ______________________________________________________________________________________ 21 table 2. register summary (continued) register read/write and address data main0_ d0 a4:a0 write (w)/ read (r) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 main29 0 11101 reserved 0 0 0 0 0 0 0 0 0 0 main30 0 11110 reserved 0 0 0 0 0 0 0 0 0 0 main31 0 11111 reserved 0 0 0 0 0 0 0 0 0 0 local1 1 00001 reserved 0 0 0 0 0 0 0 0 0 0 local2 1 00010 reserved 0 0 0 0 0 0 0 0 0 0 local3 1 00011 reserved 0 0 0 0 0 0 0 0 0 0 local4 1 00100 reserved 1 1 1 0 0 0 0 0 0 0 local5 1 00101 reserved 0 0 0 0 0 0 0 0 0 0 local6 1 00110 reserved 0 0 0 0 0 0 0 0 0 0 local7 1 00111 reserved 0 0 0 0 0 0 0 0 0 0 local8 1 01000 reserved 0 1 1 0 1 0 1 0 1 0 local9 1 01001 reserved 0 1 0 0 0 1 0 1 0 0 local10 1 01010 reserved 1 1 0 1 0 1 0 1 0 0 local11 1 01011 reserved 0 0 0 1 1 1 0 0 1 1 local12 1 01100 reserved 0 0 0 0 0 0 0 0 0 0 local13 1 01101 reserved 0 0 0 0 0 0 0 0 0 0 local14 1 01110 reserved 0 0 0 0 0 0 0 0 0 0 local15 1 01111 reserved 0 0 0 0 0 0 0 0 0 0 local16 1 10000 reserved 0 0 0 0 0 0 0 0 0 0 local17 1 10001 reserved 0 0 0 0 0 0 0 0 0 0 local18 1 10010 reserved 0 0 0 0 0 0 0 0 0 0 local19 1 10011 reserved 0 0 0 0 0 0 0 0 0 0 local20 1 10100 reserved 0 0 0 0 0 0 0 0 0 0 local21 1 10101 reserved 0 0 0 0 0 0 0 0 0 0 local22 1 10110 reserved 0 0 0 0 0 0 0 0 0 0 local23 1 10111 reserved 0 0 0 0 0 0 0 0 0 0 local24 1 11000 reserved 0 0 1 1 0 0 0 1 0 0 local25 1 11001 reserved 0 1 0 0 1 0 1 0 1 1 local26 1 11010 reserved 0 1 0 1 1 0 0 1 0 1 local27 1 11011 w/r reserved reserved reserved reserved reserved reserved reserved tx_amd_ bb_gain tx_amd_rf_gain <1:0> default 0 0 0 0 0 0 0 0 0 0 local28 1 11100 reserved 0 0 0 0 0 0 0 1 0 0 local31 1 11111 reserved 0 0 0 0 0 0 0 0 0 0
5ghz receiver max2852 22 _____________________________________________________________________________________ table 3. main address 0: (a4:a0 = 00000) table 4. main address 1: (a4:a0 = 00001, main address 0 d0 = 0) bit name bit location (d0 = lsb) description reserved d9:d5 reserved bits; set to default mode<2:0> d4:d2 ic operating mode select 000 = clockout (default) 001 = standby 010 = rx 011 = do not use 100 = tx calibration 101 = rf loopback 11x = baseband loopback rfbw d1 rf bandwidth 0 = 20mhz 1 = 40mhz (default) m/l_sel d0 main or local address select 0 = main registers (default) 1 = local registers bit name bit location (d0 = lsb) description reserved d9:d8 reserved bits; set to default lna_gain<2:0> d7:d5 lna gain control active when rx channel is selected by corresponding rx_path_unmask<5:1> bits in main address 6 d9:d5. 000 = maximum - 40db 001 = maximum - 32db 100 = maximum - 24db 101 = maximum - 16db 110 = maximum - 8db 111 = maximum gain (default) vga_gain<4:0> d4:d0 rx vga gain control active when rx channel is selected by corresponding rx_path_unmask<5:1> bits in main address 6 d9:d5. 00000 = minimum gain 00001 = minimum + 2db 01110 = minimum + 28db 01111 = minimum + 30db 1xxxx = minimum + 30db (default)
5ghz receiver max2852 ______________________________________________________________________________________ 23 table 5. main address 2: (a4:a0 = 00010, main address 0 d0 = 0) table 6. main address 3: (a4:a0 = 00011, main address 0 d0 = 0) table 7. main address 5: (a4:a0 = 00101, main address 0 d0 = 0) bit name bit location (d0 = lsb) description reserved d9:d7 reserved bits; set to default lna_band<1:0> d6:d5 lna frequency band switch 00 = 4.9ghz~5.2ghz 01 = 5.2ghz~5.5ghz (default) 10 = 5.5ghz~5.8ghz 11 = 5.8ghz~5.9ghz reserved d4:d0 reserved bits; set to default bit name bit location (d0 = lsb) description reserved d9:d8 reserved bits; set to default ts_en d7 temperature sensor enable 0 = disable (default) 1 = enable except shutdown or clockout mode ts_trig d6 temperature sensor reading trigger 0 = not trigger (default) 1 = trigger temperature reading reserved d5 reserved bits; set to default ts_read<4:0> d4:d0 spi readback only. temperature sensor reading. bit name bit location (d0 = lsb) description reserved d9 reserved bits; set to default rssi_mux_sel<2:0> d8:d6 rssi output select 000 = baseband rssi (default) 001 = do not use 010 = do not use 011 = do not use 100 = rx rf detector 101 = do not use 110 = do not use 111 = do not use reserved d5:d2 reserved bits, set to default rxhp d1 rx vga highpass corner select after rx turn-on rxhp starts at 1 during rx gain adjustment, and set to 0 after gain is adjusted. 0 = 10khz highpass corner after rx gain is adjusted (default) 1 = 600khz highpass corner during rx gain adjustment reserved d0 reserved bits; set to default
5ghz receiver max2852 24 _____________________________________________________________________________________ table 8. main address 9: (a4:a0 = 01001, main address 0 d0 = 0) table 9. main address 14: (a4:a0 = 01110, main address 0 d0 = 0) table 10. main address 15: (a4:a0 = 01111, main address 0 d0 = 0) table 11. main address 16: (a4:a0 = 10000, main address 0 d0 = 0) bit name bit location (d0 = lsb) description tx_gain<5:0> d9:d4 tx vga gain control tx channel is selected by main address 9 d3:d0. 000000 = minimum gain (default) 111111 = minimum gain + 31.5db reserved d3:d0 reserved bits; set to default bit name bit location (d0 = lsb) description reserved d9:d2 reserved bits; set to default dout_sel d1 dout pin output select 0 = pll lock detect (default) 1 = spi readback reserved d0 reserved bits; set to default bit name bit location (d0 = lsb) description vas_trig_en d9 enable vco sub-band acquisition triggered by syn_config_f<9:0> (main address 17) programming 0 = disable for small frequency adjustment (i.e., ~100khz) 1 = enable for channel switching (default) reserved d8:d7 reserved bits; set to default syn_config_n<6:0> d6:d0 integer divide ratio 1000010 = default bit name bit location (d0 = lsb) description syn_config_f<19:10> d9:d0 fractional divide ratio lsbs 0000000000 = default
5ghz receiver max2852 ______________________________________________________________________________________ 25 table 14. main address 19: (a4:a0 = 10011, main address 0 d0 = 0) table 12. main address 17: (a4:a0 = 10001, main address 0 d0 = 0) table 13. main address 18: (a4:a0 = 10010, main address 0 d0 = 0) bit name bit location (d0 = lsb) description syn_config_f<19:10> d9:d0 fractional divide ratio lsbs 0000000000 = default bit name bit location (d0 = lsb) description reserved d9:d8 reserved bits; set to default xtal_tune<7:0> d7:d0 crystal oscillator frequency tuning 00000000 = minimum frequency 10000000 = default 11111111 = maximum frequency bit name bit location (d0 = lsb) description reserved d9:d8 reserved bits; set to default vas_relock_sel d7 vas relock select 0 = start at sub-band selected by vas_spi<5:0> (main address 19 d5:d0) (default) 1 = start at current sub-band vas_mode d6 vco sub-band select 0 = by vas_spi<5:0> (main address 19 d5:d0) 1 = by on-chip vco autoselect (vas) (default) vas_spi<5:0> d5:d0 vco autoselect sub-band input select vco sub-band when vas_mode (main address 19 d6) = 0. select initial vco sub-band for autoacquisition when vas_mode = 1. 000000 = minimum frequency sub-band 011111 = default 111111 = maximum frequency sub-band vas_adc<2:0> (readback only) d8:d6 read vco autoselect tune voltage adc output active when vco_vas_rb (main address 27 d5) = 1. 000 = lower than lock range and at risk of unlock 001 = lower than acquisition range and maintain lock 010 or 101 = within acquisition range and maintain lock 110 = higher than acquisition range and maintain lock 111 = higher than lock range and at risk of unlock vco_band<5:0> (readback only) d5:d0 read the current acquired vco sub-band by vco autoselect active when vco_vas_rb (main address 27 d5) = 1.
5ghz receiver max2852 26 _____________________________________________________________________________________ table 15. main address 21: (a4:a0 = 10101, main address 0 d0 = 0) table 16. main address 27: (a4:a0 = 11011, main address 0 d0 = 0) table 17. local address 27: (a4:a0 = 11011, main address 0 d0 = 1) chip information process: bicmos package type package code document no. 68 tqfn-ep t6800+2 21-0142 package information for the latest package outline information and land pat - terns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suf - fix character, but the drawing pertains to the package regardless of rohs status. bit name bit location (d0 = lsb) description reserved d9:d0 reserved bits; set to default die_id<2:0> (readback only) d7:d5 read revision id at main address 21 d7:d5 active when die_id_read (main address 27 d9) = 1. 000 = pass1 001 = pass2 bit name bit location (d0 = lsb) description die_id_read d9 die id readback select 0 = main address 21 d9:d0 reads its own values (default) 1 = main address 21 d7:d5 reads revision id reserved d8:d6 reserved bits, set to default vas_vco_read d5 vas adc and vco sub-band readback select 0 = main address 19 d9:d0 reads its own values (default) 1 = main address 19 d8:d6 reads vas_adc<2:0>; main address 19 d5:d0 reads vco_band<5:0> reserved d4:d0 reserved bits; set to default bit name bit location (d0 = lsb) description reserved d9:d3 reserved bits, set to default tx_amd_bb_gain d2 tx calibration am detector baseband gain 0 = minimum gain (default) 1 = minimum gain + 5db tx_amd_rf_gain d1:d0 tx calibration am detector rf gain 00 = minimum gain (default) 01 = minimum gain + 14db rise at output 1x = minimum gain + 28db rise at output
5ghz receiver max2852 ______________________________________________________________________________________ 27 typical operating circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 max2852 am detector txrf+/- crystal oscillator/buffer txrf+/- amd+/- amd+/- 0? 90? 0? 90? rf rssi bb rssi rssi mux serial interface dout phase-locked loop v cc n.c v cc gnd v cc v cc gnd n.c. v cc v cc v cc v cc n.c. n.c. gnd v cc v cc_ucx n.c. gnd txrf+ txrf- txrf output 2.4nh 4.3nh 1.0pf 1.0nf v cc_ucx n.c. txbbi+ txbbi- txbbq+ txbbq- cs sclk din v cc_lna v cc_mxr v cc_bb2 rxrf- rxrf+ rxrf output 1.3nh 1.0pf 20pf clkout 100pf 1f 10nf 1f 1nf 10nf 1nf 1nf 1nf 1nf 1nf 1nf 1nf 1nf 1nf 10nf 100nf 1nf 0.1f 1nf 1nf dout cpout- cpout+ gnd_vco rssi rxbbq- rxbbq+ rxbbi- rxbbi+ n.c. n.c. n.c. n.c. byp_vco v cc_dig v cc_vco 33pf 2.2nf 390 i pll loop filter 390 i n.c. v cc v cc n.c. n.c. n.c. n.c. n.c v cc_bb1 n.c. n.c. n.c. n.c. enable n.c. xtal v cc_xtal
5ghz receiver max2852 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 10/09 initial release 1 3/10 modified ec table to support single-pass room test flow 2, 3, 5, 8

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