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| ht49r30a-1/HT49C30-1/ht49c30l 8-bit lcd type mcu rev. 1.10 1 september 25, 2002 features operating voltage: 2.2v~5.5v for ht49r30a-1/HT49C30-1 1.2v~2.2v for ht49c30l 6 input lines 8 bidirectional i/o lines two external interrupt input one 8-bit programmable timer/event counter with pfd (programmable frequency divider) function lcd driver with 19 2, 19 3or18 4 segments 2k 14 program memory rom 96 8 data memory ram real time clock (rtc) 8-bit prescaler for rtc watchdog timer buzzer output on-chip crystal, rc and 32768hz crystal oscillator halt function and wake-up feature reduce power consumption 4-level subroutine nesting bit manipulation instruction 14-bit table read instruction up to 0.5 s instruction cycle with 8mhz system clock for ht49r30a-1/HT49C30-1 up to 8 s instruction cycle with 500khz system clock for ht49c30l 63 powerful instructions all instructions in 1 or 2 machine cycles low voltage reset/detector for ht49r30a-1/HT49C30-1 48-pin ssop package general description the HT49C30-1 and the ht49c30l are 8-bit high per - formance single chip microcontrollers. the ht49r30a-1 is the otp version of the HT49C30-1. its single cycle instruction and two-stage pipeline architec- ture make it suitable for high speed applications. the devices are also suitable for use in multiple lcd low power applications such as scales, leisure products, high-level household appliances, hand held lcd prod- ucts and batteries operated systems in particular.
block diagram ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 2 september 25, 2002 ! " ! " # # # $ ! % & # ! # # ' # # ( ) * + ! " & , ) * ' * * ) - ' # ) * + # # ) . # / # 0 * ( ) ( * ) ' # 1 $ * $ ' ( / ) 2 ( / 0 ' * - * / * 3 4 # $ ) $ ) $ ! " . & , ) & , ' * ) pin assignment pad assignment HT49C30-1 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 3 september 25, 2002 ! ht49c30l * the ic substrate should be connected to vss in the pcb layout artwork. pad description pad name i/o options description pa0/bz pa1/bz pa2 pa3/pfd pa4~pa7 i/o wake-up pull-high or none cmos or nmos pa0~pa7 constitute an 8-bit bidirectional input/output port with schmitt trig- ger input capability. each bit on port can be configured as a wake-up input by options. pa0~pa3 can be configured as a cmos output or nmos input/out - put with or without pull-high resistor by options. pa4~pa7 are always pull-high nmos input/output. of the eight bits, pa0~pa1 can be set as i/o pins or buzzer outputs by options. pa3 can be set as an i/o pin or as a pfd output also by options. pb0/int0 pb1/int1 pb2/tmr pb3~pb5 i pb0~pb5 constitute a 6-bit schmitt trigger input port. each bit on port are with pull-high resistor. of the six bits, pb0 and pb1 can be set as input pins or as external interrupt control pins (int0 ) and (int1 ) respectively, by software application. pb2 can be set as an input pin or as a timer/event counter input pin tmr also by software application. vss negative power supply, ground vlcd i lcd power supply for ht49r30a-1/HT49C30-1. voltage pump for ht49c30l. v2 i voltage pump for ht49r30a-1/HT49C30-1. lcd power supply for ht49c30l. v1,c1,c2 i voltage pump seg18/com3 com2~com0 o 1/2 or 1/3 or 1/4 duty seg18 can be set as a segment or as a common output driver for lcd panel by options. com2~com0 are outputs for lcd panel plate. seg17~seg0 o lcd driver outputs for lcd panel segments ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 4 september 25, 2002 7 ( 8 ( 9 3 5 0 2 6 ( 3 0 5 3 ( 6 2 0 5 2 0 5 3 ( 6 2 3 5 0 ) 2 ( ( 3 5 0 2 6 ( * + ) # ( * + ) # # . ) # # # 3 # 5 # 0 ( ) * ( ) * ) * * * * 3 $ 3 5 0 2 6 ( pad name i/o options description osc4 osc3 o i rtc or system clock real time clock oscillators. osc3 and osc4 are connected to a 32768hz crystal oscillator for timing purposes or to a system clock source (depending on the options). vdd positive power supply osc2 osc1 o i crystal or rc osc1 and osc2 are connected to an rc network or a crystal (by options) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. the system clock may come from the rtc oscillator. if the system clock co - mes from rtcosc, these two pins can be floating. res i schmitt trigger reset input, active low absolute maximum ratings supply voltage..................................v ss 0.3v to 5.5v* supply voltage ................................v ss 0.3v to 2.2v** storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature ........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. * for ht49r30a-1/HT49C30-1 ** for ht49c30l d.c. characteristics v dd =1.5v for ht49c30l, v dd =3v&v dd =5v for ht49r30a-1 and HT49C30-1 ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage for ht49c30l 1.2 2.2 v lvr disable (for ht49r30a-1/HT49C30-1) 2.2 5.5 v i dd1 operating current (crystal osc) 1.5v no load, f sys =455khz 60 100 a 3v no load, f sys =4mhz 12ma 5v 35ma i dd2 operating current (rc osc) 1.5v no load, f sys =400khz 50 100 a 3v no load, f sys =4mhz 12ma 5v 35ma i dd3 operating current (f sys =32768hz) 1.5v no load 2.5 4 a 3v 0.3 0.6 ma 5v 24ma i stb1 standby current (*f s =t1) 1.5v no load, system halt, lcd off at halt 0.1 0.5 a 3v 1 a 5v 2 a ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 5 september 25, 2002 symbol parameter test conditions min. typ. max. unit v dd conditions i stb2 standby current (*f s =32.768khz osc) 1.5v no load, system halt, lcd on at halt, c type 12 a 3v 2.5 5 a 5v 610 a i stb3 standby current (*f s =wdt rc osc) 1.5v no load, system halt lcd on at halt, c type 0.5 1 a 3v 25 a 5v 610 a i stb4 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, r type, 1/2 bias 17 30 a 5v 34 60 a i stb5 standby current (*f s =32.768khz osc) 3v no load, system halt, lcd on at halt, r type, 1/3 bias 13 25 a 5v 28 50 a i stb6 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1/2 bias 14 25 a 5v 26 50 a i stb7 standby current (*f s =wdt rc osc) 3v no load, system halt, lcd on at halt, r type, 1/3 bias 10 20 a 5v 19 40 a v il1 input low voltage for i/o ports, tmr and int 1.5v 0 0.3v dd v 3v 0 0.3v dd v 5v 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 1.5v 0.7v dd v dd v 3v 0.7v dd v dd v 5v 0.7v dd v dd v v il2 input low voltage (res ) 1.5v 0 0.4v dd v 3v 0 0.4v dd v 5v 0 0.4v dd v v ih2 input high voltage (res ) 3v 0.9v dd v dd v 1.5v 0.9v dd v dd v 5v 0.9v dd v dd v i ol1 i/o port sink current 1.5v v ol =0.1v dd 0.4 0.8 ma 3v 6 12 ma 5v 10 25 ma i oh1 i/o port source current 1.5v v oh =0.9v dd 0.3 ma 3v 2 -4 ma 5v 5 8 ma i ol2 lcd comment and segment current 3v v ol =0.1v dd 210 420 a 5v 350 700 a i oh2 lcd comment and segment current 3v v oh =0.9v dd 80 160 a 5v 180 360 a ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 6 september 25, 2002 symbol parameter test conditions min. typ. max. unit v dd conditions r ph pull-high resistance of i/o ports and int0 , int1 1.5v 75 150 300 k 3v 40 60 80 k 5v 10 30 50 k v lvr low voltage reset voltage 2.7 3.2 3.6 v v lvd low voltage detector voltage 3.0 3.3 3.6 v note: t sys =1/f sys *f s please refer to the clock option of wdt a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 1.5v 400 500 khz 3v 400 4000 khz 5v 400 8000 khz f sys2 system clock (rc osc) 1.5v 400 500 khz 3v 400 4000 khz 5v 400 8000 khz f sys3 system clock (32768hz crystal osc) 32768 hz f rtcosc rtc frequency 32768 hz f timer timer i/p frequency 1.5v 0 500 khz 3v 0 4000 khz 5v 0 8000 khz t wdtosc watchdog oscillator 1.5v 35 70 140 s 3v 45 90 180 s 5v 35 65 130 s t res external reset low pulse width for ht49c30l 10 s for ht49r30a-1/HT49C30-1 1 s t sst system start-up timer period wake-up from halt 1024 t sys t opd option load time during reset 1.5v 35 70 140 ms 3v 45 90 180 ms 5v 35 70 140 ms t int interrupt pulse width for ht49c30l 10 s for ht49r30a-1/HT49C30-1 1 s note: t sys =1/f sys ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 7 september 25, 2002 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 8 september 25, 2002 functional description execution flow the system clock is derived from either a crystal or an rc oscillator or a 32768hz crystal oscillator. it is inter - nally divided into four non-overlapping clocks. one in - struction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. the pipelining scheme causes each instruction to effec - tively execute in a cycle. if an instruction changes the value of the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) is of 11 bits wide and controls the sequence in which the instructions stored in the pro - gram rom are executed. the contents of the pc can specify a maximum of 2048 addresses. after accessing a program memory word to fetch an in - struction code, the value of the pc is incremented by one. the pc then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading a pcl register, a subroutine call, an ini - tial reset, an internal interrupt, an external interrupt, or returning from a subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get a proper instruction; oth - erwise proceed with the next instruction. the lower byte of the pc (pcl) is a readable and writeable register (06h). moving data into the pcl per - forms a short jump. the destination is within 256 loca - tions. . % ' ' 7 9 : ' ' 7 ; 9 . % ' ' 7 < 9 : ' ' 7 9 . % ' ' 7 < 9 : ' ' 7 < 9 < < ' = > ' 7 ' = 9 execution flow mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 external interrupt 0 00000000100 external interrupt 1 00000001000 timer/event counter overflow 00000001100 time base interrupt 00000010000 rtc interrupt 00000010100 skip pc+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 9 september 25, 2002 when a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 2048 14 bits which are addressed by the pc and table pointer. certain locations in the rom are reserved for special usage: location 000h location 000h is reserved for program initialization. after chip reset, the program always begins execution at this location. location 004h location 004h is reserved for the external interrupt service program. if the int0 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. location 008h location 008h is reserved for the external interrupt service program also. if the int1 input pin is activated, and the interrupt is enabled, and the stack is not full, the program begins execution at location 008h. location 00ch location 00ch is reserved for the timer/event counter interrupt service program. if a timer interrupt results from a timer/event counter overflow, and if the inter - rupt is enabled and the stack is not full, the program begins execution at location 00ch. location 010h location 010h is reserved for the time base interrupt service program. if a time base interrupt occurs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 010h. location 014h location 014h is reserved for the real time clock inter - rupt service program. if a real time clock interrupt oc - curs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014h. table location any location in the rom can be used as a look-up ta - ble. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the contents of the higher-order byte to tblh (table higher-order byte register) (08h). only the destination of the lower-order byte in the table is well-defined; the other bits of the ta- ble word are all transferred to the lower portion of tblh, and the remaining 2 bit is read as 0 . the tblh is read only, and the table pointer (tblp) is a read/write register (07h), indicating the table location. before accessing the table, the location should be placed in tblp. all the table related instructions re- quire 2 cycles to complete the operation. these areas may function as a normal rom depending upon the user s requirements. stack register stack the stack register is a special part of the memory used to save the contents of the pc. the stack is organized into 4 levels and is neither part of the data nor part of the program, and is neither readable nor writeable. its acti - vated level is indexed by a stack pointer (sp) and is nei - ther readable nor writeable. at a commencement of a subroutine call or an interrupt acknowledgment, the contents of the pc is pushed onto the stack. at the end of the subroutine or interrupt routine, signaled by a re - turn instruction (ret or reti), the contents of the pc is ( ( ( 4 ( ( 4 ( ( 2 4 ' ? ( ( 4 0 . . 4 @ ' ' ' & ' ( ' ' 0 ( 4 ( ( 4 ( ( 4 . . 4 a ' = b ' : = ' ' ( ' ? ) a ' ' ' ? $ > ; ' ? = ' 7 3 5 ' c 9 : = ' ' ' ? ' * ' ' $ > ; ' ? = ' 7 3 5 ' c 9 program memory instruction(s) table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits p10~p8: current program counter bits @7~@0: table pointer bits ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 10 september 25, 2002 restored to its previous value from the stack. after chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag is recorded but the ac - knowledgment is still inhibited. once the sp is decre - mented (by ret or reti), the interrupt is serviced. this feature prevents stack overflow, allowing the program - mer to use the structure easily. likewise, if the stack is full, and a call is subsequently executed, a stack overflow occurs and the first entry is lost (only the most recent four return addresses are stored). data memory ram the data memory (ram) is designed with 113 8 bits, and is divided into two functional groups, namely special function registers and general purpose data memory, most of which are readable/writeable, although some are read only. of the two types of functional groups, the special func - tion registers consist of an indirect addressing register 0 (00h), a memory pointer register 0 (mp0;01h), an indi - rect addressing register 1 (02h), a memory pointer reg - ister 1 (mp1;03h), a bank pointer (bp;04h), an accumulator (acc;05h), a program counter lower-order byte register (pcl;06h), a t able pointer (tblp;07h), a table higher-order byte register (tblh;08h), a real time clock control register (rtcc;09h), a status register (status;0ah), an inter- rupt control register 0 (intc0;0bh), a timer/event coun- ter (tmr;0dh), a timer/event counter control register (tmrc;0eh), i/o registers (pa;12h, pb;14h), and in- terrupt control register 1 (intc1;1eh). on the other hand, the general purpose data memory, addressed from 20h to 7fh, is used for data and control informa- tion under instruction commands. the areas in the ram can directly handle arithmetic, logic, increment, decrement, and rotate operations. ex - cept some dedicated bits, each bit in the ram can be set and reset by set [m].i and clr [m].i they are also indirectly accessible through the memory pointer register 0 (mp0;01h) or the memory pointer register 1 (mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] accesses the ram pointed to by mp0 (01h) and mp1(03h) respectively. reading lo - cation 00h or 02h indirectly returns the result 00h. while, writing it indirectly leads to no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 (7-bit) and mp1 (7-bit), used to access the ram by combining corresponding indirect address - ing registers. mp0 can only be applied to data memory, while mp1 can be applied to data memory and lcd dis - play memory. accumulator acc the accumulator (acc) is related to the alu opera - tions. it is also mapped to location 05h of the ram and is capable of operating with immediate data. the data movement between two data memory locations must pass through the acc. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions and provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz etc.) = ' # # ' , 7 6 5 ' * 9 = ' # # ' , ( ( 4 ( 4 ( 4 ( 4 ( 4 ( 3 4 ( 5 4 ( 0 4 ( 2 4 ( 6 4 ( # 4 ( * 4 ( 4 ( 4 ( 4 ( . 4 ( 4 4 4 4 4 3 4 5 4 0 4 2 4 6 4 # 4 * 4 4 4 4 . 4 0 . 4 @ ' ! d ' ' e ( e ( 4 ( ' # ' ' ( ' # ' ' * # $ * $ * $ 4 # ! ( # * ram mapping ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 11 september 25, 2002 the alu not only saves the results of a data operation but also changes the status register. status register status the status register (0ah) is of 8 bits wide and contains, a carry flag (c), an auxiliary carry flag (ac), a zero flag (z), an overflow flag (ov), a power down flag (pd), and a watchdog time-out flag (to). it also records the status information and controls the operation sequence. except the to and pd flags, bits in the status register can be altered by instructions similar to other registers. data written into the status register does not alter the to or pd flags. operations related to the status register, however, may yield different results from those in - tended. the to and pd flags can only be changed by a watchdog timer overflow, chip power-up, or clearing the watchdog timer and executing the halt instruc - tion. the z, ov, ac, and c flags reflect the status of the latest operations. on entering the interrupt sequence or executing the subroutine call, the status register will not be automati - cally pushed onto the stack. if the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. interrupts the device provides two external interrupts, an internal timer/event counter interrupt, an internal time base in- terrupt, and an internal real time clock interrupt. the in- terrupt control register 0 (intc0;0bh) and interrupt control register 1 (intc1;1eh) both contain the interrupt control bits that are used to set the enable/disable status and interrupt request flags. once an interrupt subroutine is serviced, other inter - rupts are all blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may take place during this interval, but only the interrupt request flag will be recorded. if a certain interrupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc0 or of intc1 may be set in order to allow interrupt nesting. once the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is en - abled, until the sp is decremented. if immediate service is desired, the stack should be prevented from becom - ing full. all these interrupts can support a wake-up function. as an interrupt is serviced, a control transfer occurs by pushing the contents of the pc onto the stack followed by a branch to a subroutine at the specified location in the rom. only the contents of the pc is pushed onto the stack. if the contents of the register or of the status register (status) is altered by the interrupt service pro - gram which corrupts the desired control sequence, the contents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int0 or int1 , and the related interrupt request flag (eif0; bit 4 of intc0, eif1; bit 5 of intc0) is set as well. after the interrupt is enabled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h or 08h occurs. the interrupt request flag (eif0 or eif1) and emi bits are all cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf; bit 6 of intc0), which is normally caused by a timer overflow. after the interrupt is enabled, and the stack is labels bits function c0 c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z 2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared by either a system power-up or executing the clr wdt instruction. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6 unused bit, read as 0 7 unused bit, read as 0 status register ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 12 september 25, 2002 not full, and the tf bit is set, a subroutine call to location 0ch occurs. the related interrupt request flag (tf) is re - set, and the emi bit is cleared to disable further inter - rupts. the time base interrupt is initialized by setting the time base interrupt request flag (tbf; bit 4 of intc1), that is caused by a regular time base signal. after the interrupt is enabled, and the stack is not full, and the tbf bit is set, a subroutine call to location 10h occurs. the related interrupt request flag (tbf) is reset and the emi bit is cleared to disable further interrupts. the real time clock interrupt is initialized by setting the real time clock interrupt request flag (rtf; bit 5 of intc1), that is caused by a regular real time clock sig - nal. after the interrupt is enabled, and the stack is not full, and the rtf bit is set, a subroutine call to location 14h occurs. the related interrupt request flag (rtf) is reset and the emi bit is cleared to disable further inter - rupts. during the execution of an interrupt subroutine, other in - terrupt acknowledgments are all held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set both to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti sets the emi bit and en - ables an interrupt service, but ret does not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses are serviced on the latter of the two t2 pulses if the corresponding interrupts are enabled. in the case of simultaneous requests, the priorities in the following table apply. these can be masked by resetting the emi bit. no. interrupt source priority vector a external interrupt 0 1 04h b external interrupt 1 2 08h c timer/event counter overflow 3 0ch d time base interrupt 4 10h e real time clock interrupt 5 14h the timer/event counter interrupt request flag (tf), ex- ternal interrupt 1 request flag (eif1), external interrupt 0 request flag (eif0), enable timer/event counter interrupt bit (eti), enable external interrupt 1 bit (eei1), enable external interrupt 0 bit (eei0), and enable master inter - rupt bit (emi) make up of the interrupt control register 0 (intc0) which is located at 0bh in the ram. the real time clock interrupt request flag (rtf), time base inter - rupt request flag (tbf), enable real time clock interrupt bit (erti), and enable time base interrupt bit (etbi), constitute the interrupt control register 1 (intc1) which is located at 1eh in the ram. emi, eei0, eei1, eti, etbi, and erti are all used to control the enable/dis - able status of interrupts. these bits prevent the re - quested interrupt from being serviced. once the interrupt request flags (rtf, tbf, tf, eif1, eif0) are all set, they remain in the intc1 or intc0 respectively until the interrupts are serviced or cleared by a software in - struction. register bit no. label function intc0 (0bh) 0 emi control the master (global) interrupt (1=enabled; 0=disabled) 1 eei0 control the external interrupt 0 (1=enabled; 0=disabled) 2 eei1 control the external interrupt 1 (1=enabled; 0=disabled) 3 eti control the timer/event counter interrupt (1=enabled; 0=disabled) 4 eif0 external interrupt 0 request flag (1=active; 0=inactive) 5 eif1 external interrupt 1 request flag (1=active; 0=inactive) 6 tf internal timer/event counter request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc1 (1eh) 0 etbi control the time base interrupt (1=enabled; 0:disabled) 1 erti control the real time clock interrupt (1=enabled; 0:disabled) 2, 3 unused bit, read as 0 4 tbf time base request flag (1=active; 0=inactive) 5 rtf real time clock request flag (1=active; 0=inactive) 6, 7 unused bit, read as 0 intc register ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 13 september 25, 2002 it is recommended that a program not use the call subroutine within the interrupt subroutine. it s because interrupts often occur in an unpredictable manner or re - quire to be serviced immediately in some applications. at this time, if only one stack is left, and enabling the in - terrupt is not well controlled, operation of the call in the interrupt subroutine may damage the original control se - quence. oscillator configuration the device provides three oscillator circuits for system clocks, i.e., rc oscillator, crystal oscillator and 32768hz crystal oscillator, determined by options. no matter what type of oscillator is selected, the signal is used for the system clock. the halt mode stops the system oscilla - tor (rc and crystal oscillator only) and ignores external signal to conserve power. the 32768hz crystal oscilla - tor (system oscillator) still runs at halt mode. if the 32768hz crystal oscillator is selected as the system os - cillator, the system oscillator is not stopped; but the in - struction execution is stopped. since the (used as system oscillator or oscillator) is also designed for tim - ing purposes, the internal timing (rtc, time base, wdt) operation still runs even if the system enters the halt mode. of the three oscillators, if the rc oscillator is used, an external resistor between osc1 and vss is required, and the range of the resistance should be from 24k to 1m for ht49r30a-1/HT49C30-1 and from 560k to 1m for ht49c30l. the system clock, divided by 4, is available on osc2 with pull-high resistor, which can be used to synchronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temper- ature, and the chip itself due to process variations. it is therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. on the other hand, if the crystal oscillator is selected, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. a resonator may be connected between osc1 and osc2 to replace the crystal and to get a frequency reference, but two ex - ternal capacitors in osc1 and osc2 are required. there is another oscillator circuit designed for the real time clock. in this case, only the 32.768khz crystal oscil - lator can be applied. the crystal should be connected between osc3 and osc4. the rtc oscillator circuit can be controlled to oscillate quickly by setting the qosc bit (bit 4 of rtcc). it is recommended to turn on the quick oscillating function upon power on, and then turn it off after 2 seconds. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. although the system enters the power down mode, the system clock stops, and the wdt oscillator still works with a pe - riod of approximately 78 s. the wdt oscillator can be disabled by options to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or an instruction clock (system clock/4) or a real time clock oscillator (rtc os - cillator). the timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the wdt can be disabled by options. but if the wdt is disabled, all exe - cutions related to the wdt lead to no operation. the wdt time-out period is f s /2 15 ~f s /2 16 . if the wdt clock source chooses the internal wdt oscil- lator, the time-out period may vary with temperature, vdd, and process variations. on the other hand, if the clock source selects the instruction clock and the halt instruction is executed, wdt may stop counting and lose its protecting purpose, and the logic can only be restarted by an external logic. when the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt can stop the system clock. the wdt overflow under normal operation initializes a chip reset and sets the status bit to . in the halt mode, the overflow initializes a warm reset , and only the pc and sp are reset to zero. to clear the contents of the wdt, there are three methods to be adopted, i.e., system oscillator ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 14 september 25, 2002 external reset (a low level to res ), software instruction, and a halt instruction. there are two types of soft - ware instructions; clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruc - tion, only one type of instruction can be active at a time depending on the options clr wdt times selection option . if the clr wdt is selected (i.e., clr wdt times equal one), any execution of the clr wdt in - struction clears the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e., clr wdt times equal two), these two instructions have to be executed to clear the wdt; otherwise, the wdt may reset the chip due to time-out. multi-function timer the device provides a multi-function timer for the wdt, time base and rtc but with different time-out periods. the multi-function timer consists of a 8-stage divider and an 7-bit prescaler, with the clock source coming from the wdt osc or rtc osc or the instruction clock (i.e.., s ystem clock divided by 4). the multi-function timer also provides a selectable frequency signal (ranges from f s /2 2 to f s /2 8 ) for lcd driver circuits, and a selectable frequency signal (ranges from f s /2 2 to f s /2 9 ) for the buzzer output by options. it is recommended to select a near 4khz signal to lcd driver circuits for proper display. time base the time base offers a periodic time-out period to gener - ate a regular internal interrupt. its time-out period ranges from /2 12 to f s /2 15 selected by options. if time base time-out occurs, the related interrupt request flag (tbf; bit 4 of intc1) is set. but if the interrupt is en - abled, and the stack is not full, a subroutine call to loca - tion 10h occurs. real time clock rtc the real time clock (rtc) is operated in the same man - ner as the time base that is used to supply a regular in - ternal interrupt. its time-out period ranges from f s /2 8 to f s /2 15 by software programming . writing data to rt2, rt1 and rt0 (bit2, 1, 0 of rtcc;09h) yields various time-out periods. if the rtc time-out occurs, the related interrupt request flag (rtf; bit 5 of intc1) is set. but if the interrupt is enabled, and the stack is not full, a sub - routine call to location 14h occurs. the real time clock time-out signal also can be applied to be a clock source of timer/event counter for getting a longer time-out pe - riod. ' ' ' ' ' ' ' ' & ' * ' & ) / & ) 3 * b b ' 7 & ) / & ) 6 9 $ ' a ' 7 & ) / & ) 2 9 a = time base a ' ' ' ' ' ' ' ' & 2 ' ' : d = ( ' & ) 2 / & ) 3 real time clock ' = > ) a - ' = = - > 4 b 0 5 2 4 b 1 1 & ; ' ' & ) 3 / & ) 5 a watchdog timer ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 15 september 25, 2002 rt2 rt1 rt0 rtc clock divided factor 000 2 8 * 001 2 9 * 010 2 10 * 011 2 11 * 100 2 12 101 2 13 110 2 14 111 2 15 note: * not recommended for use power down operation halt the halt mode is initialized by the halt instruction and results in the following. the system oscillator turns off but the wdt or rtc oscillator keeps running (if the wdt oscillator or the real time clock is selected). the contents of the on-chip ram and of the registers remain unchanged. the wdt is cleared and start recounting (if the wdt clock source is from the wdt oscillator or the real time clock oscillator). all i/o ports maintain their original status. the pd flag is set but the to flag is cleared. lcd driver is still running (if the wdt osc or rtc osc is selected). the system quits the halt mode by an external reset, an interrupt, an external falling edge signal on port a, or a wdt overflow. an external reset causes device initial- ization, and the wdt overflow performs a warm reset . after examining the to and pd flags, the reason for chip reset can be determined. the pd flag is cleared by sys- tem power-up or by executing the clr wdt instruction, and is set by executing the halt instruction. on the other hand, the to flag is set if wdt time-out occurs, and causes a wake-up that only resets the pc (program counter) and sp, and leaves the oth - ers at their original state. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by options. awakening from an i/o port stimulus, the program resumes execution of the next instruction. on the other hand, awakening from an interrupt, two se - quences may occur. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. but if the in - terrupt is enabled, and the stack is not full, the regular in - terrupt response takes place. when an interrupt request flag is set before entering the halt status, the system cannot be awaken using that interrupt. if wake-up events occur, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period is inserted after the wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. however, if the wake-up results in the next instruction execution, the execution will be per - formed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which reset may occur. res is reset during normal operation res is reset during halt wdt time-out is reset during normal operation the wdt time-out during halt differs from other chip reset conditions, for it can perform a warm reset that resets only the pc and sp and leaves the other circuits at their original state. some registers remain unaffected during any other reset conditions. most registers are re - set to the initial condition once the reset conditions are met. examining the pd and to flags, the program can distinguish between different chip resets . to pd reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem awakes from the halt state. awaking from the halt state, the sst delay is added. an extra option load time delay is added during reset and power on. reset circuit ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 16 september 25, 2002 the functional unit chip reset status is shown below. pc 000h interrupt disabled prescaler, divider cleared wdt, rtc, time base cleared. after master reset, wdt starts counting timer/event counter off input/output ports input mode sp points to the top of the stack ' ; % ' ' < reset timing chart - 4 # $ - ; : = = c ; ' ( ; ? ' = - ' reset configuration the states of the registers are summarized below: register reset (power on) wdt time-out (norma operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* tmr xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmrc 0000 1--- 0000 1--- 0000 1--- 0000 1--- uuuu u--- program counter 0000h 0000h 0000h 0000h 0000h mp0 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu mp1 -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu bp ---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc0 -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 --00 --00 --00 --00 --00 --00 --00 --00 --uu --uu rtcc --00 0111 --00 0111 --00 0111 --00 0111 --uu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu note: * stands for warm reset u stands for unchanged x stands for unknown ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 17 september 25, 2002 timer/event counter one timer/event counters is implemented in the device. it contains an 8-bit programmable count-up counter. the timer/event counter clock source may come from the system clock or system clock/4 or rtc time-out sig - nal or external source. system clock source or system clock/4 is selected by options. using external clock input allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. while using the internal clock allows the user to generate an accurate time base. there are two registers related to the timer/event coun - ter, i.e., tmr ([0dh]) and tmrc ([0eh]). there are also two physical registers which are mapped to tmr loca - tion; writing tmr places the starting value in the timer/event counter preload register, while reading it yields the contents of the timer/event counter. tmrc is a timer/event counter control register used to define some options. the tn0 and tn1 bits define the operation mode. the event count mode is used to count external events, which means that the clock source is from an external tmr pin. the timer mode functions as a normal timer with the clock source coming from the internal selected clock source. finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal tmr, and the counting is based on the internal selected clock source. in the event count or timer mode, the timer/event coun- ter starts counting at the current contents in the timer/event counter and ends at ffh. once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt re- quest flag (tf; bit 6 of intc0). in the pulse width measurement mode with the va lues of the ton and te bits equal to one, after the tmr has received a transient from low to high (or high to low if the te bit is 0 ), it will start counting until the tmr returns to the original level and resets the ton. the measured result remains in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be made until the ton is set. the cycle measurement will re-function as long as it receives further transient pulse. in this oper - ation mode, the timer/event counter begins counting ac - cording not to the logic level but to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton is automatically cleared after the measurement cycle is completed. but in the other two modes, the ton can only be reset by in - structions. the overflow of the timer/event counter is one of the wake-up sources and can also be applied to a pfd (programmable frequency divider) output at pa3 by options. no matter what the operation mode is, writing a 0 to eti disables the related interrupt service. when the pfd function is selected, executing clr [pa].3 instruc - tion to enable pfd output and executing set [pa].3 in - struction to disable pfd output. in the case of timer/event counter off condition, writing data to the timer/event counter preload register also re- loads that data to the timer/event counter. but if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event coun- ter preload register. the timer/event counter still contin- ues its operation until an overflow occurs. when the timer/event counter (reading tmr) is read, the clock is blocked to avoid errors. as this may results in a counting error, blocking of the clock should be taken into account by the programmer. ' = > ( ( = ' - % ' = ) a ' = ' ) a ' * = a & = c ' ! " ' = > ) f . # ' ' $ ' & timer/event counter ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 18 september 25, 2002 label (tmr0c) bits function 0~2 unused bit, read as 0 te 3 to define the tmr0 active edge of timer/event counter (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer counting (0=disabled; 1=enabled) tn2 5 2 to 1 multiplexer control inputs to select the timer/event counter clock source (0=rtc outputs; 1= system clock or system clock/4) tn0 tn1 6 7 to define the operating mode (tn1, tn0) 01= event count mode (external clock) 10= timer mode (internal clock) 11= pulse width measurement mode (external clock) 00= unused tmrc register it is strongly recommended to load a desired value into the tmr register first, then turn on the related timer/event counter for proper operation, because the initial value of tmr is unknown. due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredict - able result. after this procedure, the timer/event function can be operated normally. input/output ports there are a 8-bit bidirectional input/output port, an 6-bit input port in the device, labeled pa, pb which are mapped to [12h], [14h] of the ram, respectively. pa0~pa3 can be configured as cmos (output) or nmos (input/output) with or without pull-high resistor by options. pa4~pa7 are always pull-high and nmos (in - put/output). if you choose nmos (input), each bit on the port (pa0~pa7) can be configured as a wake-up input. pb can only be used for input operation. all the ports for the input operation (pa, pb), are non-latched, that is, the in - puts should be ready at the t2 rising edge of the instruc - tion mov a, [m] (m=12h or 14h). for pa output operation, all data are latched and remain unchanged until the output latch is rewritten. when the pa structures are open drain nmos type, it should be noted that, before reading data from the pads, a 1 should be written to the related bits to disable the nmos device. that is executing first the instruction set [m].i (i=0~7 for pa) to disable related nmos de - vice, and then mov a, [m] to get stable data. after chip reset, these input lines remain at the high level or are left floating (by options). each bit of these output latches can be set or cleared by the mov [m], a (m=12h) instruction. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. when a pa line is used as an i/o line, the related pa line options should be config - ured as nmos with or without pull-high resistor. once a pa line is selected as a cmos output, the i/o function cannot be used. the input state of a pa line is read from the related pa pad. when the pa is configured as nmos with or with- out pull-high resistor, one should be careful when apply- ing a read-modify-write instruction to pa. since the read-modify-write will read the entire port state (pads state) firstly, execute the specified instruction and then write the result to the port data register. when the read operation is executed, a fault pad state (caused by the load effect or floating state) may be read. errors will then occur. there are three function pins that share with the pa port: pa0/bz, pa1/bz and pa3/pfd. the bz and bz are buzzer driving output pair and the pfd is a programmable frequency divider output. if the user wants to use the bz/bz or pfd function, the related pa port should be set as a cmos output. the buzzer output signals are controlled by pa0 and pa1 data regis - ters and defined in the following table. pa1 data register pa0 data register pa0/pa1 pad state 0 0 pa0=bz, pa1=bz 1 0 pa0=bz, pa1=0 x 1 pa0=0, pa1=0 note: x stands for unused ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 19 september 25, 2002 the pfd output signal function is controlled by the pa3 data register and the timer/event counter state. the pfd output signal frequency is also dependent on the timer/event counter overflow period. the definitions of pfd control signal and pfd output frequency are listed in the following table. timer timer preload value pa3 data register pa3 pad state pfd frequency off x 0 u x off x 1 0 x on n 0 pfd f int /[2 (256 n)] on n 1 0 x note: x stands for unused u stands for unknown f 1 f ' * - ' % ' ' ) - > ; 7 # ' = 9 - > = = ; # ( / # 0 7 # ( / # 9 ' 7 # ( / # 9 ' ' ? ' ) - > = = ; * ( / * 3 ) pa input/output ports pb input ports lcd display memory the device provides an area of embedded data memory for lcd display. this area is located from 40h to 52h of the ram at bank 1. bank pointer (bp; located at 04h of the ram) is the switch between the ram and the lcd display memory. when the bp is set as 01h , any data written into 40h~52h will effect the lcd display. when the bp is cleared to 00h , any data written into 40h~52h means to access the general purpose data memory. the lcd display memory can be read and written to only by indirect addressing mode using mp1. when data is written into the display data area, it is auto- matically read by the lcd driver which then generates the corresponding lcd driving signals. to turn the dis - play on or off, a 1 or a 0 is written to the correspond - ing bit of the display memory, respectively. the figure illustrates the mapping between the display memory and lcd pattern for the device. ( 4 ( 4 4 4 3 ( * ( ( 5 0 2 3 3 display memory ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 20 september 25, 2002 lcd driver output the output number of the device lcd driver can be 19 2 or 19 3or18 4 by options (i.e., 1/2 duty, 1/3 duty or 1/4 duty). the bias type of lcd driver can be r type (for ht49r30a-1/HT49C30-1) or c type. if the r bias type is selected, no external capacitor is required. if the c bias type is selected, a capacitor mounted between c1 and c2 pins is needed. the bias voltage of lcd driver can be 1/2 bias or 1/3 bias by options. ! ! ! " # # $ % ! & ' ' % $ ( ) * + , - . % ( ) * + - . ' ' ! $ ( ) * + - lcd driver output (1/3 duty, 1/2 bias, r/c type) ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 21 september 25, 2002 - " % * ! % - / ! " # # - % # # # # % % * ! % - / , ! " # # # # % - # # % - % - / ! $ ( ) * + , - . % ( ) * + - . lcd driver output low voltage reset/detector functions for ht49r30a-1/HT49C30-1 there is a low voltage detector (lvd) and a low voltage reset circuit (lvr) implemented in the microcontroller. these two functions can be enabled/disabled by op - tions. once the options of lvd is enabled, the user can use the rtcc.3 to enable/disable (1/0) the lvd circuit and read the lvd detector status (0/1) from rtcc.5; otherwise, the lvd function is disabled. the lvr has the same effect or function with the exter - nal res signal which performs chip reset. during halt state, lvr is disabled. the definitions of rtcc register are listed in the follow - ing table. register bit no. label read/write reset function rtcc (09h) 0~2 rt0~rt2 r/w 111b 8 to 1 multiplexer control inputs to select the real clock prescaler output 3 lvdc* r/w 0 lvd enable/disable (1/0) 4 qosc r/w 0 32768hz osc quick start-up oscillating 0/1: quickly/slowly start 5 lvdo* r 0 lvd detection output (1/0) 1: low voltage detected 6~7 unused bit, read as 0 note: * for ht49r30a-1/HT49C30-1 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 22 september 25, 2002 options the following shows the options in the device. all these options should be defined in order to ensure proper functioning system. options osc type selection. this option is to determine whether an rc or crystal or 32768hz crystal oscillator is chosen as system clock. wdt clock source selection. rtc and time base. there are three types of selection: system clock/4 or rtc osc or wdt osc. wdt enable/disable selection. wdt can be enabled or disabled by options. clr wdt times selection. this option defines how to clear the wdt by instruction. one time means that the clr wdt can clear the wdt. two times means that if both of the clr wdt1 and clr wdt2 have been executed, only then will the wdt be cleared. time base time-out period selection. the time base time-out period ranges from clock/2 12 to clock/2 15 clock means the clock source selected by op - tions. buzzer output frequency selection. there are eight types of frequency signals for buzzer output: clock/2 2 ~clock/2 9 . clock means the clock source se - lected by options. wake-up selection. this option defines the wake-up capability. external i/o pins (pa only) all have the capability to wake-up the chip from a halt by a falling edge. pull-high selection. this option is to decide whether the pull-high resistance is visible or not on the pa0~pa3. (pb and pa4~pa7 are al- ways pull-high) pa0~pa3 cmos or nmos selection. the structure of pa0~pa3 4 bits can be selected as cmos or nmos individually. when the cmos is selected, the related pins only can be used for output operations. when the nmos is selected, the related pins can be used for in- put or output operations. (pa4~pa7 are always nmos) clock source selection of timer/event counter. there are two types of selection: system clock or system clock/4. i/o pins share with other functions selection. pa0/bz , pa1/bz: pa0 and pa1 can be set as i/o pins or buzzer outputs. pa3/pfd: pa3 can be set as i/o pins or pfd output. lcd common selection. there are three types of selection: 2 common (1/2 duty) or 3 common (1/3 duty) or 4 common (1/4 duty). if the 4 com - mon is selected, the segment output pin seg18 will be set as a common output. lcd bias power supply selection. there are two types of selection: 1/2 bias or 1/3 bias for ht49r30a-1/HT49C30-1. lcd bias type selection. this option is to determine what kind of bias is selected, r type or c type for ht49r30a-1/HT49C30-1, c type for ht49c30l. lcd driver clock selection. there are seven types of frequency signals for the lcd driver circuits: f s /2 2 ~f s /2 8 . f s means the clock source selection by options. lcd on/off at halt selection lvr selection. lvr has enable or disable options for ht49r30a-1/HT49C30-1 lvd selection. lvd has enable or disable options for ht49r30a-1/HT49C30-1 application circuits rc oscillator application crystal oscillator application 32768hz crystal oscillator application note: c1=c2=300pf if f sys < 1mhz, otherwise, c1=c2=0 the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 23 september 25, 2002 # ( / # 0 * ( / * 3 & , ) ( ( / 0 ( / $ # $ $ ' c = $ ( d . ( d . ( d . ( ( > ( > ( d . > / 0 ( . # ( / # 0 * ( / * 3 ( / 0 ( / $ $ # $ $ ' c = ( d . ( d . ( d . ( ( ( > ( > ( d . # ( / # 0 * ( / * 3 ( / 0 ( / $ $ # $ $ ' c = ( d . ( d . ( d . ( ( ( > ( > ( d . rc oscillator application crystal oscillator application 32768hz crystal oscillator application note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 24 september 25, 2002 # ( / # 0 * ( / * 3 & , ) ( ( / 0 ( / $ # $ ( d . ( d . $ ( d . ( ( > ( d . 3 5 ( > / 0 ( . # ( / # 0 * ( / * 3 ( / 0 ( / $ # $ ( d . ( d . ( ( . ( ( ( . ( ( > ( d . $ ( d . # ( / # 0 * ( / * 3 ( / 0 ( / $ # $ ( d . ( d . ( ( ( > ( > ( d . $ ( d . instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 25 september 25, 2002 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to (4) ,pd (4) to (4) ,pd (4) none none to,pd note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pd are cleared. otherwise the to and pd flags remain unchanged. ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 26 september 25, 2002 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 27 september 25, 2002 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 28 september 25, 2002 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pd) and time-out bit (to) are cleared. operation wdt 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pd and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the to and pd flags remain unchanged. operation wdt 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 29 september 25, 2002 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 30 september 25, 2002 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 31 september 25, 2002 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 32 september 25, 2002 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 33 september 25, 2002 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 34 september 25, 2002 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 35 september 25, 2002 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 36 september 25, 2002 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 37 september 25, 2002 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 38 september 25, 2002 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 39 september 25, 2002 package information 48-pin ssop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 395 420 b 291 299 c8 12 c 613 637 d85 99 e 25 f4 10 g25 35 h4 12 0 8 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 40 september 25, 2002 2 3 # * . i 4 product tape and reel specifications reel dimensions ssop 48w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 100 0.1 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 32.2+0.3 0.2 t2 reel thickness 38.2 0.2 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 41 september 25, 2002 carrier tape dimensions ssop 48w symbol description dimensions in mm w carrier tape width 32.0 0.3 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 14.2 0.1 d perforation diameter 2.0 min. d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 12.0 0.1 b0 cavity width 16.20 0.1 k1 cavity depth 2.4 0.1 k2 cavity depth 3.2 0.1 t carrier tape thickness 0.35 0.05 c cover tape width 25.5 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 42 september 25, 2002 ( . 1 * ( # ( - 1 ht49r30a-1/HT49C30-1/ht49c30l rev. 1.10 43 september 25, 2002 copyright 2002 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science-based industrial park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (sales office) 11f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (shanghai) inc. 7th floor, building 2, no.889, yi shan rd., shanghai, china tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 holmate semiconductor, inc. 48531 warm springs boulevard, suite 413, fremont, ca 94539 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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