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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a laser diode driver with light power control ad9661a ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features < 2 ns rise/fall times output current: 120 ma single +5 v power supply switching rate: 200 mhz typ onboard light power control loop applications laser printers and copiers and fall times are 2 ns to complement printer applications that use image enhancing techniques such as pulse width modula- tion to achieve gray scale and resolution enhancement. control signals are ttl/cmos compatible. the driver output provides up to 120 ma of current into an infrared n type laser, and the onboard disable circuit turns off the output driver and returns the light power control loop to a safe state. the ad9661a can also be used in closed-loop applications in which the output power level follows an analog power level voltage input. by optimizing the external hold capacitor and the photo detector, the loop can achieve bandwidths as high as 25 mhz. the ad9661a is offered in a 28-pin plastic soic for operation over the commercial temperature range (0 c to +70 c). general description the ad9661a is a highly integrated driver for laser diode appli- cations such as printers and copiers. the ad9661a gets feed- back from an external photo detector and includes an analog feedback loop to allow users to set the power level of the laser, and switch the laser on and off at up to 100 mhz. output rise functional block diagram pulse2 disable circuit delay ttl ttl ttl ttl disable pulse dac c gain analog power level level shift out level shift in 50 w ref 5pf * *13ns delay on rising edge; 0ns on falling 1:10 3C120ma i out volt ref 1:1 hold v ref laser diode +5v photo detector v ref i monitor analog power monitor r gain gain 0C1.6v cal v level shift in + v ref sense in 1.0v 8 i monitor v1 output level shift circuit ad9661a
ad9661aCspecifications test ad9661akr parameter level temp min typ max units conditions analog input input voltage range, power level iv full v ref v ref + 1.6 v input bias current, power level i +25 c C50 +50 m a analog bandwidth, control loop 1 v +25 c 25 mhz c hold = 33 pf, r f = 1 k w , c f = 2 pf input voltage range, level shift in iv full 0.1 1.6 v input bias current, level shift in i +25 c C10 0 m a analog bandwidth, level shift 2 v full 130 mhz level shift offset i +25 c C32 +32 mv level shift gain i +25 c 0.95 1.0 1.05 v/v outputs output current, i out i +25 c 120 ma v out = 2.5 v output compliance range iv +25 c 2.50 5.25 v idle current i +25 c 2 5.0 ma pulse = low, disable = low disable current iv +25 c 1.0 m a pulse = low, disable = high switching performance maximum pulse rate v +25 c 200 mhz output current C3 db output propagation delay (t pd ), rising 3 iv full 2.9 3.9 5.0 ns output propagation delay (t pd ), falling 3 iv full 3.2 3.7 4.3 ns output current rise time 4 iv full 1.5 2.0 ns output current fall time 5 iv full 1.5 2.0 ns cal aperture delay 6 iv full 13 ns disable time 7 iv +25 c35ns hold node input bias current i +25 c C200 200 na v hold = 2.5 v input voltage range iv full v ref v ref + 1.6 v open-loop application only minimum external hold cap v full 25 pf ttl/cmos inputs 8 logic 1 voltage i +25 c 2.0 v logic 1 voltage iv full 2.0 v logic 0 voltage i +25 c 0.8 v logic 0 voltage iv full 0.8 v logic 1 current i +25 c C10 10 m av high = 5.0 v logic 0 current i +25 c C1.5 ma v low = 0.8 v bandgap reference output voltage (v ref ) i +25 c 1.6 1.8 1.9 v temperature coefficient v +25 c C0.1 mv/ c output current v +25 c C0.5 1.0 ma sense in current gain i +25 c 0.95 1 1.02 ma/ma voltage i +25 c 0.7 1.0 1.3 v input resistance v +25 c <150 w power supply +v s voltage i +25 c 4.75 5.00 5.25 v +v s current i +25 c 60 75 95 ma disable = high, v hold = v ref , v s = 5.0 v notes 1 based on rise time of closed-loop pulse response. see performance curves. 2 based on rise time of pulse response. 3 propagation delay measured from the 50% of the rising/falling transition of write pulse to the 50% point of the rising/falling edge of the output modulation current. 4 rise time measured between the 10% and 90% points of the rising transition of the modulation current. 5 fall time measured between the 10% and 90% points of the falling transition of the modulation current. 6 aperture delay is measured from the 50% point of the rising edge of write pulse to the time when the output modulation begins t o recalibrate, write cal is held during this test. 7 disable time is measured from the 50% point of the rising edge of disable to the 50% point of the falling transition of the out put current. fall time during disable is similar to fall time during normal operation. 8 pulse, pulse2 , disable, and cal are ttl/cmos compatible inputs. specifications subject to change without notice. rev. 0 C2C (+v s = +5 v, temperature = +25 8 c unless otherwise noted)
ad9661a rev. 0 C3C absolute maximum ratings* +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v power level, level shift in . . . . . . . . . . . 0 v to +v s ttl/cmos inputs . . . . . . . . . . . . . . . . . . . . C0.5 v to +v s output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma operating temperature ad9661akr . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . . +150 c lead soldering temp (10 sec) . . . . . . . . . . . . . . . . . . . +300 c *absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. ordering guide model temperature range package option ad9661akr 0 c to +70 c r-28 AD9661AKR-REEL 0 c to +70 c r-28 (1000/reel) 100 w 450 w 1250 w v bandgap v ref +v s 1ma +v s 50 w 50 w sense in 1ma t/h hold output ttl input +v s equivalent circuits warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9661a features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c; 100% production tested at temperature extremes for military devices; sample tested at temperature extremes for commercial/industrial devices.
ad9661a rev. 0 C4C pin descriptions pin function output analog laser diode current output. connect to cathode of laser diode, anode connected to +v s externally. power level analog voltage input, v ref to v ref + 1.6 v. output current is set proportional to the power level during calibration as follows: i monitor = v power level v ref r gain + 50 w cal ttl/cmos compatible, feedback loop t/h control signal. logic low enables calibration mode, and the feedback loop t/h goes into track mode 13 ns after (the aperture delay) pulse goes logic high (there is no aperture delay if pulse goes high before cal transitions to a low level). logic high dis- ables the t/h and immediately places it in hold mode. pulse should be held high while calibrating. floats logic high. hold external hold capacitor for the bias loop t/h. approximate droop in the output current while cal is logic high is: d i out = 18 10 9 t hold c hold bandwidth of the loop is: bw ? 1 2 p (550 w ) c hold pulse ttl/cmos compatible, current control signal. logic high supplies i out to the laser diode. logic low turns i out off. floats logic high. pulse 2 ttl/cmos compatible, current control signal. logic low supplies i out to the laser diode. logic high turns i out off. floats logic high. sense in analog current input, i monitor , from pin photo detector diode. sense in should be connected to the anode of the pin diode, with the pin cathode connected to +v s or another positive voltage. voltage at sense in varies slightly with temperature and current, but is typically 1.0 v. gain external connection for the feedback network of the transimpedance amplifier. external feedback network, r gain and c gain , should be connected between gain and power monitor. see text for choosing values. power monitor output voltage monitor of the internal feedback loop. voltage is proportional to feedback current from photo diode, i monitor . disable ttl/cmos compatible, current output disable circuit. logic low for normal operation; logic high disables the current outputs to the laser diode, and drives the voltage on the hold capacitors close to v ref (minimizes the output current when the device is re-enabled). disable floats logic high. v ref analog voltage output, internal bandgap voltage reference, ~1.8 v, provided to user for power level offset. +v s power supply, nominally +5 v. all +v s connections should be tied together externally. ground ground reference. all ground connections should be tied together externally. level shift in analog input to the on board level shift circuit. input range 0.1 v C 1.6 v. level shift out voltage output from on board level shift circuit. connect to power level externally to use the on board level shift circuit. output voltage is v level shift out = v level shift in +v ref . pin assignments ad9661akr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (not to scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pulse2 dnc v ref level shift in gain sense input ground +v s ground hold power level disable +v s ground output ground output ground output ground output ground +v s ground cal pulse1 power monitor level shift out
ad9661a rev. 0 C5C theory of operation the ad9661a combines a very fast output current switch with an onboard analog light power control loop to provide the user with a complete laser diode driver solution. the block diagram illustrates the key internal functions. the control loop of the ad9661a adjusts the output current level, i out , so that the photo diode feedback current, i monitor , into sense in is pro- portional to the analog input voltage at power level. since the monitor current is proportional to the laser diode light power, the loop effectively controls laser power to a level pro- portional to the analog input. the control loop should be peri- odically calibrated (see choosing c hold ). the disable circuit turns off i out and returns the hold capacitor voltages to their minimum levels (minimum output current) when disable = logic high. it is used during initial power up of the ad9661a or during time periods where the laser is inactive. when the ad9661a is re-enabled the control loop must be recalibrated. normal operation of the ad9661a involves the following (in order, see figure 1): 1. the ad9661a is enabled (disable = logic low). 2. the input voltage (power level) is driven to the appropriate level to set the calibrated laser diode output power level. 3. the feedback loop is closed for calibration ( cal = logic low, and pulse = logic high), and then opened ( cal = logic high). 4. while the feedback loop is open, the laser is pulsed on and off by pulse. 5. the feedback loop is periodically recalibrated as needed. 6. the ad9661a is disabled when the laser will not be pulsed for an indefinite period of time. control loop transfer function the relationship between i monitor and v power level is i monitor = v power level v ref ( r gain + 50 w ) once the loop is calibrated. when the loop is open ( cal = logic high), the output current, i out , is proportional to the held voltage at hold; the external hold capacitor on this pin determines the droop error in the output current between calibrations. the sections below discuss choosing the external components in the feedback loop for a particular application. choosing r gain the gain resistor, r gain , allows the user to match the feedback loops t ransfer function to the laser diode/photo diode combination. the user should define the maximum laser diode output power for the intended application, p ld max , and the corresponding photo diode monitor current, i monitor max . a typical laser diode transfer function is illustrated below. r gain should be chosen as: r gain = 1. 6 v i monitor max 50 w 4 3 0 2 1 0 120 20 40 60 80 100 optical output ?mw constant write power 0 c case 25 c case 50 c case i out forward current ?ma figure 2. laser diode current-to-optical power curve power-up or laser not in use cal time recalibrate laser power modulated disable cal pulse laser output power calibrated level hold time figure 1. normal operating mode
ad9661a rev. 0 C6C to choose a value, the user will need to determine the amount of time the loop will be in hold mode, t hold , the maximum change in laser output power the application can tolerate, and the laser efficiency (defined as the change in laser output power to the change in laser diode current). as an example, if an ap- plication requires 5 mw of laser power 5%, and the laser diode efficiency is 0.25 mw/ma, then d i max = 5 mw (5%)/ 0.25 mw ma ? ? ? ? = 1. 0 ma if the same application had a hold time requirement of 250 m s, then the minimum value of the hold capacitor would be: c hold = 18 10 9 250 m s 1. 0 ma = 4.5 nf when determining the calibration time, the t/h and the exter- nal hold capacitor can be modeled using the simple rc circuit illustrated below. c hold r ad9661a t/h tza power level power monitor hold external hold capacitor figure 3. c ircuitry model for determining calibration times using this model, the voltage at the hold capacitor is v c hold = v t = 0 + ( v t = v t = 0 )1 e t t ? ? ? ? where t = 0 is when the calibration begins ( cal goes logic low), v t = 0 is the voltage on the hold cap at t = 0, v t = is the steady state voltage at the hold cap with the loop closed, and t = r c hold is the time constant. with this model the error in v c hold for a finite calibration time, as compared to v t = , can be estimated from the following table and chart: table ii. t calibration % final value error % 7 t 99.9 0.09 6 t 99.7 0.25 5 t 99.2 0.79 4 t 98.1 1.83 3 t 95.0 4.97 2 t 86.5 13.5 t 63.2 36.8 the laser diodes output power will then vary from 0 to p ld max for an input range of v ref to v ref +1.6 v @ the power level input. minimum specifications for i monitor max should be used when choosing r gain . users are cautioned that laser diode/photo diode combinations that produce monitor currents that are less than i monitor max in the equation above will produce higher la- ser output power than predicted, which may damage the laser diode. such a condition is possible if r gain is calculated using typical instead of minimum monitor current specifications. in that case the input range to the ad9661a power level input should be limited to avoid damaging laser diodes. another approach would be to use a potentiometer for r gain . this allows users to optimize the value of r gain for each laser diode/photo diode combinations monitor current. the draw- back to this approach is that potentiometers stray inductance and capacitance may cause the transimpedance amplifier to overshoot and degrade its settling, and the value of c gain may not be optimized for the entire potentiometers range. c gain optimizes the response of the transimpedance amplifier and should be chosen as from the table below. choosing c gain larger than the recommended value will slow the response of the amplifier. lower values improve tza bandwidth but may cause the amplifier to oscillate. table i. recommended r gain c gain 2.5 k w 2 pf 1.5 k w 3 pf 1 k w 4 pf 500 w 8 pf choosing c hold choosing values for the hold capacitor, c hold , is a tradeoff between output current droop when the control loop is open, and the time it takes to calibrate and recalibrate the laser power when the loop is closed. the amount of output current droop is determined by the value of the hold capacitor and the leakage current at that node. when the control loop is open ( cal logic high), the pin con- nection for the hold capacitor (hold) is a high impedance in- put. leakage current will range from 200; this low current minimizes the droop in the output power level. assuming the worst case current of 200 na, the output current will change as follows: d i out = 18 10 9 c hold
ad9661a rev. 0 C7C time constants ? t 100 30 0 05 1 % final value ?% of volts 24 20 10 3 40 50 60 70 80 90 figure 4. calibration time initial calibration is required after power-up or any other time the laser has been disabled. disabling the ad9661a drives the hold capacitor to ? v ref . in this case, or in any case where the output current is more than 10% out of calibration, r will range from 300 w to 550 w for the model above; the higher value should be used for calcul ating the worst case calibration time. following the example above, if c hold were chosen as 4.5 nf, then t = rc = 550 w 4.5 nf would be 2.48 m s. for an initial calibration error < 1%, the initial calibration time should be > 5 t = 12.36 m s. initial calibration time will actually be better than this calcula- tion indicates, as a significant portion of the calibration time will be within 10% of the final value, and the output resistance in the ad9660s t/h decreases as the hold voltage approaches its final value. recalibration is functionally identical to initial calibration, but the loop need only correct for droop. because droop is assumed to be a small percentage of the initial calibration (< 10%), the resistance for the model above will be in the range of 75 w to 140 w . again, the higher value should be used to estimate the worst case time needed for recalibration. continuing with the example above, since the droop error dur- ing hold time is < 5%, we meet the criteria for recalibration and t = rc = 140 w 4.5 nf = 0.64 m s. to get a final error of 1% after recalibration, the 5% droop must be corrected to within a 20% error (20% 5% = 1%). a 2 t recalibration time of 1.2 m s is sufficient. continuous recalibration in applications where the hold capacitor is small (< 500 pf) and the write pulse signals always have a pulse width > 25 ns, the user may continuously calibrate the feedback loop. in such an application, the cal signal should be held logic low, and the pulse signal will control loop calibration via the internal and gate. in such application, it is important to optimize the layout for the tza (power monitor, gain, r gain and c gain ). driving the analog inputs the power level input of the ad9661a drives the track and hold amplifier and allows the user to adjust the amount of output current as described above. the input voltage range is v ref to v ref + 1.6 v, requiring the user to create an offset of v ref for a ground based signal (see below for description of the on board level shift circuit). the circuit below will perform the level shift and scale the output of a dac whose output is from ground to a positive voltage. this solution is especially attrac- tive because both the dac and the op amp can run off a single +5 v supply, and the op amp doesnt have to swing rail to rail. dac v dac op191 +5v v ref + v dac = v power level r2 r1 bias level v ref ad9661a r1 r1 r2 r2 figure 5. driving the analog inputs using the level shift circuit the ad9661a includes an on board level shift circuit to provide the offset described above. the input, level shift in, has an input range from 0.1 v to 1.6 v. the output, level shift out, has a range from v ref to v ref +1.6 v, and can drive power monitor. the linearity of the level shift cir- cuit is poor for inputs below 100 mv. between 100 mv and 1.6 v it is about 7 bits accurate. layout considerations as in all high speed applications, proper layout is critical; it is particularly important when both analog and digital signals are involved. analog signal paths should be kept as short as possible, and isolated from digital signals to avoid coupling in noise. in particular, digital lines should be isolated from output, sense in, power level, level shift in power monitor, and hold traces. digital signal paths should also be kept short, and run lengths matched to avoid propagation delay mismatch. layout of the ground and power supply circuits is also critical. a single, low impedance ground plane will reduce noise on the circuit ground. power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit. 0.1 m f surface mount capacitors, placed as close as possible to the ad9661a +v s connections, and the +v s connection to the laser diode meet this requirement. multilayer circuit boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance power planes to further reduce noise.
ad9661a rev. 0 C8C minimizing the impedance of the output current path because of the very high current slew that the ad9661a is capable of producing (120+ ma in 1.5 ns), the inductance of the output current path to and from the laser diode is critical. a good layout of the output current path will yield high quality light pulses with rise times of about 1.5 ns and less than 5% overshoot. a poor layout can result in significant overshoot and ringing. the most important guideline for the layout is to mini- mize the impedance (mostly inductance) of the output current path to the laser. it is important to recognize that the laser current path is a closed loop. the figure illustrates the path that current travels: (1) from the +v s connection at the anode of the laser to the cathode (2) from the cathode to the output pins of the ad9661a (3) through the output drive circuit of the ad9661a, (4) through the return path (ground plane in the illustration) (5) through the bypass capacitors back to the +v s connection of the laser diode. the inductance of this loop can be minimized by placing the laser as close to the ad9661a as possible to keep the loop short, and by placing the send and re- turn paths on adjacent layers of the pc board to take advantage of mutual coupling of the path inductances. this mutual cou- pling effect is the most important factor in reducing inductance in the current path. the trace from the output pins of the ad9661a to the cathode of the laser should be several millimeters wide and should be as direct as possible. the return current will choose the path of least resistance. if the return path is the ground plane, it should have an unbroken path, under the output trace, from the laser anode back to a the ad9661a. if the return path is not the ground plane (such as on a two layer board, or on the +v s plane), it should still be on the board plane adjacent to the plane of the output trace. if the current cannot return along a path that follows the output trace, the inductance will be drasti- cally increased and performance will be degraded. ground plane bypass caps ground pin connections output pin connections pin assignments laser diode current path segments (see text) 25 24 23 22 21 20 19 mutual coupling reduces inductance 4 5 2 1 3 ad9661a 26 +v s plane figure 6. laser diode current loop optimizing the feedback layout in applications where the dynamic performance of the analog feedback loop is important, it is necessary to optimize the layout of the gain resistor, r gain , as well as the monitor current path to sense in. such applications include systems which recali- brate the write loop on pulses as short as 25 ns, and closed-loop applications. the best possible tza settling will be achieved by using a single carbon surface mount resistor (usually 5% tolerance) for r gain and small surface mount capacitor for c gain . because the gain pin (pin 5) is essentially connected to the inverting input of the tza, it is very sensitive to stray capacitance. r gain should be placed between pin 5 and pin 6, as close as possible to pin 5. small traces should be used, and the ground and +v s planes adjacent to the trace should be removed to further mini- mize stray capacitance. the trace from sense in to the anode of the pin photodetec- tor should be thin and routed away from the laser cathode trace. example calculations the example below (in addition to the one included in the sec- tions above) should guide users in choosing r gain , c gain , the hold capacitor values, and worst case calibration times. system requirements: ? laser power: 4 mw 2% ? hold time: 0.5 ms laser diode/photo diode characteristics: ? laser efficiency 0.3 mw/ma ? monitor current : 0.2 ma/mw ? from the laser power requirements and efficiency we can estimate: d i out max = 4 mw (2.0%)/ 0.3 mw ma ? ? ? ? = 266.6 m a .
ad9661a rev. 0 C9C ? choosing a hold caps based on this: c hold = 18 10 9 0.5 ms 266.6 m a = 0.034 m f ? the initial calibration time for < 0.1% error: 7 t= 7 rc = 7 550 w 0.034 m f = 130.9 m s ? recalibration for a 0.1% error after 2% droop (need to correct within 5%): 3 t = 3 rc = 3 140 w 0.034 m f = 14.28 m s ? from the monitor current specification and the max power specified: i monitor max = 4 mw 0.2 ma mw = 800 m a and r gain = 1. 6 v i monitor max 50 w= 2.0 k w ?c gain would be chosen from the table as 3 pf for safe compensation. 1ns/div 20ns/div pulse input (ttl) laser power 20mv/div laser power 20mv/div figure 7. driving 78n20 laser diode @ 5 mw typical performance characteristics
20ns 10mv +5v 1k w 10 w to scope mpsh81 33pf hold sense in output ad9661a power monitor gain power level pulsel low high 3v 2v 2pf 1k w figure 9. typical ad9661a closed-loop pulse response v hold ?v 180 40 0 1.7 3.2 2 i out ?ma 2.3 2.9 20 2.6 60 80 100 120 140 160 3.5 3.8 4.1 4.4 4.2 figure 8. typical ad9661a v/i transfer function ad9661aCtypical performance characteristics rev. 0 C10C
ad9661a rev. 0 C11C ad9661a evaluation board the ad9661a evaluation board is comprised of two printed circuit boards. the laser diode driver (ldd) resource board is both a digital pattern generator and an analog reference gen- erator (see ldd resource board block diagram.) the board is controlled by an ibm compatible personal computer through a standard printer cable. the resource board interfaces to the ad9661a dut board, which contains the ad9661a, a level shift circuit for the analog input, and a socket for an n type laser diode. a dummy load circuit for the laser diode is in- cluded for evaluation. power for all the boards is provided through the banana jacks on the ad9661a dut board. these should be connected to a linear, +5 v power supply. schematics for the ldd resource board, ad9661a dut, and dummy load are included, along with a bill of mate- rial and layout information. please contact applications for additional information. figure 10. ldd resource board block diagram ad9661a dummy load circuit/ laser diode socket optional level shift circuit ad9661a evaluation board 20 5 input smb connectors for digital controls 20-pin header for analog controls figure 11. evaluation board block diagram 40mhz clock oscillator 32k x 16 memory output smb connectors address counter and resource controller readback latch digital pattern generator centronics connector p1 standard parallel printer cable ibm-compatible pc with windows parallel printer port 8 8 x1 x1 0C2.55v 0C2.55v analog reference laser diode driver resource board j4 j5 j7 j8 j6 j2 cal (jcalb) disable (jdis) pulse2 (jpulb) unused trigger pulse1 (jpul) 20-pin header j3 12 11 r9 r8 ad9661a level shift in +5v power supply ground 17C20 1C10 external level shift circuit pulse width modulator (ad9560) output buffer interface to ad9661a evaluation board dac 1 dac 2
ad9661a rev. 0 C12C outline dimensions dimensions shown in inches and (mm). 28-pin plastic soic (r-28) 28 15 14 1 0.712 (18.08) 0.700 (17.78) 0.419 (10.64) 0.393 (9.98) 0.300 (7.60) 0.292 (7.40) pin 1 seating plane 0.012 (0.30) 0.004 (0.10) 0.019 (0.48) 0.014 (0.36) 0.104 (2.64) 0.093 (2.36) 0.0500 (1.27) bsc 0.013 (0.33) 0.009 (0.23) 0.04 (1.02) 0.024 (0.61) c2079C6C10/95 printed in u.s.a.

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