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vsc056 data sheet enhanced two-wire seri al backplane controller revision 4.1 january 2008 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim?s website at www.maxim-ic.com. maxim integrated products 1 of 134 to order the vsc056 device, see ?ordering information,? page 134. g eneral d escription the vsc056 device is an i/o-intensive pe ripheral device that is intended to be part of a cost-effective fibre channel arbitrated loop (fc-al), small comp uter system interface (scsi), serial attached scsi (sas), or serial ata (sata) enclosure management solution. the device contains an address- programmable two-wire serial interface, a block of control and status registers, i/o port control logic, specialized port bypass control logic, and a clock- generation block. along with an external crystal, the device can be configured to support up to 64 bi ts of general-purpose i/o; or 16 bits of general-purpose i/o, 32 bits of po rt bypass control (16 pairs supporting 16 drives), eight fan speed monitoring inputs, and eight pulse-width modulated general-purpose control outputs. the vsc056 supports various combinations of individual po rt bypass circuit (pbc), clock recovery unit (cru), and signal detect unit (sdu) functions, as we ll as integrated solutions. the control register portion of the device allows the user to individua lly program each i/o pin as an input, an output, or an open- drain or open-source output. f eatures ? up to 64 bits of user-definable, bidirectional general-purpose inputs and outputs ? integrated port bypass, clock recovery and signal detect support for up to 16 drives ? eight programmable fan speed monitoring inputs ? eight programmable pulse-width modulated fan control outputs ? up to 32 programmable input-to-output bypass pairs ? two clock input ranges: 8.0 mhz to 12.5 mhz (external crystal or external clock source) and 32.0 mhz to 75.0 mhz (external clock source) ? selectable direct led drive flashing capability ? pin-programmable addressing for up to 16 devices on a single serial bus ? 5-v tolerant high current i/o, slave mode two-wire serial interface and interrupt output ? ten programmable led pulse train circuits ? one 24-bit general-purpose timer (supports a timeout greater than four seconds with a 12.5 mhz core clock) ? up to 16 subaddressed master mode two-wire serial interface ports ? external reset of the sl ave two-wire serial core ? enhanced fan speed monitor input filters ? 20% of package pins are power and ground for excellent noise immunity and long-term reliability a pplications ? enterprise storage environments ? storage area network (san) appliances ? network attached storage (nas) systems ? fabric attached storage (fas) systems ? rack-mounted servers with raid ? jbod arrays ? disk-based backup storage ? near-line storage replacement systems ? fixed-content storage systems
2 of 134 revision 4.1 january 2008 vsc056 data sheet additional control features include: selectable flash rates for direct led drive, input edge detection for interrupt generation, input to output bypass capability, fan speed monitoring control, and pulse-width modulated output control. support for sub-addressing additional two-wire serial slave devices using a set of seven control registers is included. this capability allows up to 16 independent master mode two-wire serial slave ports to be created using 32 of the i/o pins. the addressing capability of the vsc056 includes three pins, which are used for device addressing, as well as one pin that can be used to select two device t ype identifiers. sixteen vsc0 56 devices can be used in a single two-wire serial interface system. block diagram two-w ire slav e interf ace interrupt priority and control clock generator and div iders i/o ports i/o control and led flashing p0.0 ? p0.7 p1.0 ? p1.7 p2.0 ? p2.7 p3.0 ? p3.7 p4.0 ? p4.7 fan speed sensors port by pass control power-on reset cksel1 cksel0 sda scl a2 ? a0 asel int# osci osco cksel2 p5.0 ? p5.7 p6.0 ? p6.7 p7.0 ? p7.7 pulse-width modulation control sy ncen sy nc# reset
3 of 134 revision 4.1 january 2008 vsc056 data sheet t ypical a pplications fc-al drive enclosure configuration basic port bypass configuration support for up to 128 drives: backplane controller suppor ts up to two sets of cru/sdu functions and drives, and 16 backplane controllers can be attached simultane ously to the serial bus four-drive implementation is shown below; four-channel pbc with two cru/sdu functions and general- purpose i/o lines for drive control and stat us, and other enclosure control functions. figure 1. single loop, single controller with four drives driv e bay 1 driv e bay 2 driv e bay 3 driv e bay 4 vsc7147 vsc056 local i/o (x8) vsc120 embedded controller temperature sensor (lm75) flash mem ory two-wire serial interf ace pbc_en1 pbc_en2 pbc_en3 pbc_en4 power supplies leds (x8) pbc_en fans (x4) copper or optics x2 4 c 1 6 eeprom enhanced backplane controller vsc7142
4 of 134 revision 4.1 january 2008 vsc056 data sheet general-purpose i/o configuration controlled by general-purpose microcontroller with two-wire serial interface support for up to 1024 i/o lines: backplane controller sup ports up to 64 i/o lines and 16 backplane controllers can be simultaneously attached to the serial bus four-backplane controller implementation is shown here wi th shared open-drain interrupt figure 2. four backplane controllers, 256 bidirectional i/o lines microcontroller wit h two-wire serial interf ace two-wire serial interf ace interrupt (optional) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8)i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8)i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8)i/o (x8) i/o (x8) i/o (x8) i/o (x8) i/o (x8) vsc056 enhanced backplane controller vsc056 enhanced backplane controller vsc056 enhanced backplane controller vsc056 enhanced backplane controller
5 of 134 vsc056 data sheet revision 4.1 january 2008 general description.......... ................. ................................ ................. ................ ......... 1 features ............... ................. ................................ .............. ............... .............. ............ . 1 applications ............. ................ ................. ................ .......................................... ......... 1 typical applications ............ ................................ ................. ................ .............. ......... 3 revision history......... ................. ................ ........................................................ ......... 9 1 introduction ............ ................ ................. ................ ................. ................ ......... 10 2 functional descriptions ............. ................ ............................................. ......... 11 2.1 two-wire serial interface .................................................................................................. ..........11 2.2 control registers .......................................................................................................... ...............11 2.3 i/o logic ......................................................................................................................................13 2.4 clock generator ............................................................................................................ ..............13 2.5 power-on reset ............................................................................................................. ..............14 3 registers ............................................... ................. ................ ................. ........... 15 3.1 control registers .......................................................................................................... ...............15 3.2 control register definitions ............................................................................................... ..........21 3.2.1 00h: general-purpose i/o port 0 data (gpd0) .............................................................21 3.2.2 01h: general-purpose i/o port 1 data (gpd1) .............................................................22 3.2.3 02h: general-purpose i/o port 2 data (gpd2) .............................................................22 3.2.4 03h: general-purpose i/o port 3 data (gpd3) .............................................................23 3.2.5 04h: general-purpose i/o port 4 data (gpd4) .............................................................23 3.2.6 05h: general-purpose i/o port 5 data (gpd5) .............................................................24 3.2.7 06h: general-purpose i/o port 6 data (gpd6) .............................................................24 3.2.8 07h: general-purpose i/o port 7 data (gpd7) .............................................................25 3.2.9 10h: i/o port 0 data direction (ddp0) ...........................................................................25 3.2.10 11h: i/o port 1 data direction (ddp1) ...........................................................................26 3.2.11 12h: i/o port 2 data direction (ddp2) ...........................................................................26 3.2.12 13h: i/o port 3 data direction (ddp3) ...........................................................................27 3.2.13 14h: i/o port 4 data direction (ddp4) ...........................................................................27 3.2.14 15h: i/o port 5 data direction (ddp5) ...........................................................................28 3.2.15 16h: i/o port 6 data direction (ddp6) ...........................................................................28 3.2.16 17h: i/o port 7 data direction (ddp7) ...........................................................................29 3.2.17 20h: port bypass control 0 (pbc0) ...............................................................................30 3.2.18 21h: port bypass control 1 (pbc1) ...............................................................................31 3.2.19 22h: port bypass control 2 (pbc2) ...............................................................................32 3.2.20 23h: port bypass control 3 (pbc3) ...............................................................................33 3.2.21 24h: port bypass control 4 (pbc4) ...............................................................................34 3.2.22 25h: port bypass control 5 (pbc5) ...............................................................................35 3.2.23 26h: port bypass control 6 (pbc6) ...............................................................................36 contents
6 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.24 27h: port bypass control 7 (pbc7) ...............................................................................37 3.2.25 28h: port bypass control 8 (pbc8) ...............................................................................38 3.2.26 29h: port bypass control 9 (pbc9) ...............................................................................39 3.2.27 2ah: port bypass control 10 (pbc10) ...........................................................................40 3.2.28 2bh: port bypass control 11 (pbc11) ...........................................................................41 3.2.29 2ch: port bypass control 12 (pbc12) ..........................................................................42 3.2.30 2dh: port bypass control 13 (pbc13) ..........................................................................43 3.2.31 2eh: port bypass control 14 (pbc14) ...........................................................................44 3.2.32 2fh: port bypass control 15 (pbc15) ...........................................................................45 3.2.33 30h: fan speed control 0 (fsc0) .................................................................................46 3.2.34 31h: fan speed count overflow 0 (fsco0) .................................................................47 3.2.35 32h: fan speed current count 0 (fscc0) ...................................................................47 3.2.36 34h: fan speed control 1 (fsc1) .................................................................................48 3.2.37 35h: fan speed count overflow 1 (fsco1) .................................................................49 3.2.38 36h: fan speed current count 1 (fscc1) ...................................................................49 3.2.39 38h: fan speed control 2 (fsc2) .................................................................................50 3.2.40 39h: fan speed count overflow 2 (fsco2) .................................................................51 3.2.41 3ah: fan speed current count 2 (fscc2) ...................................................................51 3.2.42 3ch: fan speed control 3 (fsc3) ................................................................................52 3.2.43 3dh: fan speed count overflow 3 (fsco3) ................................................................53 3.2.44 3eh: fan speed current count 3 (fscc3) ...................................................................53 3.2.45 40h: fan speed control 4 (fsc4) .................................................................................54 3.2.46 41h: fan speed count overflow 4 (fsco4) .................................................................55 3.2.47 42h: fan speed current count 4 (fscc4) ...................................................................55 3.2.48 44h: fan speed control 5 (fsc5) .................................................................................56 3.2.49 45h: fan speed count overflow 5 (fsco5) .................................................................57 3.2.50 46h: fan speed current count 5 (fscc5) ...................................................................57 3.2.51 48h: fan speed control 6 (fsc6) .................................................................................58 3.2.52 49h: fan speed count overflow 6 (fsco6) .................................................................59 3.2.53 4ah: fan speed current count 6 (fscc6) ...................................................................59 3.2.54 4ch: fan speed control 7 (fsc7) ................................................................................60 3.2.55 4dh: fan speed count overflow 7 (fsco7) ................................................................61 3.2.56 4eh: fan speed current count 7 (fscc7) ...................................................................61 3.2.57 70h: pulse train control 00 (ptc00) ............................................................................62 3.2.58 71h: pulse train control 01 (ptc01) ............................................................................63 3.2.59 72h: pulse train control 10 (ptc10) ............................................................................64 3.2.60 73h: pulse train control 11 (ptc11) ............................................................................65 3.2.61 74h: pulse train control 20 (ptc20) ............................................................................66 3.2.62 75h: pulse train control 21 (ptc21) ............................................................................67 3.2.63 76h: pulse train control 30 (ptc30) ............................................................................68 3.2.64 77h: pulse train control 31 (ptc31) ............................................................................69 3.2.65 78h: pulse train control 40 (ptc40) ............................................................................70 3.2.66 79h: pulse train control 41 (ptc41) ............................................................................71 3.2.67 7ah: pulse train control 50 (ptc50) ............................................................................72
7 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.68 7bh: pulse train control 51 (ptc51) ............................................................................73 3.2.69 7ch: pulse train control 60 (ptc60) ............................................................................74 3.2.70 7dh: pulse train control 61 (ptc61) ............................................................................75 3.2.71 7eh: pulse train control 70 (ptc70) ............................................................................76 3.2.72 7fh: pulse train control 71 (ptc71) ............................................................................77 3.2.73 80h-87h: bit control port 0 (bcp00-bcp07) .................................................................78 3.2.74 88h: pulse train control 80 (ptc80) ............................................................................81 3.2.75 89h: pulse train control 81 (ptc81) ............................................................................82 3.2.76 8ch: pulse train control 90 (ptc90) ............................................................................83 3.2.77 8dh: pulse train control 91 (ptc91) ............................................................................84 3.2.78 90h-97h: bit control port 1 (bcp10-bcp17) .................................................................85 3.2.79 98h-9fh: pulse-width modulat ion control (pwmc0-pwmc7) .....................................87 3.2.80 a0h-a7h: bit control port 2 (bcp20-bcp27) ................................................................89 3.2.81 b0h-b7h: bit control port 3 (bcp30-bcp37) ................................................................91 3.2.82 c0h-c7h: bit control port 4 (bcp40-bcp47) ................................................................93 3.2.83 cch: general-purpose timer count 0 (gptc0) ...........................................................95 3.2.84 cdh: general-purpose timer count 1 (gptc1) ...........................................................95 3.2.85 ceh: general-purpose timer count 2 (gptc2) ...........................................................96 3.2.86 cfh: general-purpose timer enable (gpte) ...............................................................96 3.2.87 d0h-d7h: bit control port 5 (bcp50-bcp57) ................................................................97 3.2.88 e0h-e7h: bit control port 6 (bcp60-bcp67) ................................................................99 3.2.89 e8h: master interface clock divider (micd) ................................................................101 3.2.90 e9h: master interface port select (mips) ....................................................................102 3.2.91 eah: master interface data (mid) ...............................................................................102 3.2.92 ebh: master interface command (mic) ......................................................................103 3.2.93 ech: master interface low-level control (milc) ........................................................107 3.2.94 edh: master interface status (mis) .............................................................................107 3.2.95 eeh: master interface read data (mird) ...................................................................108 3.2.96 f0h-f7h: bit control port 7 (bcp70-bcp77) ..............................................................108 3.2.97 f8h: backplane controller interrupt status (bcis) ......................................................110 3.2.98 fch: backplane controller test (bct) ........................................................................111 3.2.99 fdh: clock select control (csc) ................................................................................111 3.2.100 feh: clock divider control (cdc) ...............................................................................113 3.2.101 ffh: backplane controller version (ver) ...................................................................114 4 electrical specifications ........... ................................ ............... .............. ......... 115 4.1 dc characteristics ......................................................................................................... ...........115 4.1.1 general-purpose i/o ports ..........................................................................................115 4.1.2 two-wire serial interface ............................................................................................116 4.1.3 address inputs ........................................................................................................... ..116 4.1.4 interrupt output ......................................................................................................... ...117 4.1.5 reset, test, and synchronization clock control inputs ..............................................117 4.1.6 device synchronization ...............................................................................................117 4.1.7 oscillator and clock input ............................................................................................118
8 of 134 vsc056 data sheet revision 4.1 january 2008 4.1.8 oscillator output ........................................................................................................ ..118 4.2 ac characteristics ......................................................................................................... ............119 4.2.1 external clock timing ..................................................................................................11 9 4.2.2 two-wire serial interface timing ................................................................................120 4.3 operating conditions ....................................................................................................... ..........121 4.4 maximum ratings ............................................................................................................ ..........121 4.5 two-wire serial interface operation ........................................................................................ ..122 4.6 oscillator requirements .................................................................................................... ........123 4.7 external reset circuit ..................................................................................................... ...........123 4.8 optional external tach filter ............................................................................................. .......124 5 pin descriptions ............ ................ ............................ ............... .............. ......... 125 5.1 pin diagram ................................................................................................................ ...............125 5.2 pin identifications ........................................................................................................ ..............127 6 package information ..... ................ ............................ ............... .............. ......... 132 6.1 thermal specifications ..................................................................................................... .........132 6.2 moisture sensitivity ....................................................................................................... ............132 6.3 package drawing ............................................................................................................ ...........132 7 ordering information ............. ................. ................ ............................... ......... 134
9 of 134 vsc056 data sheet revision 4.1 january 2008 r evision h istory this section describes changes that have been implemente d in this document. the chan ges are listed by revision, starting with the mo st recent publication. revision 4.1 revision 4.1 of this data sheet was published in january 2008. the following is a summary of the changes implemented in the data sheet. the power supply voltage for the recommended operating co nditions were correct ed. the minimum power supply voltage is 3.0 v and maximum is 3.6 v. for more information, see table 22 , page 121. revision 4.0 revision 4.0 of this data sheet was published in april 2007. the following is a summary of the changes implemented in the data sheet: the electrostatic discharge voltage was added. for charged device model, it is 1500 v. for human body model, it is a class 2 rating. the moisture sensitivity is now specified as level 3. revision 2.0 revision 2.0 of this data sheet was published in octobe r 2006. this is the first publication of this document.
10 of 134 vsc056 data sheet revision 4.1 january 2008 1 introduction this data sheet provides reference information fo r the maxim enhanced two- wire serial backplane controller, vsc056. it is intended for system designers and software and firmware developers who are using this device to support enclosure management fu nctions or other related remote i/o expansion tasks. thevsc056 is package and power supply compatible with the vsc055. the vsc056 is similar to the vsc055 in feature and function, except for differences in the reset and clock out functions. this document assumes that the user is familiar wi th the two-wire serial in terfaces, the programmable i/o control, and the operatio n of fc-al control functions, such as a pbc (port bypass controller), a cru (clock recovery unit), and an sdu (s ignal detect unit). the user may also need to be familiar with fibre channel arbitrated loop (f c-al) operation and scsi enclosure serv ices (ses).
11 of 134 vsc056 data sheet revision 4.1 january 2008 2 functional descriptions the vsc056 device is composed of five major functional blocks: a slave mode two-wire serial interface a block of control registers general-purpose i/o and specialized port bypass control logic a clock generator power-on reset control logic the vsc056 fully supports a generic two-wire serial interface and is compatible with other industry- standard devices that support this interface at both 100 khz and 400 khz. 2.1 two-wire serial interface the vsc056 device supports a single slave mode two- wire serial interface. all interchip communication to a microcontroller takes place over this bus. the interface supports a 3-bit addr ess bus that allows the user to select one of eigh t possible addresses. the address bus is co mpared to bits 3:1 of the slave address byte. the slave address byte is the first byte tr ansmitted to the device after a start condition. the vsc056 supports two pin-selectable, 4-bit device type identifier values, 1000b and 1100b. the address bits and the device identifier allow the use of up to 16 devices on a single two-wire serial interface. the serial interface control logic includes: a slave state machine address comparison logic serial-to-parallel and para llel-to-serial conversion register read/write control filtering for the clock and data line a read or write transaction is determined by the least significant bit (r/w) of the first byte transferred. write accesses require a 3-byte transfer. the first byte is the slave address with the r/w bit low, the second byte contains the register addr ess, and the third byte is the write data. read access requires a 4-byte transfer since data transfer directio n can not change after receipt of the slave address byte. the first byte is the slave address with the r/w bit low, the second byte contains the register address, the third byte is a repeated slave address with the r/w bit high, and the fourth byte is the read data. if the transaction is a write, the data will be latched into the appropriate register during the acknowledge of the third byte. all transactions to or from the device complete during the acknowledge of the third byte allowing the user to immediately initiate another transfer to the device. se quential read or write transactions are allowed and are extensions of the above protocol with additional data bytes added to the end of the transaction. all sequential transactions cause the internal address to increment by one, regardless of the register address. 2.2 control registers the vsc056 device contains six groups of control re gisters. each group supports a specific function within the device as follows: the first group is the port data registers the second group is the data direction registers the third group contains special bit control features
12 of 134 vsc056 data sheet revision 4.1 january 2008 the fourth group supports the port bypass control function the fifth group supports fan speed monitoring the sixth group supports pulse-width modulated fan speed control the vsc056 device contains 164 regi sters to support all re quired functions. in no rmal i/o operation, each 8-bit group of i/o pins are controlled by a pair of regi sters, port data and data direction. the use of these pairs of registers allows each i/o line to be individually configured as an input wi th internal pull-up, output or open-drain output with internal pull-up. the bit control features are enabled through a separate register for each i/o pin. the bit control registers allow the user to independently confi gure each i/o pin to enable one of th e special control features, as well as to control port data and data di rection (which are shadowed copies of the standard control bits found in the port data and data direction registers). each i/o pin that has been configured as an input can also be configured to assert the open-drain interrupt pin when a rising edge, a falling edge, or either edge is detected on the i/o pin. an interrupt status register pr ovides the user with a binary indication of which i/o pin is the source of the current inte rrupt. each i/o pin that is configur ed as an output can automatically generate one of seven selectable flashing rates, which can be driven in an open source or open drain mode. additionally, two of the standard flash rates can be modified as well as eight dedicated programmable circuits to generate user defined pulse trains for un ique flashing sequences. by providing all i/o control capability in a single register, the user can control the operation of the i/o on a pin-by-pin basis. two additional bits in the odd-numbered bit control regist ers of each port can configure the pin as an output, which follows the corresponding even-numbered input of each port. as an exam ple, p0.0 becomes the input source of p0.1, which would be programmed as an output operating in one of the three available modes. the outputs can be configured as totem pole, open-drain or open-source dr ive, allowing a closer approximation of the input driver. the port bypass registers co ntrol the operation of a selected group of i/o lines, which can be dedicated to support various combinations of individual pbc/cr u/sdu functions and integrated solutions. enabling port bypass control causes the normal or bit control regi ster settings to be overridden. any further changes to the affected registers have no effect. each port b ypass control register automa tically configures the i/o lines to support a force bypass output and a signal detected input. the fan speed registers control the operation of eight programmable inputs that can be used to monitor signals from fans equipped with tachometer outputs. enabling fan speed control causes the normal or bit control register settings to be overridden. any further changes to the affected registers have no effect. each group of three registers provides the capability to en able the function, to establish a user-defined rpm overflow value that indicates a fa ilure, and to determine the current rpm value of the fan. the digital filters on the fan speed inputs can be enabled to incr ease the normal 100 ns to 200 ns filter to 400 ns to 500 ns. the pulse-width modulation control registers enable inte rnal logic to provide duty cycles of 0% to 100% in 3% increments at default frequencies of 26 kh z, 52 khz, and 104 khz. optionally, the pwm outputs can be programmed for three additional frequency ranges of 5.2 khz, 10.4 khz, and 20.8 khz or 1.04 khz 2.08 khz, and 4.16 khz or 208 hz, 416 hz and 833 hz. these outputs can vary the speed of up to eight fans through the use of external drivers and power mosfets or pulse-width to voltage converters. they can also be used to support other pulse-width modulated requirements within the system.
13 of 134 vsc056 data sheet revision 4.1 january 2008 2.3 i/o logic each general-purpose 5-v tolerant i/o pin is controlled by a set of registers in the control register block. the i/o supports a high current drive output buffer that can be configured as a totem pole or open-drain driver. the input section of the i/o supports ttl signaling and includes an internal weak pull-up device. this allows unused i/o pins to be left unconnect ed without high-current drain issues. the port bypass control i/o pins, which are shared with port 3, port 4, port 5, and port 6, are generated using the same buffer logic as the other ports. wh en enabled in port bypass control mode, internal logic overrides the existing configuration, with each i/o pin dedicated to the specific port bypass function. all i/o lines default as inputs with the weak internal pull-up enabled. 2.4 clock generator clock generation for the device is composed of an in ternal oscillator, divider circuits, and a distribution network. it supports nominal clock frequencies of: 8.0 mhz 8.33 mhz 8.854 mhz 10.0 mhz 33.33 mhz 40.0 mhz 50.0 mhz 53.125 mhz the three cksel inputs select one of the eight av ailable fixed clock frequencies. the internal low- frequency clock (8.0 mhz to 12.5 mhz) is used for filte ring incoming serial interface signals and interrupt sources, as well as for clocking the slave state mach ine. divided clocks provide the source for led flash rate generators. the oscillator provides a stable cloc k source for the device and re quires the use of an off- chip crystal with a frequency of 8.0 mhz, 8.33 mhz, 8.854 mhz, or 10.0 mhz and related passive components or external clock source. the available fixe d clock rates have been selected to allow the use of other system clocks which may be avai lable as well as low-cost crystals. the following table describes the cksel settings for the available fixed input clocks and the associated divider value. table 1. cksel settings cksel2 cksel1 cksel0 input clock divider internal clock vss vss vss 10.0 mhz n/a 10.0 mhz vss vss vdd 8.33 mhz n/a 8.33 mhz vss vdd vss 8.854 mhz n/a 8.854 mhz vss vdd vdd 8.0 mhz n/a 8.0 mhz vdd vss vss 40.0 mhz 4 10.0 mhz vdd vss vdd 33.33 mhz 4 8.33 mhz vdd vdd vss 53.125 mhz 6 8.854 mhz vdd vdd vdd 50.0 mhz 6 8.33 mhz
14 of 134 vsc056 data sheet revision 4.1 january 2008 the vsc056 device can operate at frequencies other than those listed in the above table and maintain accurate fan speed and led control frequencies, as we ll as continue to meet both the standard mode (100 khz) and fast mode (400 khz) serial interfa ce timings. frequencies from 8.0 mhz to 12.5 mhz and 32.0 mhz to 75.0 mhz are allowable as long as they m eet the ac timing requirem ents. for information on ac timing requirements, see ?ac characteristics,? page 119. the clock divider control register (cdc), located at feh, can be programmed to override the divider value selected by the cksel input pins and adjust the divided clock source used for the fan speed and led control logic. the pulse-width modulated outputs are not controlled by this logic and can vary based on the input frequency. for examples of various frequency settings, based on both the cksel inputs and the appropriate cdc re gister value, see ?feh: clock divider control (cdc),? page 113. logic within the vsc056 synchronizes the divided cloc ks between devices attached to the same two-wire serial bus with no more than 200 ns of skew when th e fixed divider frequencies are used. multiple devices can then be used to drive differ ent leds at the same frequency, providing a synchronized visible indication. devices attached to di fferent two-wire serial busses ca n be synchronized by enabling the sync# pin. this pin, which is connected to the sync# pin of all vsc056 devices in the system, provides a sync pulse based on a programmable delay that is gr eater than the slowest selected led flash rate. for more information about the programmabl e capabilities of th is feature, see ?fdh: clock select control (csc),? page 111. 2.5 power-on reset power-on reset (por) is accomplished by the use of an internal por cell. the external reset# pin provides the ability to reset the tw o-wire serial interface core, allowing for easy recovery of the two-wire serial bus after a warm restart or at any time deemed appropriate w ithin the system. if the external reset# pin is used, it can be driven by a power supp ly supervisor circuit, a reset pulse sourced from another device, or a simple circui t composed of a resist or, a capacitor, and a diode. the external reset source does not have to be synchronous to the vsc056 clock input. if the external resistor-capacitor-diode circuit is used, the components selected must be able to provide a valid low to high transition after v dd is stable. if the reset# pin is not used, it must be connected to v dd . after power on, the serial interface state machine always returns an id le state while waiting for a start co ndition to appear on the scl and sda pins. a proper power-on reset sequence clears the serial interface state machine, the clock generators, the control registers, the i/o control logic, and the port bypass control logic. the divided clocks used for led flash rate generation are also in a known state. regardless of the effectiveness of the power-on reset mechanism, it is strongly recommended that the control registers and the i/o control logic be cleared through the soft reset register bit. this can be accomplished by writing a 80h to the bct register (fch), followed immediately by a two-wire stop condition. this bit is self-resetting and does not require further attention.
15 of 134 vsc056 data sheet revision 4.1 january 2008 3registers this section contains descriptions for the device-specific control registers. all register locations are fixed within the device and are mapped for easy acce ss, as well as for future enhancements. 3.1 control registers the control register section is separated into three su b-sections: a register map, an address map, and bit level descriptions of all registers. the register map lists all registers by operating address. the address map shows the relative layout of all control registers. although all registers can be accessed at any time and no register function interfe res with the operation of the serial interface, changing regist er bits does have an immediate effect on the respective i/o lines. the following table provides the mapping of the registers. table 2. register map data memory address access label description 00h r/w gpd0 general-purpose i/o port 0 data register 01h r/w gpd1 general-purpose i/o port 1 data register 02h r/w gpd2 general-purpose i/o port 2 data register 03h r/w gpd3 general-purpose i/o port 3 data register 04h r/w gpd4 general-purpose i/o port 4 data register 05h r/w gpd5 general-purpose i/o port 5 data register 06h r/w gpd6 general-purpose i/o port 6 data register 07h r/w gpd7 general-purpose i/o port 7 data register 10h r/w ddp0 i/o port 0 data direction register 11h r/w ddp1 i/o port 1 data direction register 12h r/w ddp2 i/o port 2 data direction register 13h r/w ddp3 i/o port 3 data direction register 14h r/w ddp4 i/o port 4 data direction register 15h r/w ddp5 i/o port 5 data direction register 16h r/w ddp6 i/o port 6 data direction register 17h r/w ddp7 i/o port 7 data direction register 20h r/w pbc0 port bypass control 0 register 21h r/w pbc1 port bypass control 1 register 22h r/w pbc2 port bypass control 2 register 23h r/w pbc3 port bypass control 3 register 24h r/w pbc4 port bypass control 4 register 25h r/w pbc5 port bypass control 5 register 26h r/w pbc6 port bypass control 6 register 27h r/w pbc7 port bypass control 7 register 28h r/w pbc8 port bypass control 8 register
16 of 134 vsc056 data sheet revision 4.1 january 2008 29h r/w pbc9 port bypass control 9 register 2ah r/w pbc10 port bypass control 10 register 2bh r/w pbc11 port bypass control 11 register 2ch r/w pbc12 port bypass control 12 register 2dh r/w pbc13 port bypass control 13 register 2eh r/w pbc14 port bypass control 14 register 2fh r/w pbc15 port bypass control 15 register 30h r/w fsc0 fan speed control 0 register 31h r/w fsco0 fan speed count overflow 0 register 32h r fscc0 fan speed current count 0 register 34h r/w fsc1 fan speed control 1 register 35h r/w fsco1 fan speed count overflow 1 register 36h r fscc1 fan speed current count 1 register 38h r/w fsc2 fan speed control 2 register 39h r/w fsco2 fan speed count overflow 2 register 3ah r fscc2 fan speed current count 2 register 3ch r/w fsc3 fan speed control 3 register 3dh r/w fsco3 fan speed count overflow 3 register 3eh r fscc3 fan speed current count 3 register 40h r/w fsc4 fan speed control 4 register 41h r/w fsco4 fan speed count overflow 4 register 42h r fscc4 fan speed current count 4 register 44h r/w fsc5 fan speed control 5 register 45h r/w fsco5 fan speed count overflow 5 register 46h r fscc5 fan speed current count 5 register 48h r/w fsc6 fan speed control 6 register 49h r/w fsco6 fan speed count overflow 6 register 4ah r fscc6 fan speed current count 6 register 4ch r/w fsc7 fan speed control 7 register 4dh r/w fsco7 fan speed count overflow 7 register 4eh r fscc7 fan speed current count 7 register 70h r/w ptc00 pulse train 0 control 0 register 71h r/w ptc01 pulse train 0 control 1 register 72h r/w ptc10 pulse train 1 control 0 register 73h r/w ptc11 pulse train 1 control 1 register 74h r/w ptc20 pulse train 2 control 0 register 75h r/w ptc21 pulse train 2 control 1 register 76h r/w ptc30 pulse train 3 control 0 register 77h r/w ptc31 pulse train 3 control 1 register 78h r/w ptc40 pulse train 4 control 0 register table 2. register map (continued) data memory address access label description
17 of 134 vsc056 data sheet revision 4.1 january 2008 79h r/w ptc41 pulse train 4 control 1 register 7ah r/w ptc50 pulse train 5 control 0 register 7bh r/w ptc51 pulse train 5 control 1 register 7ch r/w ptc60 pulse train 6 control 0 register 7dh r/w ptc61 pulse train 6 control 1 register 7eh r/w ptc70 pulse train 7 control 0 register 7fh r/w ptc71 pulse train 7 control 1 register 80h r/w bcp00 bit control port 0 - bit 0 register 81h r/w bcp01 bit control port 0 - bit 1 register 82h r/w bcp02 bit control port 0 - bit 2 register 83h r/w bcp03 bit control port 0 - bit 3 register 84h r/w bcp04 bit control port 0 - bit 4 register 85h r/w bcp05 bit control port 0 - bit 5 register 86h r/w bcp06 bit control port 0 - bit 6 register 87h r/w bcp07 bit control port 0 - bit 7 register 88h r/w ptc80 pulse train 8 control 0 register 89h r/w ptc81 pulse train 8 control 1 register 8ch r/w ptc90 pulse train 9 control 0 register 8dh r/w ptc91 pulse train 9 control 1 register 90h r/w bcp10 bit control port 1 - bit 0 register 91h r/w bcp11 bit control port 1 - bit 1 register 92h r/w bcp12 bit control port 1 - bit 2 register 93h r/w bcp13 bit control port 1 - bit 3 register 94h r/w bcp14 bit control port 1 - bit 4 register 95h r/w bcp15 bit control port 1 - bit 5 register 96h r/w bcp16 bit control port 1 - bit 6 register 97h r/w bcp17 bit control port 1 - bit 7 register 98h r/w pwmc0 pulse-width modulation control 0 register 99h r/w pwmc1 pulse-width modulation control 1 register 9ah r/w pwmc2 pulse-width modulation control 2 register 9bh r/w pwmc3 pulse-width modulation control 3 register 9ch r/w pwmc4 pulse-width modulation control 4 register 9dh r/w pwmc5 pulse-width modulation control 5 register 9eh r/w pwmc6 pulse-width modulation control 6 register 9fh r/w pwmc7 pulse-width modulation control 7 register a0h r/w bcp20 bit control port 2 - bit 0 register a1h r/w bcp21 bit control port 2 - bit 1 register a2h r/w bcp22 bit control port 2 - bit 2 register a3h r/w bcp23 bit control port 2 - bit 3 register a4h r/w bcp24 bit control port 2 - bit 4 register table 2. register map (continued) data memory address access label description
18 of 134 vsc056 data sheet revision 4.1 january 2008 a5h r/w bcp25 bit control port 2 - bit 5 register a6h r/w bcp26 bit control port 2 - bit 6 register a7h r/w bcp27 bit control port 2 - bit 7 register b0h r/w bcp30 bit control port 3 - bit 0 register b1h r/w bcp31 bit control port 3 - bit 1 register b2h r/w bcp32 bit control port 3 - bit 2 register b3h r/w bcp33 bit control port 3 - bit 3 register b4h r/w bcp34 bit control port 3 - bit 4 register b5h r/w bcp35 bit control port 3 - bit 5 register b6h r/w bcp36 bit control port 3 - bit 6 register b7h r/w bcp37 bit control port 3 - bit 7 register c0h r/w bcp40 bit control port 4 - bit 0 register c1h r/w bcp41 bit control port 4 - bit 1 register c2h r/w bcp42 bit control port 4 - bit 2 register c3h r/w bcp43 bit control port 4 - bit 3 register c4h r/w bcp44 bit control port 4 - bit 4 register c5h r/w bcp45 bit control port 4 - bit 5 register c6h r/w bcp46 bit control port 4 - bit 6 register c7h r/w bcp47 bit control port 4 - bit 7 register cch r/w gptc0 general-purpose timer count 0 register cdh r/w gptc1 general-purpose timer count 1 register ceh r/w gptc2 general-purpose timer count 2 register cfh r/w gpte general-purpose timer enable register d0h r/w bcp50 bit control port 5 - bit 0 register d1h r/w bcp51 bit control port 5 - bit 1 register d2h r/w bcp52 bit control port 5 - bit 2 register d3h r/w bcp53 bit control port 5 - bit 3 register d4h r/w bcp54 bit control port 5 - bit 4 register d5h r/w bcp55 bit control port 5 - bit 5 register d6h r/w bcp56 bit control port 5 - bit 6 register d7h r/w bcp57 bit control port 5 - bit 7 register e0h r/w bcp60 bit control port 6 - bit 0 register e1h r/w bcp61 bit control port 6 - bit 1 register e2h r/w bcp62 bit control port 6 - bit 2 register e3h r/w bcp63 bit control port 6 - bit 3 register e4h r/w bcp64 bit control port 6 - bit 4 register e5h r/w bcp65 bit control port 6 - bit 5 register e6h r/w bcp66 bit control port 6 - bit 6 register e7h r/w bcp67 bit control port 6 - bit 7 register e8h r/w micd master interface clock divider register table 2. register map (continued) data memory address access label description
19 of 134 vsc056 data sheet revision 4.1 january 2008 the following table provides the mapping of the register sets by address. e9h r/w mips master interface port select register eah r/w mid master interface data register ebh r/w mic master interface command register ech r/w milc master interface low-level control register edh r mis master interface status register eeh r mird master interface read data register f0h r/w bcp70 bit control port 7 - bit 0 register f1h r/w bcp71 bit control port 7 - bit 1 register f2h r/w bcp72 bit control port 7 - bit 2 register f3h r/w bcp73 bit control port 7 - bit 3 register f4h r/w bcp74 bit control port 7 - bit 4 register f5h r/w bcp75 bit control port 7 - bit 5 register f6h r/w bcp76 bit control port 7 - bit 6 register f7h r/w bcp77 bit control port 7 - bit 7 register f8h r/w bcis backplane controller interrupt status register fch r/w bct backplane controller test register fdh r/w csc clock select control register feh r/w cdc clock divider control register ffh r ver backplane controller version register table 3. address map 11b 10b 01b 00b address gpd3 gpd2 gpd1 gpd0 00h gpd7 gpd6 gpd5 gpd4 04h reserved reserved reserved reserved 08h-0ch ddp3 ddp2 ddp1 ddp0 10h ddp7 ddp6 ddp5 ddp4 14h reserved reserved reserved reserved 18h-1ch pbc3 pbc2 pbc1 pbc0 20h pbc7 pbc6 pbc5 pbc4 24h pbc11 pbc10 pbc9 pbc8 28h pbc15 pbc14 pbc13 pbc12 2ch reserved fscc0 fsco0 fsc0 30h reserved fscc1 fsco1 fsc1 34h reserved fscc2 fsco2 fsc2 38h reserved fscc3 fsco3 fsc3 3ch reserved fscc4 fsco4 fsc4 40h reserved fscc5 fsco5 fsc5 44h reserved fscc6 fsco6 fsc6 48h table 2. register map (continued) data memory address access label description
20 of 134 vsc056 data sheet revision 4.1 january 2008 reserved fscc7 fsco7 fsc7 4ch reserved reserved reserved reserved 50h-6ch ptc11 ptc10 ptc01 ptc00 70h ptc31 ptc30 ptc21 ptc20 74h ptc51 ptc50 ptc41 ptc40 78h ptc71 ptc70 ptc51 ptc50 7ch bcp03 bcp02 bcp01 bcp00 80h bcp07 bcp06 bcp05 bcp04 84h reserved reserved ptc41 ptc40 88h reserved reserved ptc51 ptc50 8ch bcp13 bcp12 bcp11 bcp10 90h bcp17 bcp16 bcp15 bcp14 94h pwmc3 pwmc2 pwmc1 pwmc0 98h pwmc7 pwmc6 pwmc5 pwmc4 9ch bcp23 bcp22 bcp21 bcp20 a0h bcp27 bcp26 bcp25 bcp24 a4h reserved reserved reserved reserved a8h-ach bcp33 bcp32 bcp31 bcp30 b0h bcp37 bcp36 bcp35 bcp34 b4h reserved reserved reserved reserved b8h-bch bcp43 bcp42 bcp41 bcp40 c0h bcp47 bcp46 bcp45 bcp44 c4h reserved reserved reserved reserved c8h gpte gptc2 gptc1 gptc0 cch bcp53 bcp52 bcp51 bcp50 d0h bcp57 bcp56 bcp55 bcp54 d4h reserved reserved reserved reserved d8h-dch bcp63 bcp62 bcp61 bcp60 e0h bcp67 bcp66 bcp65 bcp64 e4h mic mid mips micd e8h reserved mird mis milc ech bcp73 bcp72 bcp71 bcp70 f0h bcp77 bcp76 bcp75 bcp74 f4h reserved reserved reserved bcis f8h ver cdc csc bct fch table 3. address map (continued) 11b 10b 01b 00b address
21 of 134 vsc056 data sheet revision 4.1 january 2008 3.2 control register definitions the control register definitions provides a bit-level description of all register bits, including power on and default values. the terms set and assert refer to bits th at are programmed to a bina ry 1. the terms reset, de- assert, and clear refer to bits that are programmed to a binary 0. reserv ed bits are represented by res and always return an unknown value. these bits should be masked. bits that are reserved should never be set to a binary 1, because these bits may be de fined in future versions of the device. 3.2.1 00h: general-purpose i/ o port 0 data (gpd0) the following table shows the bit assignments for the general-purpose i/o port 0 data register. register name: gpd0 address: 00h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd0.7?0 r/w general-purpose data when the i/o pin is enabled as an output, wr iting these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, reading these register bits represent the current voltage applied to the pin. at no time do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. figure 3. i/o port block diagram d ck q filter gpd read data gpd write data dd write data dd read data i/o port d ck q
22 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.2 01h: general-purpose i/ o port 1 data (gpd1) the following table shows the bit assignments for th e general-purpose i/o port 1 data register. 3.2.3 02h: general-purpose i/ o port 2 data (gpd2) the following table shows the bit assignments for the general-purpose i/o port 2 data register. register name: gpd1 address: 01h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd1.7-0 r/w general-purpose data when the i/o pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, reading these register bits represents the current voltage applied to the pin. at no time do the bits directly represent the value latched into the data register if a pin is enabled as an input and there is no signal applied, w eak internal pull-up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the le vel applied to the pin since each pin is an input by default. register name: gpd2 address: 02h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd2.7-0 r/w general-purpose data when the i/o pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, read ing these register bits represents the current voltage applied to the pin. at no time do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default.
23 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.4 03h: general-purpose i/ o port 3 data (gpd3) the following table shows the bit assignments for the general-purpose i/o port 3 data register. control of the individual i/o pins in this register can be ov erridden by the pbc0, pbc1, pbc2, and pbc3 registers when port bypass control is required. 3.2.5 04h: general-purpose i/ o port 4 data (gpd4) the following table shows the bit assignments for the general-purpose i/o port 4 data register. control of the individual i/o pins in this register can be ov erridden by the pbc4, pbc5, pbc6, and pbc7 registers when port bypass control is required. register name: gpd3 address: 03h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd3.7-0 r/w general-purpose data when the i/o pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading these register bits represents the current voltage applied to the pin. at no ti me do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull- up resistors hold the pin at a binary 1. after a reset or power on, the register bi ts are set to a binary 1, but the value returned from a register read is the leve l applied to the pin since each pin is an input by default. register name: gpd4 address: 04h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd4.7-0 r/w general-purpose data when the i/o pin is enabled as an output, wr iting these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, read ing these register bits represents the current voltage applied to the pin. at no time do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull- up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, but the value returned from a register read is the le vel applied to the pin since each pin is an input by default.
24 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.6 05h: general-purpose i/ o port 5 data (gpd5) the following table shows the bit assignments for the general-purpose i/o port 5 data register. control of the individual i/o pins in this register can be over ridden by the pbc8, pbc9, pbc10, and pbc11 registers when port bypass control is required. 3.2.7 06h: general-purpose i/ o port 6 data (gpd6) the following table shows the bit assignments for the general-purpose i/o port 6 data register. control of the individual i/o pins in this register can be overridden by the pbc12, pbc13, pbc14, and pbc15 registers when port bypass control is required. register name: gpd5 address: 05h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd5.7-0 r/w general-purpose data when the i/o pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading these register bits represents the current voltage applied to the pin. at no ti me do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull- up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, but the value returned from a register read is the leve l applied to the pin since each pin is an input by default. register name: gpd6 address: 06h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd6.7-0 r/w general-purpose data when the i/o pin has been enabled as an output, writing these bits determines the data value that will be pres ent on the corresponding i/o pin. if the i/o pin has been enabled as an input, reading these register bits represents the current voltage applied to the pin. at no time do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull-up resistors hold the pin at a binary 1. after a reset or power on, the register bits are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default.
25 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.8 07h: general-purpose i/ o port 7 data (gpd7) the following table shows the bit assignments for the general-purpose i/o port 7 data register. 3.2.9 10h: i/o port 0 data direction (ddp0) the following table shows the bit assignments for the i/o port 0 data direction register. register name: gpd7 address: 07h reset value: xxxx_xxxxb bit bit label access description 7:0 gpd7.7-0 r/w general-purpose data when the i/o pin is enabled as an output, writing these bits determines the data value that will be present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading these register bits represents the current voltage applied to the pin. at no ti me do the bits directly represent the value latched into the data register. if a pin is enabled as an input and there is no signal applied, weak internal pull- up resistors hold the pin at a binary 1. after a reset or power on, the register bi ts are set to a binary 1, however, the value returned from a register read is the level applied to the pin since each pin is an input by default. register name: ddp0 address: 10h reset value: 1111_1111b bit bit label access description 7:0 ddp0.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source f unction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up.
26 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.10 11h: i/o port 1 data direction (ddp1) the following table shows the bit assignments for the i/o port 1 data direction register. 3.2.11 12h: i/o port 2 data direction (ddp2) the following table shows the bit assignments for the i/o port 2 data direction register. register name: ddp1 address: 11h reset value: 1111_1111b bit bit label access description 7:0 ddp1.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. register name: ddp2 address: 12h reset value: 1111_1111b bit bit label access description 7:0 ddp2.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up.
27 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.12 13h: i/o port 3 data direction (ddp3) the following table shows the bit assignments for the i/o port 3 data direction register. control of the individual i/o pins in this regist er can be overridden by the pbc0, pbc1, pbc2, and pbc3 registers when port bypass control is required. 3.2.13 14h: i/o port 4 data direction (ddp4) the following table shows the bit assignments for the i/o port 4 data direction register. control of the individual i/o pins in this register can be overridden by the pbc4, pbc5, pbc6, and pbc7 registers when port bypass control is required. register name: ddp3 address: 13h reset value: 1111_1111b bit bit label access description 7:0 ddp3.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source f unction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits ar e set to a binary 1, enabling the i/o as an input with weak pull-up. register name: ddp4 address: 14h reset value: 1111_1111b bit bit label access description 7:0 ddp4.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up.
28 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.14 15h: i/o port 5 data direction (ddp5) the following table shows the bit assignments for the i/o port 5 data direction register. control of the individual i/o pins in this regist er can be overridden by the pbc8, pbc9, pbc10, and pbc11 registers when port bypass control is required. 3.2.15 16h: i/o port 6 data direction (ddp6) the following table shows the bit assignments for the i/o port 6 data direction register. control of the individual i/o pins in this register can be overridden by the pbc12, pbc13, pbc14, and pbc15 registers when port bypass control is required. register name: ddp5 address: 15h reset value: 1111_1111b bit bit label access description 7:0 ddp5.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source f unction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. register name: ddp6 address: 16h reset value: 1111_1111b bit bit label access description 7:0 ddp6.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individual ly configured as a true bi directional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up.
29 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.16 17h: i/o port 7 data direction (ddp7) the following table shows the bit assignments for the i/o port 7 data direction register. register name: ddp7 address: 17h reset value: 1111_1111b bit bit label access description 7:0 ddp7.7-0 r/w data direction these bits determine the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source f unction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up.
30 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.17 20h: port bypass control 0 (pbc0) the following table shows the bit assignments for the port bypass control 0 register. this register affects the p3.1 and p3.0 pins. register name: pbc0 address: 20h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.1 and p3.0 are automatically configured as a force bypass (fb) output pin and a signal detect ed (sd) input pin. configurations for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p3.1 and p3.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p3.1 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circ uit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p3.0 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p3.1 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this regi ster, because the read value of the register bits is always available th rough an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p3.0 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal detect unit detects a high-speed signal. if this bit is reset, the signal detec t unit does not detect a high-speed signal.
31 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.18 21h: port bypass control 1 (pbc1) the following table shows the bit assignments for the port bypass control 1 register. this register functions the same as the port bypass control 0 re gister except it affects th e p3.3 and p3.2 pins. register name: pbc1 address: 21h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.3 and p3.2 are automatically configured as an fb output pin and an sd input pin. configurat ions for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p3.3 and p3.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p3.2 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypa ss function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p3.2 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p3.3 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an i nput synchronizer and filter. after the default state is determined, to ensure that the port bypass control functions are enabled correctly, write the default value to the fb bit of this register and set the pbcen bit. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indi cation of the p3.2 i/o pin, which is connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, the signal det ect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
32 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.19 22h: port bypass control 2 (pbc2) the following table shows the bit assignments for the port bypass control 2 register. this register functions the same as the port bypass control 0 re gister except it affects th e p3.5 and p3.4 pins. register name: pbc2 address: 22h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.5 and p3.4 ar e automatically configured as an fb output pin and an sd input pin. configurat ions for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p3.5 and p3.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p3.5 i/o pin, which is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass in put of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p3.4 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p3.5 output. note: because all i/o pins on the device po wer up as inputs wi th weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available throu gh an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additi onal writes to this regist er can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p3.4 i/o pin, which is connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, the signal detec t unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
33 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.20 23h: port bypass control 3 (pbc3) the following table shows the bit assignments for the port bypass control 3 register. this register functions the same as the port bypass control 0 re gister except it affects th e p3.7 and p3.6 pins. register name: pbc3 address: 23h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p3.7 and p3.6 ar e automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p3.7 and p3.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p3.7 i/o pin, which is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass in put of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p3.6 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p3.7 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit beco mes a read-only indication of the p3.6 i/o pin, which is connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, the signal detec t unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
34 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.21 24h: port bypass control 4 (pbc4) the following table shows the bit assignments for the port bypass control 4 register. this register functions the same as the port bypass control 0 re gister except it affects th e p4.1 and p4.0 pins. register name: pbc4 address: 24h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.1 and p4.0 are automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p4.1 and p4.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p4.1 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when th e synchronized and filtered p4.0 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p4.1 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to def ine the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, bec ause the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this re gister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p4.0 i/o pin, which is connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, the signal det ect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
35 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.22 25h: port bypass control 5 (pbc5) the following table shows the bit assignments for the port bypass control 5 register. this register functions the same as the port bypass control 0 re gister except it affects th e p4.3 and p4.2 pins. register name: pbc5 address: 25h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.3 and p4.2 are automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled thro ugh other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p4.3 and p4.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p4.3 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypas s function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p4.2 input is low, resulting in a maxi mum latency of 400 ns from detection of the loss of a high-speed signal to t he de-assertion of the p4.3 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that t he port bypass control functions are enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p4.2 i/o pin, which is connected to the si gnal detected output of a pbc/cru/sdu function. if this bit is set, the signal detect unit detects a high-speed signal. if this bit is reset, the signal detec t unit does not detect a high-speed signal.
36 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.23 26h: port bypass control 6 (pbc6) the following table shows the bit assignments for the port bypass control 6 register. this register functions the same as the port bypass control 0 re gister except it affects th e p4.5 and p4.4 pins. register name: pbc6 address: 26h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.5 and p4.4 are automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other contro l registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p4.5 and p4.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generat es an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p4.5 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p4.4 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p4.5 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to de fine the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, be cause the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the por t bypass control functions are enabled correctly. additional writes to this r egister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becomes a read-only indication of the p4.4 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal dete ct unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
37 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.24 27h: port bypass control 7 (pbc7) the following table shows the bit assignments for the port bypass control 7 register. this register functions the same as the port bypass control 0 re gister except it affects th e p4.7 and p4.6 pins. register name: pbc7 address: 27h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p4.7 and p4.6 ar e automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p4.7 and p4.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input genera tes an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p4.7 i/o pin, which is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass ci rcuit is in bypass mode. this register bit is automatically cl eared when the synchronized and filtered p4.6 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p4.7 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to defi ne the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this regi ster, because the read value of the register bits is always available thro ugh an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p4.6 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal detec t unit detects a high-speed signal. if this bit is reset, the signal detec t unit does not detect a high-speed signal.
38 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.25 28h: port bypass control 8 (pbc8) the following table shows the bit assignments for the port bypass control 8 register. this register functions the same as the port bypass control 0 re gister except it affects th e p5.1 and p5.0 pins. register name: pbc8 address: 28h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p5.1 and p5.0 ar e automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p5.1 and p5.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p5.1 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when th e synchronized and filtered p5.0 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p5.1 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is po ssible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, bec ause the read value of the register bits is always available through an i nput synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p5.0 i/o pin, which is connected to the signal detected output of a pbc/cru/sdu function. if this bit is set, the signal det ect unit detects a high-speed signal. if this bit is reset, the signal detec t unit does not detect a high-speed signal.
39 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.26 29h: port bypass control 9 (pbc9) the following table shows the bit assignments for the port bypass control 9 register. this register functions the same as the port bypass control 0 re gister except it affects th e p5.3 and p5.2 pins. register name: pbc9 address: 29h reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p5.3 and p5.2 are automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p5.3 and p5.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on t he signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p5.3 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass ci rcuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p5.2 input is low, resulting in a maxi mum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p5.3 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to def ine the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an i nput synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to th is register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit beco mes a read-only indication of the p5.2 i/o pin, which is connected to the si gnal detected output of a pbc/cru/sdu function. if this bit is set, the signal detect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
40 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.27 2ah: port bypass control 10 (pbc10) the following table shows the bit assignments for the port bypass control 10 register. this register functions the same as the port bypass control 0 re gister except it affects th e p5.5 and p5.4 pins. register name: pbc10 address: 2ah reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p5.5 and p5.4 are automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p5.5 and p5.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on t he signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p5.5 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass ci rcuit is in bypass mode. this register bit is automatically cleared when the synchronized and filtered p5.4 input is low, resulting in a maxi mum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p5.5 output. note: because all i/o pins on the device power up as inputs with weak internal pull-up resistors, it is possible to def ine the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this r egister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p5.4 i/o pin, which is connected to the si gnal detected output of a pbc/cru/sdu function. if this bit is set, the signal detect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
41 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.28 2bh: port bypass control 11 (pbc11) the following table shows the bit assignments for the port bypass control 11 register. this register functions the same as the port bypass control 0 re gister except it affects th e p5.7 and p5.6 pins. register name: pbc11 address: 2bh reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p5.7 and p5.6 are automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p5.7 and p5.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on t he signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p5.7 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass i nput of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass ci rcuit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p5.6 input is low, resulting in a maxi mum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p5.7 output. note: because all i/o pins on the device power up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available th rough an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p5.6 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal detec t unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
42 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.29 2ch: port bypass control 12 (pbc12) the following table shows the bit assignments for the port bypass control 12 register. this register functions the same as the port bypass control 0 re gister except it affects th e p6.1 and p6.0 pins. register name: pbc12 address: 2ch reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p6.1 and p6.0 are automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p6.1 and p6.0. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p6.1 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when the synchronized and filtered p6.0 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to t he de-assertion of the p6.1 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to define the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an i nput synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this register can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit bec omes a read-only indication of the p6.0 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal dete ct unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
43 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.30 2dh: port bypass control 13 (pbc13) the following table shows the bit assignments for the port bypass control 13 register. this register functions the same as the port bypass control 0 re gister except it affects th e p6.3 and p6.2 pins. register name: pbc13 address: 2dh reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p6.3 and p6.2 are automatically configured as an fb output pin and an sd input pin. configurati ons for these i/o pins that may have been previously enabled through other cont rol registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p6.3 and p6.2. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p6.3 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circuit is in bypass mode. this register bit is aut omatically cleared when t he synchronized and filtered p6.2 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p6.3 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to def ine the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this re gister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p6.2 i/o pin, which has been connected to the signal detected output of a pbc/ cru/sdu function. if this bit is set, the signal det ect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
44 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.31 2eh: port bypass control 14 (pbc14) the following table shows the bit assignments for the port bypass control 14 register. this register functions the same as the port bypass control 0 re gister except it affects th e p6.5 and p6.4 pins. register name: pbc14 address: 2eh reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p6.5 and p6.4 are automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p6.5 and p6.4. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p6.5 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass in put of a pbc/cru/sdu function is not enabled and the port bypass circ uit is in normal mode. when this bit is reset, the force bypass function of a pbc/cru/sdu function is enabled and the port bypass circ uit is in bypass mode. this register bit is au tomatically cleared when t he synchronized and filtered p6.4 input is low, resulting in a maximum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p6.5 output. note: because all i/o pins on the device powe r up as inputs with weak internal pull-up resistors, it is possible to defi ne the default state of the force bypass function by using an external pull-down re sistor. the default state of the i/o can be determined by reading this register, because the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this r egister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p6.4 i/o pin, which has been connected to the signal detected output of a pbc/cru/ sdu function. if this bit is set, the signal detect unit detects a high-speed signal. if this bit is reset, the signal detect unit does not detect a high-speed signal.
45 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.32 2fh: port bypass control 15 (pbc15) the following table shows the bit assignments for the port bypass control 15 register. this register functions the same as the port bypass control 0 re gister except it affects th e p6.7 and p6.6 pins. register name: pbc15 address: 2fh reset value: 00xx_xx1xb bit bit label access description 7 pbcen r/w port bypass control enable when this bit is set, p6.7 and p6.6 ar e automatically configured as an fb output pin and an sd input pin. configurations for these i/o pins that may have been previously enabled th rough other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). when this bit is reset, the remaining bits in this register have no effect on the operation of p6.7 and p6.6. 6 sdien r/w signal detected interrupt enable when this bit is set, the sd input generates an interrupt if a transition occurs on the pin. if a transition occurs, the in t# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, transitions on the signal detected input do not generate an interrupt condition. 5:2 res r reserved. 1 fb r/w force bypass this bit controls the p6.7 i/o pin, whic h is configured as a totem pole output by setting the pbcen bit. when this bit is set, the force bypass input of a pbc/cru/sdu function is not enabled and the port bypass circuit is in normal mode. when this bit is reset, the force bypas s function of a pbc/cru/sdu function is enabled and the port bypass ci rcuit is in bypass mode. this register bit is automatically cl eared when the synchronized and filtered p6.6 input is low, resulting in a maxi mum latency of 400 ns from detection of the loss of a high-speed signal to the de-assertion of the p6.7 output. note: because all i/o pins on the device po wer up as inputs with weak internal pull-up resistors, it is possible to defi ne the default state of the force bypass function by using an external pull-down resistor. the default state of the i/o can be determined by reading this register, bec ause the read value of the register bits is always available through an input synchronizer and filter. after the default state is determined, write the default value to the fb bit of this register and set the pbcen bit to ensure that the port bypass control functions are enabled correctly. additional writes to this r egister can enable or disable the force bypass functions at any time as long as the sd input remains high. 0 sd r/w signal detected when the pbcen bit is set, this bit becom es a read-only indication of the p6.6 i/o pin, which has been connected to the signal detected output of a pbc/cru/ sdu function. if this bit is set, the signal detec t unit detects a high-speed signal. if this bit is reset, the signal detec t unit does not detect a high-speed signal.
46 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.33 30h: fan speed control 0 (fsc0) the following table shows the bit assignments for the fan speed control 0 register. this register affects the p2.0 pin. register name: fsc0 address: 30h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.0 is automatic ally configured to provide a fan speed monitoring input. configurations for this i/o pin that may have been previously enabled through other control registers ar e overridden, except for the bypass select function (bits 6 and 5 of the ap propriate bit control registers). if the appropriate bypass bits are set, the odd- numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs. when this bit is reset, the remaining bits in this register have no effect on the operation of p2.0. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc0 register provides the user wi th an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to acco mmodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.0 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco0 register. if this condition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the 8-bit f an speed counter. the available fan divisor values are as follows: the decimal count value can be calc ulated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failu re count value does not exceed the limits of an 8-bit counter. typical appl ications can consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
47 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.34 31h: fan speed coun t overflow 0 (fsco0) the following table shows the bit assignments for the fan speed count overflow 0 register. this register affects the p2.0 pin. 3.2.35 32h: fan speed cu rrent count 0 (fscc0) the following table shows the bit assignments for the fan speed current count 0 register. this register affects the p2.0 pin. register name: fsco0 address: 31h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in th e fsc0 register to avoid generating unintentional interrupts. the overflow count value can be dete rmined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monitori ng logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc0 address: 32h reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc0 register, provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is re quired to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this regist er is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with the fsien bit reset in the fsc0 register, this register is automatically updat ed with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc0 register, this register is automatic ally updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also clea red, indicating that a valid rpm value is in the process of being generated.
48 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.36 34h: fan speed control 1 (fsc1) the following table shows the bit assignments for the fan speed control 1 register. this register functions same the fan speed control 0 register except it affects the p2.1 pin. register name: fsc1 address: 34h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.1 is automatic ally configured to provide a fan speed monitoring input. configurations for this i/o pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, the odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.1. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow the user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc1 register provides the user wi th an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditi oned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit t he signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.1 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco1 register. if this condition occu rs, the int# pin asserts and a binary value equal to the address of this regi ster appears in the bcis register. when this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor va lue used to determine the correct range of rpm values supplied to the 8-bit f an speed counter. the available fan divisor values are as follows: the decimal count value can be ca lculated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the ma ximum non-failure count value does not exceed the limits of an 8-bit counter. typi cal applications may consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
49 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.37 35h: fan speed coun t overflow 1 (fsco1) the following table shows the bit assignments for the fan speed count overflow 1 register. this register functions same the fan speed count overflow 0 register except it affects the p2.1 pin. 3.2.38 36h: fan speed cu rrent count 1 (fscc1) the following table shows the bit assignments for the fan speed current count 1 register. this register functions same the fan speed current count 0 register except it affects the p2.1 pin. register name: fsco1 address: 35h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is gener ated. this register should be loaded prior to setting the fscen bit in the fsc1 register to avoid generating unintentional interrupts. the overflow count value can be det ermined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monitoring logic can support a low-end nominal rpm of 850. high-end rpm values are ba sically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc1 address: 36h reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc1 register, provide the user with an accurate bi nary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with the fsien bit reset in the fsc1 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc1 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also cleared, indicating that a valid rpm value is in the process of being generated.
50 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.39 38h: fan speed control 2 (fsc2) the following table shows the bit assignments for the fan speed control 2 register. this register functions same the fan speed control 0 register except it affects the p2.2 pin. register name: fsc2 address: 38h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.2 is automatically configur ed to provide a fan speed monitoring input. configurations for this i/o pin that may have been previously enabled through other control registers ar e overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, th e odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.2. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc2 register provides the user with an accurate binary fan speed count value that can be used to determine the cu rrent rpm value of the fan. incoming pulses are filtered and conditioned to acco mmodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.2 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco2 register. if this condition occurs , the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor va lue used to determine the correct range of rpm values supplied to the 8-bit f an speed counter. the available fan divisor values are as follows: the decimal count value can be calc ulated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. typical applications may consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
51 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.40 39h: fan speed coun t overflow 2 (fsco2) the following table shows the bit assignments for the fan speed count overflow 2 register. this register functions same the fan speed count overflow 0 register except it affects the p2.2 pin. 3.2.41 3ah: fan speed cu rrent count 2 (fscc2) the following table shows the bit assignments for the fan speed current count 2 register. this register functions same the fan speed current count 0 register except it affects the p2.2 pin. register name: fsco2 address: 39h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in the fsc2 register to avoid generating unintentional interrupts. the overflow count value can be dete rmined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monito ring logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc2 address: 3ah reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc2 register, provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this regist er is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with t he fsien bit reset in the fsc2 register, this register is automatically updat ed with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc2 register, this register is automatic ally updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. once the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also clear ed, indicating that a valid rpm value is in the process of being generated.
52 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.42 3ch: fan speed control 3 (fsc3) the following table shows the bit assignments for the fan speed control 3 register. this register functions same the fan speed control 0 register except it affects the p2.3 pin. register name: fsc3 address: 3ch reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.3 is automa tically configured to provide a fan speed monitoring input. configurations for th is i/o pin that ma y have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, the odd-numbered fan speed input pins ( p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.3. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc3 register provides the user wi th an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times that are typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.3 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco3 register. if this condition occu rs, the int# pin asserts and a binary value equal to the address of this regi ster appears in the bcis register. when this bit is reset, the fan s peed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor va lue used to determine the correct range of rpm values supplied to the 8-bit fan speed counter. the available fan divisor values are as follows: the decimal count value can be calculated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. ty pical applications ma y consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
53 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.43 3dh: fan speed count overflow 3 (fsco3) the following table shows the bit assignments for the fan speed count overflow 3 register. this register functions same the fan speed count overflow 0 register except it affects the p2.3 pin. 3.2.44 3eh: fan speed cu rrent count 3 (fscc3) the following table shows the bit assignments for the fan speed current count 3 register. this register functions same the fan speed current count 0 register except it affects the p2.3 pin. register name: fsco3 address: 3dh reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in the fsc3 register to avoid generating unintentional interrupts. the overflow count value can be dete rmined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monitoring logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc3 address: 3eh reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc3 register provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this register is 00h, an accurate fan speed count value has not been generated indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with the fsien bit reset in the fsc3 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc3 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also cleared, indicating that a valid rpm value is in the process of being generated.
54 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.45 40h: fan speed control 4 (fsc4) the following table shows the bit assignments for the fan speed control 4 register. this register functions same the fan speed control 0 register except it affects the p2.4 pin. register name: fsc4 address: 40h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.4 is automatically configured to provide a fan speed monitoring input. configurations for th is i/o pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, t he odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.4. when enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc4 register provides the user wi th an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to ac commodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.4 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco4 register. if this condition occu rs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, the fan s peed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor va lue used to determine the correct range of rpm values supplied to the 8-bit fan speed counter. the available fan divisor values are as follows: the decimal count value can be calc ulated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in th e above equation with the appropriate divisor as long as the ma ximum non-failure count value does not exceed the limits of an 8-bit counter. typical appl ications may consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
55 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.46 41h: fan speed coun t overflow 4 (fsco4) the following table shows the bit assignments for the fan speed count overflow 4 register. this register functions same the fan speed count overflow 0 register except it affects the p2.4 pin. 3.2.47 42h: fan speed cu rrent count 4 (fscc4) the following table shows the bit assignments for the fan speed current count 4 register. this register functions the same as fan speed current count 0 register except it affects the p2.4 pin. register name: fsco4 address: 41h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in the fsc4 register to avoid generati ng unintentional interrupts. the overflow count value can be dete rmined using the following equation, where ff% is equal to the percentage of nominal rpm, which constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monito ring logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc4 address: 42h reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc4 register, provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this regi ster is 00h, an accurate fan speed count value is not generated, indicating that t he fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with the fsien bit reset in the fsc4 register, this register is automatically updat ed with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc4 register, this register is automati cally updated with an accurate fan speed count, once per revolution of the fan, un til an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also cleared, indicating that a valid rpm value is in the process of being generated.
56 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.48 44h: fan speed control 5 (fsc5) the following table shows the bit assignments for the fan speed control 5 register. this register functions same the fan speed control 0 register , except it affects the p2.5 pin. register name: fsc5 address: 44h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.5 is automatically configured to provide a fan speed monitoring input. configurations for th is i/o pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, the odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.5. when enabled as a fan speed monitoring input, pulses from the fan tachometer output gate an internal 20 khz clock in to an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allo w the user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc5 register provides the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and condi tioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.5 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco5 register. if this condition occu rs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, the fan s peed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor value used to determine the correct range of rpm values supplied to the 8-bit f an speed counter. the available fan divisor values are as follows: the decimal count value can be calc ulated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. ty pical applications ma y consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
57 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.49 45h: fan speed coun t overflow 5 (fsco5) the following table shows the bit assignments for the fan speed count overflow 5 register. this register functions same the fan speed count overflow 0 register except it affects the p2.5 pin. 3.2.50 46h: fan speed cu rrent count 5 (fscc5) the following table shows the bit assignments for the fan speed current count 5 register. this register functions the same as fan speed current count 0 register except it affects the p2.5 pin. register name: fsco5 address: 45h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in t he fsc5 register to avoid generating unintentional interrupts. the overflow count value can be deter mined using the following equation, where ff% is equal to the percentage of nominal rpm, which constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monitori ng logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc5 address: 46h reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc5 register, provide the user with an accurate bi nary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000)/(decimal count value divisor) when the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or there are no tachometer pulses present. when operating in a polled mode, with the fsien bit reset in the fsc5 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc5 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan until an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also be cleared, indicating that a valid rpm value is in the process of being generated.
58 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.51 48h: fan speed control 6 (fsc6) the following table shows the bit assignments for the fan speed control 6 register. this register functions same the fan speed control 0 register except it affects the p2.6 pin. register name: fsc6 address: 48h reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.6 is automatic ally configured to provide a fan speed monitoring input. configurations for this i/o pin that may have been previously enabled through other control registers ar e overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, t he odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.6. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc6 register provides the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to acco mmodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.6 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco6 register. if this condition occurs , the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. when this bit is reset, the fan speed monitoring logic will not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor va lue used to determine the correct range of rpm values supplied to the 8-bit f an speed counter. the available fan divisor values are as follows: the decimal count value can be calc ulated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. ty pical applications ma y consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
59 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.52 49h: fan speed coun t overflow 6 (fsco6) the following table shows the bit assignments for the fan speed count overflow 6 register. this register functions same the fan speed count overflow 0 register except it affects the p2.6 pin. 3.2.53 4ah: fan speed cu rrent count 6 (fscc6) the following table shows the bit assignments for the fan speed current count 6 register. this register functions the same as fan speed current count 0 register except it affects the p2.6 pin. register name: fsco6 address: 49h reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in t he fsc6 register to avoid generating unintentional interrupts. the overflow count value can be deter mined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monitori ng logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc6 address: 4ah reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc6 register, provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is required to generate an accurate fan speed count value. the following equation can be used to determine the current rpm value of the fan: rpm = (1,200,000) /( decimal count value divisor) when the result of a read of this regi ster is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or no tachometer pulses are present. when operating in a polled mode, with the fsien bit reset in the fsc6 register, this register is automati cally updated with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc6 register, this register is automati cally updated with an accurate fan speed count, once per revolution of the fan, un til an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also cleared, indicating that a valid rpm value is in the process of being generated.
60 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.54 4ch: fan speed control 7 (fsc7) the following table shows the bit assignments for the fan speed control 7 register. this register functions same the fan speed control 0 register except it affects the p2.7 pin. register name: fsc7 address: 4ch reset value: 00xx_xx00b bit bit label access description 7 fscen r/w fan speed control enable when this bit is set, p2.7 is automatic ally configured to provide a fan speed monitoring input. configurations for this i/o pin that may have been previously enabled through other control registers are overridden, except for the bypass select function (bits 6 and 5 of the appropriate bit control registers). if the appropriate bypass bits are set, the odd-numbered fan speed input pins (p2.1, p2.3, p2.5, or p2.7) are configured as outputs . when this bit is reset, the remaining bits in this register have no effect on the operation of p2.7. when enabled as a fan speed monitoring i nput, pulses from the fan tachometer output gate an internal 20 khz clock into an 8-bit counter. a divisor value stored in bits 1 and 0 of this register allow t he user to select one of four nominal rpm values based on fan tachometer outputs, which pulse twice per revolution. the fscc7 register provides the user wi th an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. incoming pulses are filtered and conditioned to accommodate the slow rise and fall times typical of fan tachometer outputs. the maximum input signal is limited to a range of v ss to v dd . if this input is supplied from a fan tachometer output that exceeds this range, external components are required to limit the signal to an acceptable range. 6 fsien r/w fan speed interrupt enable when this bit is set, the p2.7 input generates an interrupt if the 8-bit counter value is greater than or equal to the count overflow value loaded into the fsco7 register. if this condition occu rs, the int# pin asserts and a binary value equal to the address of this regist er appears in the bcis register. when this bit is reset, the fan speed monitoring logic does not generate an interrupt condition. 5:2 res r reserved. 1:0 fd1-0 r/w fan divisor these two bits determine the divisor val ue used to determine the correct range of rpm values supplied to the 8-bit fan speed counter. the available fan divisor values are as follows: the decimal count value can be calculated using the following equation: decimal count value = (1,200,000) / (rpm divisor) any nominal rpm value can be used in the above equation with the appropriate divisor as long as the maximum non-failure count value does not exceed the limits of an 8-bit counter. ty pical applications may consider 60% to 70% of nominal rpm a fan failure, which would result in a decimal count value of 250 (fah) and 214 (d6h), respectively, at the above stated rpm values. fd1 fd0 divisor nominal rpm decimal count value 0 0 1 8000 150 (96h) 0 1 2 4000 150 (96h) 1 0 4 2000 150 (96h) 1 1 8 1000 150 (96h)
61 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.55 4dh: fan speed count overflow 7 (fsco7) the following table shows the bit assignments for the fan speed count overflow 7 register. this register functions same the fan speed count overflow 0 register except it affects the p2.7 pin. 3.2.56 4eh: fan speed cu rrent count 7 (fscc7) the following table shows the bit assignments for the fan speed current count 7 register. this register functions the same as fan speed current count 0 except it affects the p2.7 pin. register name: fsco7 address: 4dh reset value: 0000_0000b bit bit label access description 7:0 fsco7-0 r/w fan speed count overflow these eight bits are compared to the 8-bit fan speed counter. if the counter exceeds this value, an interrupt is generated. this register should be loaded prior to setting the fscen bit in the fsc7 register to avoid generating unintentional interrupts. the overflow count value can be deter mined using the following equation, where ff% is equal to the percentage of nominal rpm that constitutes a fan failure: decimal overflow count value = (1,200,000) / (rpm divisor ff%) based on the above equation, a divisor of 8, and a detected fan failure at 70% of nominal rpm, the fan speed monito ring logic can support a low-end nominal rpm of 850. high-end rpm values are bas ically unlimited; however, counter resolution is diminished above 8000 rpm. register name: fscc7 address: 4eh reset value: 0000_0000b bit bit label access description 7:0 fscc7-0 r these eight bits, when enabled by setting the fscen bit in the fsc7 register, provide the user with an accurate binary fan speed count value that can be used to determine the current rpm value of the fan. a minimum of one complete revolution of the fan is requi red to generate an accurate fan speed count value. the following equation c an be used to determine the current rpm value of the fan: rpm = (1,200,000) / (decimal count value divisor) when the result of a read of this register is 00h, an accurate fan speed count value is not generated, indicating that the fan has not completed a minimum of one revolution. when the result of a read of this register is ffh, the fan is rotating very slowly or no tachometer pulses are present. when operating in a polled mode, with the fsien bit reset in the fsc7 register, this register is automatically updated with an accurate fan speed count once per revolution of the fan. when operating in an interrupt mode with the fsien bit set in the fsc7 register, this register is automatically updated with an accurate fan speed count, once per revolution of the fan, until an interrupt is generated. after the interrupt is generated, the value remains stable until the interrupt is cleared. when the interrupt is cleared, this register is also cleared, indicating that a valid rpm value is in the process of being generated.
62 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.57 70h: pulse trai n control 00 (ptc00) this register, along with the ptc01 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc00 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc01 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc00 register with a 45h and the ptc01 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc01 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 00 register. register name: ptc00 address: 70h reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the fi rst bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
63 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.58 71h: pulse trai n control 01 (ptc01) this register, along with the ptc00 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc00 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc01 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc00 register with a 45h and the ptc01 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc00 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 01 register. register name: ptc01 address: 71h reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse-train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 41.67 ms 0 1 55.55 ms 1 0 83.33 ms 1 1 125 ms ptl1 ptl0 pulse-train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
64 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.59 72h: pulse trai n control 10 (ptc10) this register, along with the ptc11 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc10 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc11 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc10 register with a 45h and the ptc11 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc11 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 10 register. register name: ptc10 address: 72h reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the fi rst bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time 0: defines led off time.
65 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.60 73h: pulse trai n control 11 (ptc11) this register, along with the ptc10 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc10 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc11 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc10 register with a 45h and the ptc11 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc10 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111.the following table shows the bit assignments for the pulse train control 11 register. register name: ptc11 address: 73h reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 41.67 ms 0 1 55.55 ms 1 0 83.33 ms 1 1 125 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
66 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.61 74h: pulse trai n control 20 (ptc20) this register, along with the ptc21 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc20 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc21 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc20 register with a 45h and the ptc21 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc21 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 20 register. register name: ptc20 address: 74h reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time 0: defines led off time.
67 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.62 75h: pulse trai n control 21 (ptc21) this register, along with the ptc20 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc20 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc21 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc20 register with a 45h and the ptc21 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc20 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 21 register. register name: ptc21 address: 75h reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 41.67 ms 0 1 55.55 ms 1 0 83.33 ms 1 1 125 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
68 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.63 76h: pulse trai n control 30 (ptc30) this register, along with the ptc31 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc30 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc31 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc30 register with a 45h and the ptc31 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc31 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 30 register. register name: ptc30 address: 76h reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
69 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.64 77h: pulse trai n control 31 (ptc31) this register, along with the ptc30 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc30 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc31 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc30 register with a 45h and the ptc31 register with a c1h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 125 ms. if the default values of this register or the ptc30 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 31 register. register name: ptc31 address: 77h reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits.the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 41.67 ms 0 1 55.55 ms 1 0 83.33 ms 1 1 125 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
70 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.65 78h: pulse trai n control 40 (ptc40) this register, along with the ptc41 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train leng th and the on/off time to derive a specific visual indication. the ptc40 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc41 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc40 register with a 45h and the ptc41 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc41 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 40 register. register name: ptc40 address: 78h reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
71 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.66 79h: pulse trai n control 41 (ptc41) this register, along with the ptc40 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc40 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc41 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc40 register with a 45h and the ptc41 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc40 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 41 register. register name: ptc41 address: 79h reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 41.67 ms 0 1 55.55 ms 1 0 83.33 ms 1 1 125 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
72 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.67 7ah: pulse trai n control 50 (ptc50) this register, along with the ptc51 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc50 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc51 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc50 register with a 45h and the ptc51 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc51 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 50 register. register name: ptc50 address: 7ah reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
73 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.68 7bh: pulse trai n control 51 (ptc51) this register, along with the ptc50 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc50 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc51 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc50 register with a 45h and the ptc51 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc50 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 51 register.) register name: ptc51 address: 7bh reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0041.67ms 0155.55ms 1083.33ms 11125ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
74 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.69 7ch: pulse trai n control 60 (ptc60) this register, along with the ptc61 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train leng th and the on/off time to derive a specific visual indication. the ptc60 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc61 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc60 register with a 45h and the ptc61 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc61 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 60 register. register name: ptc60 address: 7ch reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shifted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
75 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.70 7dh: pulse trai n control 61 (ptc61) this register, along with the ptc60 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train leng th and the on/off time to derive a specific visual indication. the ptc60 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc61 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc60 register with a 45h and the ptc61 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc60 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 61 register. register name: ptc61 address: 7dh reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0041.67ms 0155.55ms 1083.33ms 11125ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
76 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.71 7eh: pulse trai n control 70 (ptc70) this register, along with the ptc71 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc70 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc71 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc70 register with a 45h and the ptc71 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc71 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 71 register. register name: ptc70 address: 7eh reset value: 0000_0000b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time.
77 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.72 7fh: pulse trai n control 71 (ptc71) this register, along with the ptc70 register, provides a user-programma ble led flashing pulse train. the user can adjust the pulse duration, the pulse train le ngth, and the on/off time to derive a specific visual indication. the ptc70 register provides eight of the tw elve bits available in th e programmable pulse train. the ptc71 register contains two bits of pulse-widt h programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc70 register with a 45h and the ptc71 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc70 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 71 register. register name: ptc71 address: 7fh reset value: 0000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shifted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0041.67ms 0155.55ms 1083.33ms 11125ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
78 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.73 80h-87h: bit contro l port 0 (bcp00-bcp07) these eight registers provide individu al bit control for the port 0 i/o pi ns. all register bits are identical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, wi th parallel read and write paths. the following table shows the bit assignments for the bit control port 0 registers. register name: bcp00-bcp07 address: 80h - 87h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs (function se lect) bits, enables one of eight pulse train circuits controlled by the pulse train registers ptc00 through ptc71 (70h through 7fh) as the output drive function for this i/o pin. when this bit is set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circ uits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass function of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits c auses the i/o pin to be configured as an output that reflects the input state of the corresponding ev en-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these tw o register bits only appear in the odd-numbered bit control registers bc p07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when th e bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appropriate registers or through the use of the fs, dd, and gpd bits. the pwm function (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabled for each i/o pin at any time. if a mode change is desired, first disable t he existing mode, then enable the new mode.
79 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mechanism for flashing leds. the dd and gpd bits can be used to drive each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to configur e the i/o as an output. asserting the dd bit tri-states the i/o and effectively conf igures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user-programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull- down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using the flashing mec hanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that gener ates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurr ed. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that occurs as a result of the data direction change, which may rely on the weak inte rnal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input wi th weak pull-up. 0 gpd r/w general-purpose data when the i/o pin has been enabled as an out put, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading this register bit represents the current voltage applied to the pin. at no ti me does this bit directly represent the value latched into the data register. if the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binar y 1. after a reset or power on, this register bit is set to a binary 1, however, the value returned from a register read is the level applied to the pin sinc e each pin is an input by default. bit bit label access description
80 of 134 vsc056 data sheet revision 4.1 january 2008 table 4 shows the available output drive combinations. table 5 shows the available combinations that can be used to drive an led. table 4. bypass driving modes byp0 byp1 bypass driving mode 0 0 normal gpio operation, control is defined by the fs2-0, dd, and gpd bits 0 1 open-drain drive, active driver to v ss only 1 0 open-drain source, active driver to v dd only 1 1 totem pole drive, active driver to v ss and v dd table 5. led options pte fs2 fs1 fs0 dd gpd i/o state 00001xi nput with weak internal pull-up resistor, default state 000000output driven low to v ss 000100output t oggling at 0.25 hz, drive to v ss only 001000output t oggling at 0.33 hz, drive to v ss only 001100output t oggling at 0.50 hz, drive to v ss only 010000output t oggling at 1.00 hz, drive to v ss only 010100output t oggling at 2.00 hz, drive to v ss only 011000output t oggling at 3.08 hz, drive to v ss only 011100output t oggling at 4.00 hz, drive to v ss only 100000pulse train 0 selected, drive to v ss only 100100pulse train 1 selected, drive to v ss only 101000pulse train 2 selected, drive to v ss only 101100pulse train 3 selected, drive to v ss only 110000pulse train 4 selected, drive to v ss only 110100pulse train 5 selected, drive to v ss only 111000pulse train 6 selected, drive to v ss only 111100pulse train 7 selected, drive to v ss only 000001output driven high to v dd 000101output t oggling at 0.25 hz, drive to v dd only 001001output t oggling at 0.33 hz, drive to v dd only 001101output t oggling at 0.50 hz, drive to v dd only 010001output t oggling at 1.00 h, drive to v dd only 010101output t oggling at 2.00 hz, drive to v dd only 011001output t oggling at 3.08 hz, drive to v dd only 011101output t oggling at 4.00 hz, drive to v dd only 100001pulse train 0 selected, drive to v dd only 100101pulse train 1 selected, drive to v dd only 101001pulse train 2 selected, drive to v dd only 101101pulse train 3 selected, drive to v dd only 110001pulse train 4 selected, drive to v dd only 110101pulse train 5 selected, drive to v dd only
81 of 134 vsc056 data sheet revision 4.1 january 2008 table 6 shows the available in put edge combinations. 3.2.74 88h: pulse trai n control 80 (ptc80) this register, along with the ptc81 register, provid es a user-programmable led flashing pulse train that defines the 0.33 hz flash rate (selectab le in the bit control registers) at power on. the user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific vi sual indication. the ptc80 register provides eight of the twel ve bits available in the programmable pulse train. the ptc81 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc80 register with a 45h and the ptc81 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc51 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 80 register. 111001pulse train 6 selected, drive to v dd only 111101pulse train 7 selected, drive to v dd only table 6. input edge combinations fs2 fs1 fs0 dd gpd interrupt condition 0001xn o i n t e r r u p t generated, default x 0 1 1 x interrupt generated on a rising edge x 1 0 1 x interrupt generated on a falling edge x 1 1 1 x interrupt generated on either edge 1001xn o i n t e r r u p t generated register name: ptc80 address: 88h reset value: 0011_1111b bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the 0.33 hz (fs2-fs0 = 010b in the selected bit control register) flash rate. 1: defines led on time. 0: defines led off time. table 5. led options (continued) pte fs2 fs1 fs0 dd gpd i/o state
82 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.75 89h: pulse trai n control 81 (ptc81) this register, along with the ptc80 register, provid es a user-programmable led flashing pulse train that defines the 0.33 hz flash rate (selectab le in the bit control registers) at power on. the user can adjust the pulse duration, pulse train length, and the on/off time to derive a specific visual indication. the ptc80 register provides eight of the twel ve bits available in the programmable pulse train. the ptc81 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc80 register with a 45h and the ptc81 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc80 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 81 register. register name: ptc81 address: 89h reset value: 0100_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train lengt h, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are as follows: 3:0 pt11-8 r/w pulse train these four bits are the last bits shi fted out from 0 to 3 and define the on/off time for the flash rate. 1: defines led on time. 0: defines led off time. tpw1 tpw0 train pulse width 0 0 166.67 ms 0 1 250.0 ms 1 0 333.3 ms 1 1 500.0 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
83 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.76 8ch: pulse trai n control 90 (ptc90) this register, along with the ptc91 register, provid es a user-programmable led flashing pulse train that defines the 0.25 hz flash rate (selectab le in the bit control registers) at power on. the user can adjust the pulse duration, pulse train length, and the on/off time to derive a specific visual indication. the ptc90 register provides eight of the twel ve bits available in the programmable pulse train. the ptc91 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc90 register with a 45h and the ptc91 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc91 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 90 registers. register name: ptc90 address: 8ch reset value: 0011_1111b description pulse train control 90 bit bit label access description 7:0 pt7-0 r/w pulse train these eight bits are the first bits shi fted out from 0 to 7 and define the on/off time for the 0.25 hz (fs2-fs0 = 001b in the selected bit control register) flash rate. 1: defines led on time. 0: defines led off time.
84 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.77 8dh: pulse trai n control 91 (ptc91) this register, along with the ptc90 register, provid es a user-programmable led flashing pulse train that defines the 0.25 hz flash rate (selectab le in the bit control registers) at power on. the user can adjust the pulse duration, the pulse train length, and the on/off time to derive a specific vi sual indication. the ptc90 register provides eight of the twel ve bits available in the programmable pulse train. the ptc91 register contains two bits of pulse-width programmability, two bits of pulse train length programmability, and the remaining four bits of the programmable pulse train. as an example, the pulse train can be used to develop a visual heartbeat in dication by programming the ptc90 register with a 45h and the ptc91 register wi th a 01h. this combination develops a pulse train with two blinks followed by a gap with the on times of the led equal to 166.67 ms. if the default values of this register or the ptc90 register are modified, and synchronization to other led flash rates is desired, the sync# pin must be enabled. to enable the sync# pin, tie the syncen pin to v dd , connect an external 10 k pull-up resistor to the sync# pin, and place the proper synchronization value in bits 3:0 of the clock select control register. for information on the clock select control register, see ?fdh: clock select control (csc),? page 111. the following table shows the bit assignments for the pulse train control 91 registers. register name: ptc91 address: 8bh reset value: 1000_0000b bit bit label access description 7:6 tpw1-0 r/w train pulse width these two bits define the pulse width of each of the pulse train bits. the available pulse widths are as follows: 5:4 ptl1-0 r/w pulse train length these two bits define the pulse train leng th, which is the number of pulse train bits that is shifted out before returning to bit 0. the available pulse train lengths are given below. 3:0 pt11-8 r/w pulse train these four bits are the last bits shifte d out from 0 to 3 and define the on/off time for the flash rate. 1: defines an led on time. 0: defines an led off time. tpw1 tpw0 train pulse width 0 0 166.67 ms 0 1 250.0 ms 1 0 333.3 ms 1 1 500.0 ms ptl1 ptl0 pulse train length 0 0 12 pulse train bits from 0 to 11 0 1 10 pulse train bits from 0 to 9 1 0 9 pulse train bits from 0 to 8 1 1 8 pulse train bits from 0 to 7
85 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.78 90h-97h: bit contro l port 1 (bcp10-bcp17) these eight registers function the same as the bit control port 0 register except they provide individual bit control for the port 1 i/o pins. all register bits are id entical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bi ts are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 1 registers. register name: bcp10-bcp17 address: 90h-97h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enable s one of eight pulse train circuits controlled by the pulse train regist ers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when this bit is set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass function of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits c auses the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configur ed as an output that follows the signal applied to the p0.0 input. these two register bits only appear in the odd-numbered bit control registers bcp07, bcp05, bcp03, and bcp01. for available output drive combinations, see table 4, page 80. note: these bits are only used when the bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appropriate registers or through the use of the fs, dd, and gpd bits. the pwm function (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enab led for each i/o pin at any time. if a mode change is desired, first disable the existing mode and then enable the new mode.
86 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providi ng a simple mechanism for flashing leds. the dd and gpd bits can be used to drive each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to configure the i/o as an output. asserting the dd bit tri-states the i/o an d effectively configures the i/o as an input. the six bits allow the user to se lect one of seven flash rates or eight user-programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration w hen using the flashing mechanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that generat es an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurred. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that oc curs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individual ly configured as a true bi directional function. to implement an open-drain or open-source f unction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. 0 gpd r/w general-purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. at no time does this bit directly represent the value latched into the data register. if the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds th e pin at a binary 1. after a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is t he level applied to the pin since each pin is an input by default. bit bit label access description
87 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.79 98h-9fh: pulse-wi dth modulation control (pwmc0-pwmc7) these eight registers provide a pulse-width modulated output that can optionally be made available on each of the port 1 i/o pins. configurations for these i/o pins that may have been previously enabled through other control registers are overridden if either one or both of the pwbf bits are set. the pwbf bits have higher priority control over the port 1 i/o pins than any other mode of operation. the pulse-width modulated outputs are based on a 32-step counter and provide values from a 3.125% to a 100% duty cycle in 3.125% increments . the following table shows the bit assignments for the pulse-width modulation control registers. the following table shows the available percentages of high time for the pulse width for the pwp4-0 bits. register name: pwmc0-pwmc7 address: 98h-9fh reset value: x000_0000b bit bit label access description 6:5 pwbf1-0 r/w pulse-width base frequency these two bits determine the base operating frequency of the pulse-width modulated output. these frequencies vary with the input clock rate and are nominally based on a 10.0 mhz clock s ource. the available base frequencies are as follows. 4:0 pwp4-0 r/w pulse-width percentage these five bits determine the percentage of high time that the output pulse contains. there are 32 steps that can be adjusted in 3.125% increments. for the available percentages of high time, see table 7, page 87. table 7. pulse-width percentages pwp4 pwp3 pwp2 pwp1 pwp0 pulse-width percentage 0 0 0 0 0 3.125% on/high time 0 0 0 0 1 6.25% on/high time 0 0 0 1 0 9.375% on/high time 0 0 0 1 1 12.5% on/high time 0 0 1 0 0 15.625% on/high time 0 0 1 0 1 18.75% on/high time 0 0 1 1 0 21.875% on/high time 0 0 1 1 1 25.0% on/high time 0 1 0 0 0 28.125% on/high time 0 1 0 0 1 31.25% on/high time 0 1 0 1 0 34.375% on/high time 0 1 0 1 1 37.5% on/high time 0 1 1 0 0 40.625% on/high time pwbf1 pwbf0 pulse-width base frequency 0 0 normal operation?contr ol is provided through gpd1/ddp1 or bcp1 0 1 26 khz base frequency 1 0 52 khz base frequency 1 1 104 khz base frequency
88 of 134 vsc056 data sheet revision 4.1 january 2008 0 1 1 0 1 43.75% on/high time 0 1 1 1 0 46.875% on/high time 0 1 1 1 1 50.0% on/high time 1 0 0 0 0 53.125% on/high time 1 0 0 0 1 56.25% on/high time 1 0 0 1 0 59.375% on/high time 1 0 0 1 1 62.5% on/high time 1 0 1 0 0 65.625% on/high time 1 0 1 0 1 68.75% on/high time 1 0 1 1 0 71.875% on/high time 1 0 1 1 1 75.0% on/high time 1 1 0 0 0 78.125% on/high time 1 1 0 0 1 81.25% on/high time 1 1 0 1 0 84.375% on/high time 1 1 0 1 1 87.5% on/high time 1 1 1 0 0 90.625% on/high time 1 1 1 0 1 93.75% on/high time 1 1 1 1 0 96.875% on/high time 1 1 1 1 1 100% on/high time table 7. pulse-width percentages (continued) pwp4 pwp3 pwp2 pwp1 pwp0 pulse-width percentage
89 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.80 a0h-a7h: bit cont rol port 2 (bcp20-bcp27) these eight registers function the same as the bit control port 0 registers except they provide individual bit control for the port 2 i/o pins. all register bits are id entical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bi ts are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 2 registers. register name: bcp20-bcp27 address: a0h-a7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enables one of eight pulse train circuits controlled by the pulse train registers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when the pte bit set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass function of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either one or both of these bits causes the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these tw o register bits only appear in the odd-numbered bit control registers bc p07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when th e bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appropriate registers or through the use of the fs, dd, and gpd bits. the pwm functi on (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabled for each i/o pin at any time. if a mode change is desired, first disable t he existing mode, then enable the new mode.
90 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mechanism for flashing leds. the dd and gpd bits can be used to driv e each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to co nfigure the i/o as an output. asserting the dd bit tri-states the i/o and effectiv ely configures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user- programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using t he flashing mechanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that gener ates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurr ed. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input wi th weak pull-up. 0 gpd r/w general-purpose data when the i/o pin is enabled as an output, writing this bit determines the data value, which is present on the corresponding i/o pin. if the i/o pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. at no time does this bit directly represent the value latched into the data register. if the pin is enabled as an input and ther e is no signal applied, a weak internal pull-up resistor holds the pin at a binar y 1. after a reset or power on, this register bit is set to a binary 1; howeve r, the value returned from a register read is the level applied to the pin sinc e each pin is an input by default. bit bit label access description
91 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.81 b0h-b7h: bit cont rol port 3 (bcp30-bcp37) these eight registers function the same as the bit control port 0 registers except they provide individual bit control for the port 3 i/o pins. all register bits are id entical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bi ts are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. additionally, the control of the individual i/o pins assigned to these registers can be overridden by the pbc0, pbc1, pbc2, and pbc3 registers when port bypass control is required. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 3 registers. register name: bcp30-bcp37 address: b0h-b7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enable s one of eight pulse train circuits controlled by the pulse train regist ers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when this bit is set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass f unction of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits caus es the i/o pin to be configured as an output that reflects the input stat e of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these two register bits only appear in the odd-numbered bit control registers bcp0 7, bcp05, bcp03, and bcp01. for the available output drive combinations, see ta b l e 4 , page 80. note: these bits are only used when t he bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appropriate registers or through the use of the fs, dd, and gpd bits. the pwm function (port 0 only) and bypass function are the highest priority controls for t he appropriate i/o pin. the next highest priorities are the pbc function (p ort 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enab led for each i/o pin at any time. if a mode change is desired, fi rst disable the existing mode, then enable the new mode.
92 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mechanism for flashing leds. the dd and gpd bits can be used to driv e each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to c onfigure the i/o as an output. asserting the dd bit tri-states the i/o and effectiv ely configures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user- programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using the flashing mechanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that generates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurred. if a valid transition occurs, the int# pin asserts and a binary value equal to t he address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that oc curs as a result of the data direction change, which may rely on the weak in ternal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually confi gured as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input wi th weak pull-up. 0 gpd r/w general-purpose data when the i/o pin is enabled as an output, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin is enabled as an input, readi ng this register bit represents the current voltage applied to the pin. at no ti me does this bit directly represent the value latched into the data register. if the pin is enabled as an input and ther e is no signal applied, a weak internal pull-up resistor holds the pin at a binar y 1. after a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin si nce each pin is an input by default. bit bit label access description
93 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.82 c0h-c7h: bit cont rol port 4 (bcp40-bcp47) these eight registers function the same as the bit control port 0 registers except they provide individual bit control for the port 4 i/o pins. all register bits are id entical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bi ts are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. additionally, the control of the individual i/o pins assigned to these registers can be overridden by the pbc4, pbc5, pbc6, and pbc7 registers when port bypass control is required. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 4 registers. register name: bcp40-bcp47 address: c0h-c7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enable s one of eight pulse train circuits controlled by the pulse train registers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when this bit is set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing ci rcuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass f unction of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits c auses the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these tw o register bits only appear in the odd-numbered bit control registers bcp07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when th e bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appr opriate registers or through the use of the fs, dd, and gpd bits. the pwm function (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc functi on (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabled for each i/o pin at any time. if a mode change is desired, first disable the existing mode, then enable the new mode.
94 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, provid ing a simple mechanism for flashing leds. the dd and gpd bits can be used to drive each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-ass erted to configure the i/o as an output. asserting the dd bit tri-states the i/o and effectively configures the i/o as an input. the six bits allow the user to se lect one of seven flash rates or eight user-programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using the flashing mechanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that gener ates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occu rred. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for av ailable input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separat e register write operations. this guarantees that any i/o transition that occu rs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually confi gured as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. 0 gpd r/w general-purpose data when the i/o pin is enabled as an outpu t, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading this register bit represents the current voltage applied to the pin. at no time does this bit directly represent the value latched into the data register. if the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. after a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is the level applied to the pin since each pin is an input by default. bit bit label access description
95 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.83 cch: general-purpose timer count 0 (gptc0) the following table shows the bit assignments for the general-purpose timer count 0 register. 3.2.84 cdh: general-purpose timer count 1 (gptc1) the following table shows the bit assignments for the general-purpose timer count 1 register. register name: gptc0 address: cch reset value: 0000_0000b bit bit label access description 7:0 tc7-0 r/w timer count these eight bits are part of the 24-b it general-purpose timer down counter initial count value. writing to this register causes the timer to update and to initiate a countdown from the new value if the timer has been enabled in the gpte register. clearing this register, along with the gptc1 and gptc2 registers, stops the down counter and disables the interrupt generation logic. after a reset or power on, these bits are cleared. register name: gptc1 address: cdh reset value: 0000_0000b bit bit label access description 7:0 tc15-8 r/w timer count these eight bits are part of the 24-b it general-purpose timer down counter initial count value. writing to this register causes the timer to update and to initiate a countdown from the new value if the timer has been enabled in the gpte register. clearing this register, along with the gptc0 and gptc2 registers, stops the down counter and disables the interrupt generation logic. after a reset or power on, these bits are cleared.
96 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.85 ceh: general-purpose timer count 2 (gptc2) the following table shows the bit assignments for the general-purpose timer count 2 register. 3.2.86 cfh: general-purpose timer enable (gpte) the following table shows the bit assignments fo r the general-purpose timer enable register. register name: gptc2 address: ceh reset value: 0000_0000b bit bit label access description 7:0 tc23-16 r/w timer count these eight bits are part of the 24- bit general-purpose timer down counter initial count value. writing to this register causes the timer to update and initiate a countdown from the new value if the timer has been enabled in the gpte register. clearing this register, along with the gptc0 and gptc1 registers, stops the down counter and disables the interrupt generation logic. after a reset or power on, these bits are cleared. register name: gpte address: cfh reset value: 0000_0000b bit bit label access description 7:1 res r reserved. 0 gpte r/w general-purpose timer enable this bit enables the general-purpose timer to down count and generate an interrupt when the timer reaches zero. the general-purpose timer down counts using a clock source that is a divide- by-three of the core clock (8.0 mhz to 12.5 mhz), resulting in a timer count resolution of 375 ns to 240 ns. when the timer initial count is set to all 1s, the maximum timeout is greater than four seconds when using a 12.5 mhz core clock. when the 24-bit timer reaches a value of zero, the interrupt output of the vsc056 is asserted. the timer then re-loads with the initial count value found in the gptc0, gptc1, and gptc2 regist ers and begins counting down again. writing a value of ffh to the bcis register clears this interrupt. after a reset or power on, this bit is cleared, disabling the timer and timer interrupt.
97 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.87 d0h-d7h: bit cont rol port 5 (bcp50-bcp57) these eight registers function the same as the eight bit control port 0 registers except that they relate to the port 5 i/o pins. in addition, the control of the individual i/o pins assigned to these registers can be overridden by the pbc8, p bc9, pbc10, and pbc11 regi sters when port bypass co ntrol is required. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 5 registers. register name: bcp50-bcp57 address: d0h-d7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enable s one of eight pulse train circuits controlled by the pulse train regist ers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when the pte bit set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass function of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits c auses the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configur ed as an output that follows the signal applied to the p0.0 input. these two register bits only appear in the odd-numbered bit control registers bcp07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when the bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the approp riate registers or through the use of the fs, dd, and gpd bits. the pwm func tion (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabled for each i/o pin at any time. if a mode change is desired, first disable the existing mode, then enable the new mode.
98 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mechanism for flashing leds. the dd and gpd bits can be used to drive each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to c onfigure the i/o as an output. asserting the dd bit tri-states the i/o and effectiv ely configures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user- programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using the flashing mechanism. for available combinations to drive an led, see ta b l e 5 , page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that generat es an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurred. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that oc curs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individual ly configured as a true bi directional function. to implement an open-drain or open-source func tion, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. 0 gpd r/w general-purpose data when the i/o pin is enabled as an output, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin has been enabled as an input, reading this register bit represents the current voltage applied to the pin. at no time does this bit directly represent the value latched into the data register. if the pin is enabled as an input and ther e is no signal applied, a weak internal pull-up resistor holds th e pin at a binary 1. after a reset or power on, this register bit is set to a binary 1; however, the value returned from a register read is th e level applied to the pin since each pin is an input by default. bit bit label access description
99 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.88 e0h-e7h: bit cont rol port 6 (bcp60-bcp67) these eight registers function the same as the eight bit control port 0 registers except that they relate to the port 6 i/o pins. in addition, the control of the individual i/o pins assigned to these registers can be overridden by the pbc12, pbc13, pbc14, and pbc15 registers when port bypass control is required. for information about the functionality of the bit control port 0 registers, see ?80h-87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 6 registers. register name: bcp60-bcp67 address: e0h-e7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enable s one of eight pulse train circuits controlled by the pulse train registers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when the pte bit is set, the fs bits se lect one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see ta b l e 5 , page 80. after a reset or power on, this bit is cleared. 6:5 byp1-0 r/w bypass select these two bits determine the bypass f unction of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits c auses the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these tw o register bits only appear in the odd-numbered bit control registers bcp 07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when th e bypass function is desired. they should not be set when normal gpio operation, pbc operation, or fan speed monitoring are selected through the appropriate registers or through the use of the fs, dd, and gpd bits. the pwm function (port 0 only) and bypass function are the highest priority controls for the appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabl ed for each i/o pin at any time. if a mode change is desired, first disable the existing mode, then enable the new mode.
100 of 134 vsc056 data sheet revision 4.1 january 2008 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mechanism for flashing leds. the dd and gpd bits can be used to drive each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to co nfigure the i/o as an output. asserting the dd bit tri-states the i/o and effectivel y configures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user- programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using t he flashing mechanism. for available combinations to drive an led, see table 5, page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that gener ates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurred. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that occu rs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source fu nction, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits ar e set to a binary 1, enabling the i/o as an input with weak pull-up. 0 gpd r/w general-purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin is enabled as an input, r eading this register bit represents the current voltage applied to the pin. at no ti me does this bit directly represent the value latched into the data register. if the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. after a reset or power on, this register bit is set to a binary 1, but the value returned from a register read is the leve l applied to the pin since, by default, each pin is an input. bit bit label access description
101 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.89 e8h: master interf ace clock divider (micd) the following seven registers comprise the master interface function. this function provides the ability to re-configure 32 of the i/o pins on a pa ir-by-pair basis as a master mode two-wire serial interface. ports 4, 5, 6, and 7 can be re-configured with four interface pairs per port. each even-numbered port pin can be configured as an sda function, with the correspon ding odd-numbered port pins configured as an scl function. the following table shows the bit assignments fo r the master interface clock divider register. the following table lists the various divider values that result in common frequencies of operation. register name: micd address: e8h reset value: 0x00_0000b bit bit label access description 7 msce r/w master interface scl clock low extend setting this bit changes the duty cycle of the master interface scl clock output from a 50% low-50% high duty cycle to a 75% low-25% high duty cycle. this allows for better matching of fast mode (400 khz) interface timings. after a reset or power on, this bit is cleared, enabling the default duty cycle. 6 res r reserved. 5:0 div5-0 r/w master interface clock divider these six bits determine the scl clock frequency of the master interface. the master interface uses a f our-cycle state machine to drive the scl output. all timings for the master interface are based on this four-cycle state machine. the frequency of operation desired is based on t he divider value along with the core clock frequency of the vsc056. for the various divider values that result in common frequencies of operation, see ta b l e 8 , page 101. table 8. master interface clock divider core clock div5-0 divider sm master interface scl clock frequency 8.0 mhz 27h 40 4 50.0 khz 10.0 mhz 31h 50 4 50.0 khz 12.5 mhz 3eh 63 4 49.6 khz 8.0 mhz 13h 20 4 100.0 khz 10.0 mhz 18h 25 4 100.0 khz 12.5 mhz 1fh 32 4 97.6 khz 8.0 mhz 04h 4 4 400.0 khz 10.0 mhz 06h 7 4 357.1 khz 12.5 mhz 07h 8 4 390.6 khz
102 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.90 e9h: master interf ace port select (mips) the following table shows the bit assignments fo r the master interface port select register. 3.2.91 eah: master in terface data (mid) the following table shows the bit assignments for the master interface data register. register name: mips address: e9h reset value: 0x00_0000b bit bit label access description 7 mipe r/w master interface port enable this bit enables the master interface on to the selected set of gpio pins based on the port select and bit select bits. setting this bit enables the interface allowing the master interface to transfer data over the selected gpio pins based on register control. clearing this bit disables the interface a nd returns control of the gpio pins to other functions within this device. after a reset or power on, this bit is cleared. 6:5 res r reserved. 4:2 ps2-0 r/w these three bits determine the port selected for master mode two-wire serial transfers. valid ports for the vsc056 include port 4 (4h), port 5 (5h), port 6 (6h), and port 7 (7h). values other than those specified do not enable the interface. after a reset or power on, these bits are cleared. 1:0 bs1-0 r/w master interface bit select these two bits determine the bits within a port selected for master mode two- wire serial transfers. 00b: enables the sda function on bit 0 a nd the scl function on bit 1 of the port. 01b: enables the sda function on bit 2 a nd the scl function on bit 3 of the port. 10b: enables the sda function on bit 4 a nd the scl function on bit 5 of the port. 11b: enables the sda function on bit 6 a nd the scl function on bit 7 of the port. after a reset or power on, these bits are cleared. register name: mid address: eah reset value: 0000_0000b bit bit label access description 7:0 md7-0 r/w master interface data these eight bits store data to be used for serial write operations or received from serial read operations. after a reset or power on, these bits are cleared.
103 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.92 ebh: master inte rface command (mic) the following table shows the bit assignments for the master interface command register. register name: mic address: ebh reset value: 1100_0000b bit bit label access description 7 sdai r serial data input this read-only bit indicates the current state of the master serial interface sda input. 1: sda signal is tri-stated and is bei ng pulled high by an external pull-up resistor. 0: device (including the vsc056) is actively driving a low value onto the sda wire. after a reset or power on, this bit is unknown. 6 sdao r/w serial data output this bit provides low-level drive contro l of the master serial interface sda signal. setting this bit allows the automatic functi ons of this master serial interface to control the sda output value. clearing this bit forces a zero value onto the serial bus, regardless of the state of the automatic controls. under normal circumstances, this bit should always be written to a 1. the read value for th is bit returns the programmed wired-and output value being driven, not the live value on the serial bus. after a reset or power on, this bit is set. 5 srst r/w soft reset setting this bit performs a soft reset oper ation. the soft reset operation clears all state machines and returns the master serial interface to an idle (non- driving) state with regard to scl and sda. the soft reset is one clock in duration. this bit is self-clearing. after a reset or power on, this bit is cleared. 4 go r/w go setting this bit initiates a byte transfer on the serial bus. this bit automatically clears itself when the transfer is complete. after a reset or power on, this bit is cleared. 3 rw r/w read/write this bit determines whether the immediat e byte to be transferred is a read or a write transaction. if this bit is set, the transfer is a read. if this bit is cleared, the transfer is a write. after a reset or power on, this bit is cleared. 2 ack r/w serial bus acknowledge this bit provides control for the ackn owledge bit of a serial byte transfer. setting this bit for a read transaction caus es the serial interface to drive the ack bit at the end of the transaction?s bit sequence. this must be used for all but the last byte of sequential read operations. reading this bit after a write transacti on has completed indicates whether or not the targeted slave device acknowledged the byte transfer. after a reset or power on, this bit is cleared.
104 of 134 vsc056 data sheet revision 4.1 january 2008 operating notes for the master serial interface encoded two-wire serial commands 52h - read byte with stop, no acknowledge (used at the end of read telegrams) 54h - read byte with acknowledge (used for middle bytes during sequential reads) 58h - write byte (used for end of address wr ites or middle bytes of sequential writes) 59h - write byte with start (used for the beginning of all telegrams and restarts) 5ah - write byte with stop (used for end of write telegrams) 60h - soft reset the sequence for normal two-wire serial protocol compliant write operations is: 1. issue start bit, send the slave device address and write bit (0) in the lsb. 2. send the slave device's register addr ess, this can zero bytes or in some slave devices this may be multiple bytes. 3. send the byte to be written to th e slave device, followed by a stop bit. pseudo-code to perform two-wire serial protocol compliant writes using this core: send slave device address: 1) <{slave_address[6:0],1'b0}> --> mid register (data) 2) write 59h to the mic register (command) 3) poll the mis register (status) until bit 0 = 1 4) test bit 1, if set continue, if clear then the slave device did not respond send register address: 5) --> mid register (data) 6) write 58h to mic register (command) 7) poll the mis register (status) until bit 0 = 1 8) test bit 1, if set continue, if clear then the slave device did not acknowledge 1 sto r/w stop condition this bit controls the stop condition of a serial transfer. setting this bit directs the master serial interface to generate a stop bit sequence (rising edge on sda while scl is high) after transferring the immediate byte. this should only be done to end a telegram. after a reset or power on, this bit is cleared. 0 sta r/w start condition this bit provides control for the start condition of a serial transfer. setting this bit directs the master serial interface to generate a start bit sequence (falling edge on sda while scl is high) prior to transferring the immediate byte. this operation should be initiated at the beginning of a telegram and as required for re starts during read transactions. after a reset or power on, this bit is cleared. bit bit label access description
105 of 134 vsc056 data sheet revision 4.1 january 2008 (repeat steps 5-8 if there are multiple register address bytes or data bytes) send data written to slave device register with a stop: 9) --> mid register (data) 10) write 5ah to the mic register (command) 11) poll the mis register until bit 0 = 1 12) test bit 1, if set continue, if clear then the slave device did not acknowledge the sequence for normal two-wire serial protocol compliant read operations is: 1) issue start bit, send the slave device address and write bit (0) in lsb 2) send the slave device's register address, this can zero bytes or in some slave devices this may be multiple bytes. 3) issue another start bit (re-start condition), send the slave device address and read bit (1) in the lsb. 4) read a byte from the slave device, or multiple bytes if the slave device supports sequential reads. 4a) for sequential reads, issue the read byte with ack command (54h) for all but the last byte. 4b) issue the read byte with stop, no ack command (52h) for the last byte. pseudo-code to perform two-wire serial protocol compliant reads using this core: send slave device address: 1) <{slave_address[6:0],1'b0}> --> mid register (data) 2) write 59h to the mic register (command) 3) poll the mis register (status) until bit 0 = 1 4) test bit 1, if set continue, if clear then the slave device did not respond send register address: 5) --> mid register (data) 6) write 58h to mic register (command) 7) poll the mis register (status) until bit 0 = 1 8) test bit 1, if set continue, if clear then the slave device did not acknowledge (repeat steps 5-8 if there are multiple register address bytes) issue re-start with slave device address and read bit: 9) <{slave_address[6:0],1'b1}> --> mid register (data) 10) write 59h to the mic register (command) 11) poll the mis register (status) until bit 0 = 1 12) test bit 1, if set continue, if clear then the slave device did not acknowledge
106 of 134 vsc056 data sheet revision 4.1 january 2008 read a byte: (if only one byte is to be read, skip to "read last byte") 13) write 54h to the mic register (command) 14) poll the mis register (status) until bit 0 = 1 15) read data is now available in the mid register (data) and in the mird register (read data) (repeat steps 13 through 15 until the next byte is the last) read last byte with a stop: 16) write 52h to the mic register (command) 17) poll the mis register (status) until bit 0 = 1 18) read data is now available in the mid register (data) and in the mird register (read data) pseudo-code to perform two-wire serial bus cleanup to return the bus to an idle state: check that sda is de-asserted. if not, pulse scl: 1) read the mic register (control) and check that bit 7=1. 2) if bit 7 in the mic register is reset, continue. if bit 7 in the mic register is set, go to step 6. 3) set bit 0 in the milc register (low level control) low, drive scl low. 4) set bit 0 in the milc register (low level control) high, release. 5) go back to step 1 and check sda again. drive a start condition followed by one bit of data and then finish with a stop condition: 6) drive sda low (start condition) by setting bit 6 low in the mic register 7) drive scl low by setting bit 0 low in the milc register. 8) release scl by setting bit 0 high in the milc register (clock out one data bit) 9) release sda (stop-condition) by setting bit 6 high in the mic register 10) begin normal two-wire serial transfers
107 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.93 ech: master interfac e low-level control (milc) the following table shows the bit assignments for the master interface low-level control register. 3.2.94 edh: master in terface status (mis) the following table shows the bit assignments for the master interface status register. register name: milc address: ech reset value: xxxx_xxx1b bit bit label access description 7:1 res r reserved. 0 sclo r/w serial clock output this bit provides low-level control of the master interface scl output. this register bit provides set or clear capability on the sc l output control register within this core. as such, writing any value to this register may interfere with automatic interface activity. during norma l core operation, this register should not be written. reading this register bit returns the scl output value that this core is currently driving on the serial bus. after a reset or power on, this bit is set (scl inactive). register name: mis address: edh reset value: xxxx_xx00b bit bit label access description 7:2 res r reserved. 1 ackr r acknowledge received this bit indicates if an acknowledge is received after a write operation. 1: an acknowledge has been received. 0: an acknowledge has not been received. after a reset or power on, this bit is cleared. 0 done r transfer complete this bit indicates when the current transfer is complete. 1: the current transfer is complete. 0: the current transfer is not complete. after a reset or power on, this bit is cleared. note : the status bits provided in this regi ster are also effectively available by reading the mic register (bit 2, ack and bit 4, go). the intention of this optional register is to provide a simp le programming model with only the required status bits included so that other bit positions do not need to be masked off to determine the result of a two-wire serial transfer operation. during master serial interface write operations, it is possible to write the mid (data) and mic (command) registers, perform a restart, read the current address (the milc register), and then poll the mis (status) register to determine if the current write operation is complete.
108 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.95 eeh: master inte rface read data (mird) this register allows a sequential read operation of the mic (command), milc (low-level control, delay to allow transfer to complete), mis (status), and mird (read data) registers by an external microcontroller to form a complete read transf er. it returns the same data as the mid (data) register . the following table shows the bit assignments for the master interface read data register. 3.2.96 f0h-f7h: bit contro l port 7 (bcp70-bcp77) these eight registers provide individu al bit control for the port 7 i/o pi ns. all register bits are identical from a control and status perspective, with the only difference being the individual i/o pin controlled and the presence of the bypass function. the data direction (bit 1) and general-purpose data (bit 0) bits are effectively the same bits found in the ddp0 and gpd0 registers, with parallel read and write paths. these eight registers function the same as the eight bit control port 0 registers except that they relate to the port 7 i/o pins. for information about the functionality of the bit control port 0 registers, see ?80h- 87h: bit control port 0 (bcp00-bcp07),? page 78. the following table shows the bit assignments for the bit control port 7 registers. register name: mird address: eeh reset value: 0000_0000b bit bit label access description 7:0 md7-0 r master interface data these eight read-only bits provide the data value received from serial read operations. after a reset or power on, these bits are cleared. register name: bcp70-bcp77 address: f0h-f7h reset value: 0000_001xb bit bit label access description 7 pte r/w pulse train enable this bit, along with the fs bits, enab les one of eight pulse train circuits controlled by the pulse train registers, ptc00 through ptc71 (70h through 7fh), as the output drive function for this i/o pin. when this bit is set, the fs bits select one of eight pulse train circuits instead of the normal fixed-rate led flashing circuits or the normal output drive mode. for the various led drive control modes, see table 5, page 80. after a reset or power on, this bit is cleared.
109 of 134 vsc056 data sheet revision 4.1 january 2008 6:5 byp1-0 r/w bypass select these two bits determine the bypass f unction of the odd-numbered i/o pins p0.7, p0.5, p0.3, and p0.1. setting either or both of these bits caus es the i/o pin to be configured as an output that reflects the input state of the corresponding even-numbered i/o pins p0.6, p0.4, p0.2, and p0.0. as an example, p0.1 can be configured as an output that follows the signal applied to the p0.0 input. these two register bits only appear in the odd-numbered bit control registers bcp 07, bcp05, bcp03, and bcp01. for the available output drive combinations, see table 4, page 80. note: these bits are only used when the by pass function is desired. they should not be set when normal gpio oper ation, pbc operation, or fan speed monitoring are selected through the appropria te registers or through the use of the fs, dd, and gpd bits. the pwm func tion (port 0 only) and bypass function are the highest priority controls for t he appropriate i/o pin. the next highest priorities are the pbc function (port 3 through port 6) and fan speed monitoring (port 1 and port 2). the lowest priorities are the bit control features found in the gpd, dd, and bcp registers. only one mode of operation should be enabl ed for each i/o pin at any time. if a mode change is desired, fi rst disable the existing mode, then enable the new mode. 4:2 fs2-0 r/w function select these three bits, along with the pte, dd, and gpd bits, determine the function of each i/o pin. when configured as an output, the fs2-0 bits determine the rate at which the high current drive i/o toggles, providing a simple mec hanism for flashing leds. the dd and gpd bits can be used to driv e each i/o individually and to take the place of the byte wide controls found in the dd and gpd registers. note that the dd bit is always de-asserted to configure the i/o as an output. asserting the dd bit tri-states the i/o and effectiv ely configures the i/o as an input. the six bits allow the user to select one of seven flash rates or eight user- programmable pulse trains, as well as to drive the led both on and off. the output can be enabled to drive in an open-source (output drives to v dd with an external pull-down resistor) or open-drain (output drives to v ss with an external pull-up) configuration when using t he flashing mechanism. for available combinations to drive an led, see ta b l e 5 , page 80. when configured as an input, the dd bit is asserted. these bits determine the type of i/o pin edge transition that gener ates an interrupt condition. transition detectors within the device filter the changes observed at the i/o pin and determine if a valid transition has occurred. if a valid transition occurs, the int# pin asserts and a binary value equal to the address of this register appears in the bcis register. for available input edge combinations, see table 6, page 81. note : when configuring an i/o pin from an output to an input with interrupt enabled, it is recommended that the data direction change and interrupt enabling be accomplished with separate register write operations. this guarantees that any i/o transition that occurs as a result of the data direction change, which may rely on the weak internal pull-up resistor, does not generate an unexpected interrupt. 1 dd r/w data direction this bit determines the direction of the data flow through the i/o pin. to enable the respective i/o pin as an input, set the appropriate bit. to enable the respective i/o pin as an output, reset the appropriate bit. each i/o pin can be individually configur ed as a true bidirectional function. to implement an open-drain or open-source function, set or reset the appropriate data bit using the data direction bit as the programmed data value. after a reset or power on, these bits are set to a binary 1, enabling the i/o as an input with weak pull-up. bit bit label access description
110 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.97 f8h: backplane controller interrupt status (bcis) the following table shows the bit assignments for th e backplane controller interrupt status register. 0 gpd r/w general-purpose data when the i/o pin has been enabled as an output, writing this bit determines the data value that is present on the corresponding i/o pin. if the i/o pin is enabled as an input, re ading this register bit represents the current voltage applied to the pin. at no time does this bit directly r epresent the value latched into the data register. if the pin is enabled as an input and there is no signal applied, a weak internal pull-up resistor holds the pin at a binary 1. after a reset or power on, this register bit is set to a binary 1; ho wever, the value returned from a register read is the level applied to the pin si nce each pin is an input by default. register name: bcis address: f8h reset value: 0000_0000b bit bit label access description 7:0 ia7-0 r interrupt active these eight bits determine the currently active interrupt source, which is enabled through the following registers: port bypass control, fan speed control, bit control, or general-purpose timer. the addresses of these registers are generated as an indicator of the currently active interrupt source. if multiple interrupt sources are active, the value generated is prioritized from the lowest binary value to the highest binary value. to clear the current interrupt and de-assert the int# pin, a value of ffh must be written to this register. if a higher binary value or lower priority interrupt source is still active, the new value is generated and the int# pin re-asserts. bit bit label access description
111 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.98 fch: backplane controller test (bct) the following table shows the bit assignments for the backplane controller test register. 3.2.99 fdh: clock select control (csc) the following table shows the bit assignments for the clock select control register. register name: bct address: fch reset value: 0xxx_x000b bit bit label access description 7 srst r/w soft reset setting this bit resets the device at the end of the current serial transfer. all inputs and outputs, control registers, clock dividers, and the slave state machine are reset by this bit. this bit is self-clearing. writing a 0 to this bit has no effect on the current state of the device. 6:3 res r reserved. 2 fsb r/w fan speed bypass setting this bit causes the main clock di vider for the fan speed monitors to be bypassed. bypassing the main clock di vider causes the f an speed counters to operate 500 times faster than normal. when reset or after power on, the normal clock divider is activated. do not set this bit during normal operation. 1 frb flash rate bypass setting this bit causes the main clock di vider for the flash rate generators to be bypassed. bypassing the main clock divi der causes the expected flash rates to be 125,000 times faster than normal. when reset or after power on, the normal clock divider is activated. this bit should not be set during normal operation. 0 sifb serial interface filter bypass setting this bit causes the digital filters on the scl and sda pins to be bypassed. bypassing the filt ers allows the serial transfer speed to be increased for test purposes. when reset or after power on, normal filtering is activated. do not set this bit during normal operation. register name: csc address: fdh reset value: 0000_0000b bit bit label access description 7 tfe r/w tach filter extend setting this bit causes the input filters on p2.0 through p2.7 to be extended from a two-stage voting circuit to a fi ve-stage voting circui t. additional noise immunity of approximat ely 300 ns is achieved. this bit enables the filter extension logic on all tach inputs and is independent of the tach control logic. the extended filters on p2.0 through p2.7 can be used in other applications with noisy signaling that require an enhanced input filter. after a reset or power on, this register bit is cleared to a 0, enabling normal input filter operation. 6 res r reserved.
112 of 134 vsc056 data sheet revision 4.1 january 2008 5:4 pds1-0 r/w pulse-width modula tion divider select these two bits determine the divider that is used for the pulse-width modulation circuits. the base frequency range of all pulse-width modulation circuits are controlled by these bits. ea ch pulse-width modulation circuit can be programmed to select one of the three available frequencies within the range. after a reset or power on, these register bits are cleared to a 0. the available frequency ranges are as follows: 3:0 sp3-0 synchronization period these four bits determine the sync hronization period of the device. the synchronization function can be used by a single vsc056 device for internal synchronization or by multiple vsc056 devices for chip-to-chip synchronization. at the end of the synchronization period, a pulse is generated on the sync# pin that causes this device , as well as all other de vices attached to the sync# pin, to re-synchronize their internal dividers. the device that asserts the sync# pin first determines the base synchronization period and effectively controls all other devices. the synchr onization period can vary from 2 seconds (0001b) to 16 seconds (1111b), depending on the value in these four bits. the user must ensure that all devices use the same synchronization period and that the period selected is a multiple of all selected led flash rate periods, including the pulse train values. these four bits are enabled when the syncen pin is tied to v dd and must be non-zero to enable device synchronization. additional ly, an external pull-up resistor (10 k ) must be connected to the sync# pin. bit bit label access description pds1 pds0 pulse-width modulation frequency range 0 0 26 khz, 52 khz or 104 khz (divide-by-3) 0 1 5.2 khz, 10.4 khz or 20.8 khz (divide-by-15) 1 0 1.04 khz, 2.08 khz or 4.16 khz (divide-by-75) 1 1 208hz, 416hz, 833hz (divide-by-375)
113 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.100 feh: clock divider control (cdc) the following table shows the bit assignments for the clock divider control register. the following table lists the appropriate cksel input clock divider values for the icd bit. register name: cdc address: feh reset value: 0000_0000b bit bit label access description 7:0 icd r/w internal clock divider these bits enable an internal clock divider that adjusts the clock source for the fan speed control and led blink contro l logic to provide a 20 khz base frequency. under normal conditions, when these bits remain reset, the cksel inputs determine the divide-by value used for generation of the 20 khz base frequency. if an external clock source between 8.0 mhz and 12.5 mhz or 32.0 mhz and 75.0 mhz that is not equal to one of the available frequencies defined by the cksel inputs is desired, this register should be programmed appropriately to adjust the divider. to simplify programming and provide an 8- bit value that can cover the desired range, the input clock source is divided by 3. this divider is positioned after the primary high-frequency divider, therefor e proper connection of the cksel2 and cksel1 inputs is required to dete rmine if both the source is a high-frequency source and whet her it should be divided by 4 or divided by 6. for example, if 66.67 mhz is the input clock frequency, the cksel2 and cksel1 inputs would be connected to v dd (divide by 6), yielding an 11.11 mhz internal clock, which is within the 8.0 mhz to 12.5 mhz operating range of the vsc056. the 11.11 mhz internal clock is then divided by 3 (3.7 mhz) and then divided by 185 (b8h is loaded into the cdc register) to achieve 20.02 khz. to enable the divider, set bit 7 of this regi ster to a 1. this limits the available divide by values from 129 (80h) to 256 (ffh), with a useful range of 133 (84h) to 208 (cfh). table 9, page 113 describes the appropriate cksel input and divider values requir ed to achieve the desired results with several input clock frequencies that are not available as part of the fixed divider logic. the cksel inputs must always be connected to either v ss or v dd based on the desired input clock range but in some cases, the value on cksel1 and cksel0 may not be important when using the cdc register. after a reset or power on, these register bits are cleared to a 0. these bits are not reset by the soft reset function. table 9. clock divider cksel2 cksel1 cksel0 input clock main divider cdc register 20 khz clock vss na na 8.5 mhz na 142 (8dh) 19.95 khz vss na na 9.0 mhz na 150 (95h) 20.0 khz vss na na 11.0 mhz na 183 (b6h) 20.03 khz vss na na 12.0 mhz na 200 (c7h) 20.0 khz vss na na 12.5 mhz na 208 (cfh) 20.03 khz vdd vss na 32.0 mhz divide-by-4 133 (84h) 20.05 khz vdd vss na 36.0 mhz divide-by-4 150 (95h) 20.0 khz vdd vss na 37.5 mhz divide-by-4 156 (9bh) 20.03 khz vdd vss na 48.0 mhz divide-by-4 200 (c7h) 20.0 khz
114 of 134 vsc056 data sheet revision 4.1 january 2008 3.2.101 ffh: backplane cont roller version (ver) the following table shows the bit assignments for the backplane controller version register. vdd vdd na 48.0 mhz divide-by-6 133 (84h) 20.05 khz vdd vdd na 60.0 mhz divide-by-6 167(a6h) 19.96 khz vdd vdd na 66.67 mhz divide-by-6 185 (b8h) 20.02 khz vdd vdd na 75.0 mhz divide-by-6 208 (cfh) 20.03 khz register name: ver address: ffh reset value: 0011_0001b bit bit label access description 7:0 ver7-0 r version these bits define the current version of the backplane controller. if revisions are required, these bits change to reflect the latest version of the device. generally, changes to bits 3:0 reflect a minor revi sion, and changes to bits 7:4 reflect a major revision or different device type. fi rmware should check this register to determine the current capabilities of the device. table 9. clock divider (continued) cksel2 cksel1 cksel0 input clock main divider cdc register 20 khz clock
115 of 134 vsc056 data sheet revision 4.1 january 2008 4 electrical specifications this section provides the dc charact eristics, ac characteristics, reco mmended operating conditions, and stress ratings for the vsc056 device. the dc and ac specifications listed in this sect ion are guaranteed over the recommended operating conditions unless otherwise noted. for information about operating conditions, see ?operating conditions,? page 121. 4.1 dc characteristics the following section shows the dc sp ecifications for the vsc056 device. the tables are grouped by functionality. 4.1.1 general-purpose i/o ports the following table lists the dc specifications for th e vsc056 when the device is configured in general- purpose i/o port mode for ports p7, p6, p5, p4, p3, p2, p1, and p0. table 10. general-purpose i/o ports parameter symbol minimum maximum unit condition output high voltage v oh 2.4 v dd vi oh = 12 ma output low voltage v ol v ss 0.4 v i ol = 12 ma input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current with pull-up i in ?25 ?125 a v in = v ss three-state output leakage (device test mode) i oz ?10 10 a
116 of 134 vsc056 data sheet revision 4.1 january 2008 4.1.2 two-wire serial interface the following table lists the dc specifications for the two-wire serial interfaces for the sda pin. the following table lists the dc specifications for the two-wire se rial interfaces for the scl pin. 4.1.3 address inputs the following table lists the dc specifications for address inputs, pins a2, a1, a0, and asel. table 11. two-wire serial interface, sda parameter symbol minimum maximum unit condition output low voltage v ol v ss 0.4 v i ol = 4 ma input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current with pull-up i in ?25 ?125 a v in = v dd /v ss three-state output leakage (device test mode) i oz ?10 10 a table 12. two-wire serial interface, scl parameter symbol minimum maximum unit condition input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current i in ?10 10 a v in = v dd /v ss table 13. address inputs parameter symbol minimum maximum unit condition input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current i in ?10 10 a v in = v dd /v ss
117 of 134 vsc056 data sheet revision 4.1 january 2008 4.1.4 interrupt output the following table lists the dc specifi cations for the interrupt output, int#. 4.1.5 reset, test, and synchr onization clock control inputs the following table lists the dc specifications for the test and synchronization clock control inputs, reset#, test, syncen, cksel2, cksel1, and cksel0. 4.1.6 device synchronization the following table lists the dc specifications for the multiple device synchronization, sync#. table 14. interrupt output parameter symbol minimum maximum unit condition output low voltage v ol v ss ? 0.5 0.4 v i ol = 4 ma table 15. reset,test, and synchronization clock control inputs parameter symbol minimum maximum unit condition input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current i in ?10 10 a v in = v dd /v ss table 16. multiple device synchronization parameter symbol condition minimum maximum unit output high voltage v oh i oh = 6 ma 2.4 v dd v output low voltage v ol i ol = 6 ma v ss 0.4 v input high voltage v ih 2.0 5.5 v input low voltage v il v ss ? 0.5 0.8 v schmitt threshold, positive v t+ 2.0 v schmitt threshold, negative v t? 0.8 v schmitt hysteresis v h 0.4 v input current with pull-up i in v in = v dd /v ss ?25 25 a three-state output leakage (device test mode) i oz ?10 10 a
118 of 134 vsc056 data sheet revision 4.1 january 2008 4.1.7 oscillator and clock input the following table lists the dc specifications for the oscillator and clock input, osci. 4.1.8 oscillator output the following table lists the dc specifi cations for the oscillator output, osco. table 17. oscillator and clock input parameter symbol minimum maximum unit condition input high voltage v ih v dd /2 v dd + 0.3 v input low voltage v il v ss ? 0.5 v dd /2 v switching threshold v t 0.8 v dd /2 v input current i in ?10 10 a v in = v dd /v ss table 18. oscillator output parameter symbol minimum maximum unit condition output high voltage v oh v dd ? 0.3 v dd vi oh = 4 ma output low voltage v ol v ss v ss + 0.3 v i ol = 4 ma
119 of 134 vsc056 data sheet revision 4.1 january 2008 4.2 ac characteristics the following section shows the ac sp ecifications for the vsc056 device. 4.2.1 external clock timing the following section contains the external cloc k cycle timing waveform and parameters for low- frequency and high-frequency oper ation for the external clock. the following table lists the ac char acteristics in low-frequency operation. the following table lists the ac char acteristics in high-frequency operation. figure 4. clock cycle timing waveform table 19. low-frequency operation parameter symbol minimum maximum unit condition frequency range f 8.0 12.5 mhz cksel2 = v ss clock cycle time t 1 80 125 ns cksel2 = v ss clock low time t 2 32 75 ns cksel2 = v ss clock high time t 3 32 75 ns cksel2 = v ss clock slew rate t 4 1v / n s table 20. high-frequency operation parameter symbol minimum maximum unit condition frequency range f 32.0 75.0 mhz cksel2 = v dd clock cycle time t 1 13.3 31.3 ns cksel2 = v dd clock low time t 2 5.3 18.8 ns cksel2 = v dd clock high time t 3 5.3 18.8 ns cksel2 = v dd clock slew rate t 4 1v / n s clock t 2 t 3 t 4 t 1
120 of 134 vsc056 data sheet revision 4.1 january 2008 4.2.2 two-wire serial interface timing this section provides information associated with device parameters that control the timing of the two-wire serial interface. the two-wire serial interface conforms to industry-standard timing for standard and fast mode operation. figure 5. two-wire serial interface timing diagram table 21. two-wire serial in terface timing characteristics parameter symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz bus free time t buf 4.7 1.3 s hold time?start condition t hd:sta 4.0 0.6 s scl low time t low 4.7 1.3 s scl high time t high 4.0 0.6 s setup time, start condition t su:sta 4.7 0.6 s hold time, data t hd:dat 00 0 . 9 s setup time, data t su:dat 250 100 s setup time, stop condition t su:sto 4.0 0.6 s scl sda s t a r t s t o p t buf t su:dat t su:sta t hd:sta t hd:dat t hd:sto t low t high
121 of 134 vsc056 data sheet revision 4.1 january 2008 4.3 operating conditions the following table lists the recommended operating conditions for the vsc056 device. 1. lower limit of specification is ambient temperature, and upper limit is case temperature. 4.4 maximum ratings stresses listed under absolute maximum ratings may be applied to devices one at a time without causing permanent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability. 1. this device has completed all required testing as specified in the jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) , and complies with a class 2 rating. the definition of class 2 is any part that passes an esd pulse of 2000 v, but fails an esd pulse of 4000 v. table 22. recommended operating conditions parameter symbol minimum typical maximum unit power supply voltage v dd 3.0 3.3 3.6 v operating temperature (1) t0 8 5 c table 23. absolute maximum ratings parameter symbol minimum maximum unit power supply voltage v dd ?0.3 3.9 v lvttl input voltage v in ?1.0 v dd + 0.3 v 5-v compatible input voltage v in ?1.0 6.5 v dc input current i in ?10 10 a latchup current i lp ?150 150 ma storage temperature t s ?40 125 c electrostatic discharge volt age, charged device model v esd_cdm ?1500 1500 v electrostatic discharge voltage, human body model v esd_hbm see note 1. v electrostatic discharge this device can be damaged by esd. maxim recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures may adversely affect reliability of the device.
122 of 134 vsc056 data sheet revision 4.1 january 2008 4.5 two-wire serial interface operation the following illustration shows the two-wire serial in terface read and write capabilities of the vsc056. all operations can be performed in any order. figure 6. two-wire serial interface operation a s e l s t a r t s a c k a c k a c k s t o p p a c k a c k a s e l s t a r t s a c k a c k a c k s t o p p a s e l s t a r t s a c k a c k a c k s t o p p a c k a c k s a s e l s t a r t a s e l s t a r t s a c k a c k s t o p p a c k s a s e l s t a r t multi-byte write byte write byte read multi-byte read slave address word address (n) data n data n + 1 data n + x slave address slave address word address (n) slave address word address (n) data data n slave address slave address word address (n) data n data n + 1 data n + x
123 of 134 vsc056 data sheet revision 4.1 january 2008 4.6 oscillator requirements the vsc056 can use an external 3.3-v, 8.0 mhz to 12.5 mhz clock source connected to the osci pin, with cksel2 tied to v ss . an external 3.3-v, 32.0 mhz to 50.0 mhz clock source can be connected to the osci pin with cksel2 tied to v dd and cksel1 tied to v ss . an external 3.3-v 48.0 mhz to 75.0 mhz clock source can be connected to the osci pin with cksel2 tied to v dd and cksel1 tied to v dd . alternatively, an 8.0 mhz to 12.5 mhz crystal and several passive components may be used. the following illustration shows two options when using a crystal. the passive components shown function properly for all crystal frequencies. option a requires fewer external components due to the high input capacitance of the osci pin and results in a st able configuration. optio n b represents a classic approach with a higher level of stability. 4.7 external reset circuit the vsc056 supports an internal power on reset circuit that eliminates the need for an external reset source. however, the device does su pport an external reset# pin, which can be driven by a power supply supervisor circuit, by a reset puls e sourced from another device, or by a circuit composed of a resistor, capacitor, and diode. if the external resistor-capacitor- diode circuit is used, the components selected must be able to provide a valid low to high transition after v dd is stable. the following diagram illustrates the external reset circuit. figure 7. oscillator options vsc056 osci osco 390 10 mhz option a 30 pf v ss vsc056 osci osco 390 10 m 10 mhz option b 30 pf 30 pf v ss v ss
124 of 134 vsc056 data sheet revision 4.1 january 2008 4.8 optional external tach filter the fan tach inputs of the vsc056 use schmitt trigger input buffers and are also internally digitally filtered. however, excessive external noise on a tach input can result in inaccurate fan speed current count values. the use of an external low- pass filter, along with the use of th e extended tach f ilter mode (tach filter extend, bit 7 of register fdh) of the vsc056 e liminates inaccurate cu rrent count values. the circuit in the following illustration provides excellent noise rejection at all possible rpm ranges supported by the vsc056. figure 8. external reset circuit figure 9. optional external tach filter vsc056 reset# r c v ss v dd v dd vsc056 p2.0 ? p2.7 330 3.3 k 0.1 f fan tach output v ss v dd
125 of 134 vsc056 data sheet revision 4.1 january 2008 5 pin descriptions this section contains the pin diagram and descriptions for the vsc056 device. 5.1 pin diagram the vsc056 has 100 pins. all pins have been placed to optimize their connection to external components. power and ground distribution is also optimized for core and high current i/o connections. all high current i/o pins, serial interface pins, and the inte rrupt output are 5-v tolerant. connect v dd and v dd2 to a 3.3 v power supply with no more than 10% tolerances. the following illustration shows the functional grouping of the signals. figure 10. functional signal grouping p1. 7 ? p1. 0 p0. 7 ? p0. 0 p3. 7 ? p3. 0 p2. 7 ? p2. 0 in t# a2 ? a0 scl asel sda cksel0 sync# s yn cen i/o por t s cl ock cont rol ser i al interface p4. 7 ? p4. 0 interrupt osci o sco p6. 7 ? p6. 0 p7. 7 ? p7. 0 p5. 7 ? p5. 0 cksel1 cksel2 test vsc 056 funct i onal tes t reset# ext ernal reset
126 of 134 vsc056 data sheet revision 4.1 january 2008 the following illustration shows the top view of the pin diagram. figure 11. pin diagram, top view 80 51 p0.2 81 50 1p 2 . 5 100 31 30 vsc056 p0.3 p7.4 p0.0 p0.1 vdd2 vdd vss test a1 a0 a2 cksel0 cksel2 cksel1 ocsi vdd vss asel osco p7.2 p7.3 p7.1 p6.7 p7.0 p6.6 p6.4 p6.5 vss p6.3 vdd p6.2 p0.5 p0.4 p0.6 p1.0 p0.7 p1.1 p1.2 p1.3 vss vdd p1.4 p1.5 vss vdd vss2 p2.7 p2.6 p3.0 p3.2 p3.1 p3.3 p3.5 p3.4 p3.6 vdd p3.7 vss p4.1 p4.0 p4.2 scl int# sda syncen sync# vss2 vdd vss p7.6 p7.7 p7.5 p1.6 p1.7 p2.0 p2.2 p2.1 p2.3 p2.4 p6.1 p5.7 p6.0 p5.6 p5.4 p5.5 p5.3 p4.3 p4.5 p4.4 p4.6 p4.7 p5.1 p5.0 vdd2 vdd p5.2 vss 90 40 10 20 60 70 reset#
127 of 134 vsc056 data sheet revision 4.1 january 2008 5.2 pin identifications this section contains the functional descriptions for the vsc056device. table 24. serial interface pin name pin number i/o pin description a2 a1 a0 10 9 8 input address select bus this pin group provides the value that is compared to bits 3:1 of the serial slave address. these pins should be strapped to v dd or v ss to provide the appropriate binary value. asel 11 input device type address select this pin provides the ability to se lect between two-device type address values in the serial sl ave address. when tied to v ss , the device type address is 1000b, and when tied to v dd , the device type address is 1100b. scl 22 input two-wire serial interface clock this pin is used by the device to latch the data present on the sda pin. this pin, in conjunction with the sda pin, also determines start and stop conditions on the serial bus. sda 23 bidirectional two-wire serial interface data this pin is used to transfer all serial data into and out of the device. this pin, in conjunction with the scl pi n, also determines start and stop conditions on the serial bus. table 25. clock pin name pin number type pin description osci 13 input oscillator input this pin is connected to one side of an external 8.0 mhz to 12.5 mhz crystal to produce the clock required for the vsc056. 8.0 mhz, 8.33 mhz, 8.854 mhz and 10.0 mhz are pre-defined fixed frequencies supported by the cksel pins when using a crystal. an alternate external 3.3 v, 8.0mhz to 12.5mhz or 32.0mhz to 75.0mhz clock source can be connected to this pin. 8.0mhz, 8.33mhz, 8.854mhz, 10.0m hz, 33.33mhz, 40.0mhz, 50.0mhz and 53.125mhz are pre-defined fixed frequencies supported by the cksel pins when using an external clock source. osco 12 output oscillator output this pin is connected to the other side of an external crystal. leave unconnected when using an external clock source. table 26. clock control pin name pin number i/o pin description cksel2 cksel1 cksel0 19 18 17 input clock select these three pins determine the input frequency of the clock or crystal that is connected to the vsc056 on the osci and osco pins. these pins also enable or disable the inte rnal system clock divider and adjust the flash rate and fan tach dividers to maintain the proper internal clock rates.
128 of 134 vsc056 data sheet revision 4.1 january 2008 table 27. interrupt pin name pin number i/o pin description int# 24 open-drain output interrupt this pin can be used to signal the microcontroller that an event has occurred on an i/o pin that is configur ed as an input or a special function event has occurred. it can be wire or ed with other open-drain outputs to provide a single interrupt input source. table 28. multiple device synchronization pin name pin number i/o pin description sync# 20 open-drain bidirectional synchronization control this pin provides an internal or external clock synchronization mechanism when the syncen pin is tied high. it can be connected to the sync# pin of other vsc056 devices or can be used independently to synchronize internally. when enabled, all devices re-synchronize their internal clock dividers to the first device that pulls this pin low. the synchronization pulse causes all devices to clear their internal dividers and ensures that devices on different two-wire serial busses have synchronized led flashing. the clock select control register pr ovides additional programmability to determine the appropriate re-synchronization timing. an external 10 k resistor should be connected to this pi n if the function is enabled. if not enabled, a weak internal pull-up will maintain a high level. syncen 21 input synchronization enable input this pin enables the synchronization control feature. when tied to v ss , synchronization control is disabled. when tied to v dd , synchronization control is enabled. when enabled, additional control is available in the clock select control register. table 29. i/o ports pin name pin number i/o description p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 96 97 98 99 100 1 5 6 bidirectional i/o port 0, pulse-width outputs port 0 is a dedicated 8-bit bidirecti onal i/o port. the user can select between an input, totem pole output, or open-drain or open-source output. capability to detect input edge changes and select various output flashing rates is also available. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver.
129 of 134 vsc056 data sheet revision 4.1 january 2008 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 86 87 88 89 92 93 94 95 bidirectional i/o port 1, pulse-width outputs port 1 is a dedicated 8-bit bidirecti onal i/o port. the user can select between an input, totem pole output, or open-drain or open-source output. capability to detect input edge changes and select various output flashing rates is also available. through control register setup, p1.7-p1.0 can be enabled as pulse- width modulated outputs, with duty cycles of 0% to 100% in 3% increments at nominal frequencies of 104 khz, 52 khz, and 26 khz. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 75 76 80 81 82 83 84 85 bidirectional i/o port 2, tach inputs port 2 is an 8-bit bidirectional i/ o port. the user can select between an input, totem pole output, or op en-drain or open-source output. capability to detect input edge changes and select various output flashing rates is also available. through control register setup, p2.7-p2.0 can be dedicated to monitoring fans equipped with tachometer outputs. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 67 68 69 70 71 72 73 74 bidirectional i/o port 3, bypass i/os port 3 is a shared 8-bit bidirectional i/o port that can be used as a general-purpose i/o port or as port bypass control. the user can select between an input, totem pole output, or open-drain or open- source output. capability to det ect input edge changes and select various output flashing rates is also available. through control register setup, four 2-bit portions of this port can be dedicated to the control of a comb ination of pbc/cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general-purpose functions. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. table 29. i/o ports (continued) pin name pin number i/o description
130 of 134 vsc056 data sheet revision 4.1 january 2008 p4.7 p4.6 p4.5 p4.4 p4.3 p4.2 p4.1 p4.0 57 58 59 60 61 62 63 64 bidirectional i/o port 4, bypass i/os port 4 is a shared 8-bit bidirectional i/o port that can be used as a general-purpose i/o port or as port bypass control. the user can select between an input, totem pole output, or open-drain or open- source output. capability to det ect input edge changes and select various output flashing rates is also available. through control register setup, four 2-bit portions of this port can be dedicated to the control of a comb ination of pbc/cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general-purpose functions. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 46 47 48 49 50 51 55 56 bidirectional i/o port 5, bypass i/os port 5 is a shared 8-bit bidirectional i/o port that can be used as a general-purpose i/o port or as port bypass control. the user can select between an input, totem pole output, or open-drain or open- source output. capability to det ect input edge changes and select various output flashing rates is also available. through control register setup, four 2-bit portions of this port can be dedicated to the control of a comb ination of pbc/cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general-purpose functions. through bit control register setup, each odd bit of this port can be enabled as an output which on a pair by pair basis, reflects the current state of each even bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/ source driver. p6.7 p6.6 p6.5 p6.4 p6.3 p6.2 p6.1 p6.0 36 37 38 39 42 43 44 45 bidirectional i/o port 6, bypass i/os port 6 is a shared 8-bit bidirectional i/o port that can be used as a general-purpose i/o port or as port bypass control. the user can select between an input, totem pole output, or open-drain or open- source output. capability to det ect input edge changes and select various output flashing rates is also available. through control register setup, four 2-bit portions of this port can be dedicated to the control of a comb ination of pbc/cru/sdu functions. any combination of port bypass control functions can be enabled with the remaining i/o pins used for general-purpose functions. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. table 29. i/o ports (continued) pin name pin number i/o description
131 of 134 vsc056 data sheet revision 4.1 january 2008 p7.7 p7.6 p7.5 p7.4 p7.3 p7.2 p7.1 p7.0 25 26 30 31 32 33 34 35 bidirectional i/o port 7, bypass i/os port 7 is a dedicated 8-bit bidirecti onal i/o port. the user can select between an input, totem pole output, or open-drain or open-source output. capability to detect input edge changes and select various output flashing rates is also available. through bit control register setup, each odd-numbered bit of this port can be enabled as an output, which on a pair-by-pair basis, reflects the current state of each even-numbered bit of this port. individual control is provided that allows programming each output as a totem pole or an open-drain/source driver. table 30. reset pin name pin no. type description reset# input reset this pin clears all functi ons within the two-wire serial slave interface and forces all logic to a known state. t he reset input is not required to be synchronous to the system clock. internal circuitry synchronizes the trailing edge of the reset pulse, and the leading edge of the reset pulse asynchronously resets the two-wire serial slave interface within the device. the reset# pin must be asserted low for a minimum of 100 ns after all power supplies have stabilized. if required, it can be asserted low at any time thereafter, with 100 ms minimum pulse width. table 31. test pin name pin no. type description test 7 input functional test this pin allows the device to be plac ed in specific test modes for device level testing. connect to v ss for normal operation. table 32. power supplies pin name pin number i/o description vdd 3, 15, 29, 41, 53, 66, 79, 91 power i/o power supply these pins are the power sources for the i/o drivers of all non-analog output and bidirectional pins. vss 2, 14, 28, 40, 52, 65, 78, 90 ground i/o ground these pins are the ground connections for the i/o drivers of all non-analog output and bidirectional pins. vdd2 4, 54 power digital core power supply these pins are the power sources for the digital core logic and receivers of all non-analog input and bidirectional pins. vss2 27, 77 ground digital core ground these pins are the ground c onnections for the digital core logic and receivers of all non-analog input and bidirectional pins. table 29. i/o ports (continued) pin name pin number i/o description
132 of 134 vsc056 data sheet revision 4.1 january 2008 6 package information the vsc056 device is available in two package types. vsc056km is a 100-pin, plastic quad flat package (qfp) with a 20 mm body width, 14 mm body length , 2.7 mm body thickness, 0.65 mm pitch, and 3.1 mm maximum height. the device is also availabl e in a lead(pb)-free package, VSC056XKM. lead(pb)-free products from maxim comply with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j- std-020. for more information, see the ipc and jedec standard. 6.1 thermal specifications thermal specifications for this device are based on the jedec standard eia/jesd51-2 and have been modeled using a four-layer test board with two signal layers, a power plane, and a ground plane (2s2p pcb). for more information, see the jedec standard. to achieve results similar to the modeled thermal resistance measurements, the guidelines for board design described in the jedec standard eia/jesd51 series must be applied. for information about specific applications, see the following: eia/jesd51-5, extension of thermal test board standards for packages with direct thermal attachment mechanisms eia/jesd51-7, high effective thermal conductivity test board for leaded surface mount packages eia/jesd51-9, test boards for area array surface mount package thermal measurements eia/jesd51-10, test boards for through-hole perimeter leaded package thermal measurements eia/jesd51-11, test boards for through-hole area array leaded package thermal measurements 6.2 moisture sensitivity this device is rated moisture sensitivity level 3 or be tter as specified in the joint ipc and jedec standard ipc/jedec j-std-020. for more informat ion, see the ipc and jedec standard. 6.3 package drawing the following illustration shows the package drawing for the vsc056 device. the drawing contains the top view, side view, detail views, dimensions, tolerances, and notes. table 33. thermal resistances part order number ja (c/w) vs. airflow (ft/min) jc 0 100 200 vsc056km 25.9 48.78 45.04 43.31 VSC056XKM 21.6 45.68 41.94 40.22
133 of 134 vsc056 data sheet revision 4.1 january 2008 figure 12. package drawing top view side view dimensions and tolerances r1 radius r2 radius detail b detail a see detail a seating plane see detail b a pin 1 indicator reference minimum a a1 a2 b b1 c c1 d d1 d2 e e1 e2 e l l1 r1 r2 s 0.10 2.57 0.22 0.22 0.13 0.11 23.65 19.90 17.65 13.90 0.73 0.13 0.40 12 0 0 nominal maximum 3.10 0.36 2.87 0.38 0.36 0.23 0.19 24.15 20.10 18.15 14.10 1.03 16 7 3.04 0.23 2.71 0.30 0.15 23.90 20.00 18.85 17.90 14.00 12.35 0.65 0.88 1.95 ref. 0.30 all dimensions and tolerances in millimeters.
134 of 134 vsc056 data sheet revision 4.1 january 2008 7 ordering information the vsc056 device is available in two package types. vsc056km is a 100-pin plastic qfp. the device is also available in a lead(pb)-free package, VSC056XKM. lead(pb)-free products from maxim comply with the temperatures and profiles defined in the joint ipc and jedec standard ipc/jedec j- std-020. for more information, see the ipc and jedec standard. table 34. ordering information part number description vsc056km 100-pin, plastic quad flat package (qfp ) with a 20 mm body width, 14 mm body length, 2.7 mm body thickness, 0.65 mm pitch, and 3.1 mm maximum height VSC056XKM lead(pb)-free, 100-pin, plastic quad flat package (qfp) with a 20 mm body width, 14 mm body length, 2.7 mm body thickness, 0.65 mm pitch, and 3.1 mm maximum height maxim integrated products 120 san gabriel drive sunnyvale, ca 94086 united states 408-737-7600 www.maxim-ic.com copyright ? 2006 to 2008 maxim integrated products maxim cannot assume responsibility for use of any circuitry ot her than circuitry entirely embod ied in a maxim product. maxim re tains the right to make changes to its products or specifications to improve performance, re liability or manufacturability. all infor mation in this document, includ ing descriptions of features, function s, performance, techni cal specifications and availability, is subjec t to change without notice at any time. while the information furnished herein is held to be accura te and reliable, no responsibilit y will be assumed by maxim for its use. furthermore, the information contai ned herein does not convey to the purchaser of microelectronic devices any license under the patent right of any manufacturer. maxim products are not intended for use in life support products where failure of a maxim product could reasonably be expected to result in death or personal injury. anyone using a maxim product in such an application without express written consent of an o fficer of maxim does so at their own risk, and agr ees to fully indemnify maxim for any damages that may result from such use or sale. is a registered trademark of maxim integrated products, inc. all other products or service names used in this publication are for i dentification purposes only, and may be trademarks or reg istered trademarks of their respective companies. all other trademarks or registered trademarks mentioned herein are the property of th eir respective holders.

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