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unisonic technologies co., ltd ur5596 cmos ic www.unisonic.com.tw 1 of 12 copyright ? 2008 unisonic technologies co., ltd qw-r502-045,c ddr termination regulator ? description the utc ur5596 is a linear bus termination regulator and designed to meet jedec sstl- 2(stub-series terminated logic) specifications for termination of ddr-sdram. it also can be used in sstl-3 or hstl (high-speed transceiver logic) scheme. the device contains a high-speed op amp to provide excellent response to the load tr ansients, and can deliver 1.5a continuous current and transient pea ks up to 3a in the application as required for ddr-sdram termination. the utc ur5596 also incorporates a v sense pin to provide superior load regulation and a v ref output as a reference for the chipset and dimms. besides, an active low shutdown (shdn) pin provides suspend to ram (str) functionality. when shdn is pulled low the v tt output will tri-state pr oviding a high impedance output, but, v ref will remain active. a power savings advantage can be obtained in this mode through lower quiescent current. regarding the output, v tt is capable of sinking and sourcing current while regulating the output voltage equal to v ddq / 2. the output stage has been designed to maintain excellent load regulation while preventing shoot through. the utc ur5596 also incorporates two distinct power rails that separates the analog circuitry from the power output stage. this allows a split rail approach to be utilized to decrease internal power dissipation and permits utc ur5596 to provide a termination solution for ddrii sdram. ? features * source and sink current * low output voltage offset * no external resistors required * linear topology * suspend to ram (str) functionality * low external component count * thermal shutdown protection *pb-free plating product number: ur5596l ? ordering information ordering number normal lead free plating package packing ur5596-s08-r ur5596l-s08-r sop-8 tape reel ur5596-s08-t ur5596l-s08-t sop-8 tube UR5596-SH2-R ur5596l-sh2-r hsop-8 tape reel ur5596-sh2-t ur5596l-sh2-t hsop-8 tube ur5596l-s08-r (1) packing type (2) package type (3) lead plating (1) r: tape reel, t: tube (2) s08: sop-8 (3) l: lead free plating, blank: pb/sn
ur5596 cmos ic unisonic technologies co., ltd 2 of 12 www.unisonic.com.tw qw-r502-045,c ? pin configuration 8 7 6 5 4 3 2 1 hsop-8 gnd av in gnd v ref v sense pv in v tt shdn v ddq ? pin description pin no. pin name pin function 1 gnd ground 2 shdn shutdown 3 v sense feedback pin for regulating v tt . 4 v ref buffered internal reference voltage of v ddq /2 5 v ddq input for internal reference equal to v ddq /2 6 av in analog input pin 7 pv in power input pin 8 v tt output voltage for connection to termination resistors
ur5596 cmos ic unisonic technologies co., ltd 3 of 12 www.unisonic.com.tw qw-r502-045,c ? block diagram
ur5596 cmos ic unisonic technologies co., ltd 4 of 12 www.unisonic.com.tw qw-r502-045,c ? absolute maximum ratings parameter symbol ratings unit pv in , av in , v ddq to gnd v dd -0.3 ~ +6 v supply voltage av in to gnd(note 1) v dd 2.2 ~ 5.5 v junction temperature t j +150 operation temperature t opr 0 ~ +125 storage temperature t stg -40 ~ +150 note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? thermal data parameter symbol ratings unit thermal resistance junction-ambient ja 150
/w ? electrical characteristics (t j =25c, v in =av in =pv in =2.5v, v ddq =2.5v, unless otherwise specified). parameter symbol test conditions min typ max unit v ref voltage v ref v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.130 1.235 1.335 1.158 1.258 1.358 1.185 1.285 1.385 v i out = 0a v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 v tt output voltage i out = 1.5a v tt v in = v ddq = 2.3v v in = v ddq = 2.5v v in = v ddq = 2.7v 1.125 1.225 1.325 1.159 1.259 1.359 1.190 1.290 1.390 v high v ih 1.9 minimum shutdown level low v il 0.8 v v tt output voltage offset (v ref - v tt ) vos tt v tt i out = 0a i out = -1.5a i out = +1.5a -20 -25 -25 0 0 0 20 25 25 mv quiescent current i q i out = 0a 320 500 a quiescent current in shutdown i sd sd = 0v 115 150 a shutdown leakage current i q_sd sd = 0v 2 5 a v tt leakage current in shutdown i v sd = 0v v tt = 1.25v 1 10 a v sense input current i sense 13 na v ref output impedance z vref i ref = -30 ~ +30 a 2.5 k ? v ddq input impedance z vddq 100 k ? thermal shutdown t sd 165
thermal shutdown hysteresis t sd-hys 10

ur5596 cmos ic unisonic technologies co., ltd 5 of 12 www.unisonic.com.tw qw-r502-045,c ? pin descriptions av in , pv in input supply pins . av in is used to supply all the internal analog circuits and pv in is used to provide the output stage to create v tt . these pins have the capability to work off separ ate supplies depending on the application. higher voltages on pv in will increase the maximum continuous output current because of output rdson limitations at voltages close to v tt . but the internal power loss will also increase, thermally limiting the design. if the junction temperature exceeds the thermal shutdown than the part will enter a shutdown state identical to the manual shutdown where v tt is tri-stated and v ref remains active. for sstl-2 applications, a good compromise would be to connect the av in and pv in directly together at 2.5v. this eliminates the need for bypassing the tw o supply pins separately. the only limit ation on input voltage selection is that pv in must be equal to or lower than av in . it is recommended to connect pv in to voltage rails equal to or less than 3.3v to prevent the thermal lim it from tripping because of excessive internal power dissipation. v ddq the input pin used to create the internal reference voltage from a resistor divider of two internal 50k ? ? resistors for regulating v tt and to guarantee v tt will track v ddq /2 precisely. as a remote sense by connecting v ddq directly to the 2.5v rail for sstl-2 applications is an optimal implementation of v ddq at the dimm. this ensur es that the reference voltage tracks the ddr memory rails precisely with out a large voltage drop from the power lines. v sense the sense pin supply improved remote load regulation, if remote load regulation is not used then the v sense pin must still be connected to v tt . a long trace will cause a significant ir dr op resulting in a termination voltage lower at one end of the bus than the other. connect v sense pin to the middle of the bus to provide a better distribution across the entire termination bus then ddr performance will be improved. take notice of when a long v sense trace is implemented in close proximity to the memory, noise pickup in the v sense trace can cause problems with precise regulation of v tt . a ceramic capacitor of 0.1uf is placed to next the v sense pin can help filter any high frequency signals and preventing errors. v ref v ref supply the buffered output of the internal reference voltage v ddq /2. this output delivers the reference voltage for the northbridge chipset and memory. since these inputs are typically extremely high impedance, there should be little current drawn from v ref . a 0.1f~0.01f ceramic capacitor could be used to acquire better performance, located close to the pin to help with noise. this out put remains active during t he shutdown state and thermal shutdown events for the suspend to ram functionality. v tt v tt is a regulated output for the bus resistors termination of ddr-sdram. it can track precisely the v ddq /2 voltage with the sinking and sourcing current capability. the utc ur5596 is designed to handle peak transient currents of up to 3a with a fast transient response. if a transient is expected to remain above the maximum continuous current rating for a significant amount of time then the output capacit or size should be large enough to prevent an excessive voltage drop. although utc ur5596 can handle large transient output currents, but it can not handling t hese for long durations since the limited thermal dissipation capa bility of sop-8 package. if large curr ents are required for longer durations, then must ensure the maximum junction temperature is not exceeded, otherwise , the maximum output current will be degraded with heating. proper thermal de-rating should always be used. while the temperature beyond the junction temperature, the thermal shutdown pr otection will be functioned, then v tt will tri-state until the part returns below the hysteretic trigger point.
ur5596 cmos ic unisonic technologies co., ltd 6 of 12 www.unisonic.com.tw qw-r502-045,c ? capacitor selection a capacitor is recommended for improve performance duri ng large load transients to prevent the input rail from dropping, even though ur5596 does not require for input stability. the i nput capacitor should be located as close as possible to the pv in pin. the typical recommended value for al electrolytic capacitors is 50 f and 10 f with x5r or better for ceramic capacitors. if av in and pv in are separated, the 47 f capacitor should be placed as close to possible to the pv in rail. an additional 0.1uf ceramic capacitor c an be placed on the avin rail to prevent excessive noise from coupling into the device. utc ur5596 has been designed to be insensitive of output capacitor size or esr (equivalent series resistance). the choice for output capacitor depends on the application and the requirements for load transient response of v tt . as a general recommendation the output capacitor should be sized above 100 f with a low esr for sstl applications with ddr-sdram. the value of esr should be determined by the maximum current spikes expected and the extent at which the output voltage is allowed to droop. ? thermal dissipation the ur5596 will generate heat result from internal power dissipation when current flow working. the device might be damaged any beyond maximum junction temperature rati ng. the maximum allowable internal temperature rise (t rmax ) can be calculated given the maximum ambient temperature (t amax ) of the application and the maximum allowable junction temperature (t jmax ). t rmax = t jmax ? t amax from this equation, the maximum power dissipation (p dmax ) of the part can be calculated: p dmax = t rmax / ja the ja of ur5596 can be calculated (refer to jedec standard) and will depend on several package type, materials, ambient air temperature and so on.
ur5596 cmos ic unisonic technologies co., ltd 7 of 12 www.unisonic.com.tw qw-r502-045,c ? typical application circuits following demonstrate several different application circuits to illustrate some of the opt ions that are possible in configuring the utc ur5596 . the individual circuit performance can be found in the typical performance characteristics that curve graphs illustrate how the maximum output current is affected by changes in av in and pv in . stub-series terminated logic(sstl) termination scheme sstl was created to improve signal integrity of the data transmission across the memory bus. this termination scheme is essential to prevent data error from signal re flections while transmitting at high frequencies encountered with ddr-sdram. class ii single parallel termination(sstl-2) is the most popular terminat ion form. it involves one r s series resistor from the chipset to the memory and one r t termination resistor (refer to figure 1). r s and r t are changeable to meet the current requirement from ur5596, the recommended values both r s and r t are 25 ? figure 1. sstl-termination scheme for sstl-2 applications for the majority of applications that implement the sstl- 2 termination schem e, it is recommended to connect all the input rails to the 2.5v rail as figure 2. this provides an optimal trade-off between power dissipation and component count and selection. + + + v tt v ddq v sense v ref gnd shdn av in pv in c in shdn v ddq =2.5v v dd =2.5v c out c ref v ref =1.25v v tt =1.25v utc ur5596 figure 2. recommended sstl-2 implementation
ur5596 cmos ic unisonic technologies co., ltd 8 of 12 www.unisonic.com.tw qw-r502-045,c ? typical application circuits(cont.) figure 3 illustrate another a pplication that the power rails are split when power dissipation or efficiency are concerned. the output stage (pv in ) can be as lower as 1.8v, and the analog circuitry (av in ) can be connected to a higher rail such as 2.5v, 3.3v or 5v. this allows the internal power dissipation to be lowered when sourcing current from v tt , but the disadvantage of this circuit is the maximum continuous current is reduced. + + + v tt v ddq v sense v ref gnd shdn av in pv in c in shdn v ddq =2.5v av in =2.2v ~ 5.5v c out c ref v ref =1.25v v tt =1.25v utc ur5596 pv in =1.8v figure 3. lower power dissipation sstl-2 implementation the third optional appl ication is that pv in connect to 3.3v and av in will be always limited to operation on the 3.3v or 5v to always equal or higher than pv in . this configuration has the ability to provide the maximum continuous output current at the downside of hi gher thermal dissipation. the power di ssipation increasing problem must be careful to prevent the junction temperature to exceed t he maximum ranting. because of this risk it is not recommended to supply the output stage with a voltage higher than a nominal 3.3v rail. + + + v tt v ddq v sense v ref gnd shdn av in pv in c in shdn v ddq =2.5v av in =3.3v or 5.5v c out c ref v ref =1.25v v tt =1.25v utc ur5596 pv in =3.3v figure 4. sstl-2 implementation with higher voltage rails
ur5596 cmos ic unisonic technologies co., ltd 9 of 12 www.unisonic.com.tw qw-r502-045,c ? typical application circuits(cont.) for ddr-ii applications as a result of the separate v ddq pin and an internal resistor divider, ur5596 can be utilized in ddr-ii system, figure 5 and 6 show two recommended circuits in ddr-ii s dram application. the output stage is connected to the 1.8v rail and the av in pin can be connected to either a 3.3v or 5v rail. if it is not desirable to use the 1.8v rail it is possible to connect the output stage to a 3.3v rail. the power dissipation increasing concern must be careful as well sstl-ii application. the advantage of configuration of figure 6 is that it has the ability to source and sink a higher maximum continuous current. figure 5. recommended ddr-ii termination + + + v tt v ddq v sense v ref gnd shdn av in pv in c in shdn v ddq =1.8v av in =3.3v or 5.5v c out c ref v ref =0.9v v tt =0.9v utc ur5596 pv in =3.3v figure 6. ddr-ii termination with higher voltage rails
ur5596 cmos ic unisonic technologies co., ltd 10 of 12 www.unisonic.com.tw qw-r502-045,c ? typical characteristics 4 3.5 3 2.5 2 1.5 1 0.5 2 2.5 3 3.5 4 4.5 5 5.5 av in (v) v ih and v il 1.40 1.10 -30 -20 0 10 20 30 i ref ( 0 a) v ref vs i ref 1.35 1.30 1.25 1.20 1.15 -10
ur5596 cmos ic unisonic technologies co., ltd 11 of 12 www.unisonic.com.tw qw-r502-045,c ? typical characteristics(cont.)
ur5596 cmos ic unisonic technologies co., ltd 12 of 12 www.unisonic.com.tw qw-r502-045,c utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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