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16-bit integrated clock-lut-dac block schematic pixel adr and mask color palette 256 x 18 bit 24 18 byps mux norm latch 24 compare triple 6/8-bit dac timing gen. mux. mode ctl 8 pll parameter & clk0 pll 1 pll parameter & clk1 pll 2x clk0 clk1 red green blue rset vref buff. latch micro- processor interface xtal osc 8 16 16 blank* pclk p0-p15 d0-d7 wr* rd* rs0-rs2 xin xout strobe cs0-cs2 pclk sense* 5342_01.ai general description the ICS5342 gendac is a combination of dual programma- ble clock generators, a 256 x 18-bit ram, and a triple 8-bit video dac. the gendac supports 8-bit pseudo color appli- cations, as well as 15-bit, 16-bit, and 24-bit true color bypass for high speed, direct access to the dacs. the ram makes it possible to display 256 colors selected from a possible 262,144 colors. the dual clock generators use phase locked loop (pll) technology to provide program- mable frequencies for use in the graphics subsystem. the vid- eo clock contains 8 frequencies, all of which are programmable by the user. the memory clock has two pro- grammable frequency locations. the three 8-bit dacs on the ICS5342 are capable of driving singly or doubly-terminated 75 w loads to nominal 0 - 0.7 volts at pixel rates up to 135 mhz. differential and integral linearity errors are less than 1 lsb over full temperature and vdd ranges. monotonicity is guaranteed by design. on-chip pixel mask register allows displayed colors to be changed in a single write cycle rather than by modifying the color palette. ics is the world leader in all aspects of frequency (clock) gen- eration for graphics, using patented techniques to produce low jitter video timing. features triple video dac, dual clock generator, and 16 bit pixel port dynamic mode switch allows switching of color depth on a pixel by pixel basis 24 (packed and sparse), 16, 15, or 8-bit pseudo color pixel mode supports true color, hi-color, and vga modes high speed 256 x 6 x 3 color palette (135 mhz) with bypass mode and 8-bit dacs eight programmable video (pixel) clock frequencies (clk0) dac power down in blanking mode anti-sparkle circuitry on-chip loop ?ters reduce external components standard cpu interface single external crystal (typically 14.318 mhz) monitor sense internal voltage reference 135 mhz (-3), 110 mhz (-2) & 80 mhz (-1) versions very low clock jitter two latched frequency select pins or three non-latched frequency select pins (programmable) hardware video checksum for manufacturing tests ICS5342 gendac 16-bit integrated clock-lut-dac rev. 0.9.0 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 1 data sheet ICS5342
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 2 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 2 pin con?uration pin con?uration pin description (68-pin plcc) symbol pin # type description d7 - d0 21-14 i/o systems data bus bidirectional data i/o lines ?used by host microprocessor for internal register read and write operations (using active low rd and wr respec- tively) for six internal registers: pixel address, color value, pixel mask, pll address, pll parameter, and command during the write cycle, the rising edge of wr latches the data into the selected register (set by the status of the three rs pins). the rising edge of rd determines the end of the read cycle. the rd set logical high indicates that data i/o lines no longer contain infor- mation from the selected register and will be tri-stated. rd 5 input ram/pll read enable bus control signal ?in active low state, any information present on the internal data bus is available on the data i/o lines, d0-d7 wr 22 input active low ram/pll write enable bus control signal ?controls write timing on microprocessor interface inputs, d0-d7 rs2-rs0 63,24,23 input register address select 0 inputs ?control selection of one of six internal registers ? inputs are sampled on falling edge of active enable signal (rd or wr ) xin 48 input crystal input ?connect to 14.318 mhz crystal xout 49 output crystal output ?connect to 14.318 mhz crystal msw 25 input mode switch ?digital control for selecting primary and secondary pixel color modes ?low selects primary mode ?connect to ground if not used agnd n/c n/c n/c n/c n/c n/c n/c n/c n/c red avdd cvdd grn blue rset dvdd cgnd pclk p7 p6 p5 p4 p3 p2 p1 p0 xvdd xgnd xout xin vref n/c dgnd 5342_02 clk0 p13 rd* strobe* blank* p9 cs1 cs0 p12 p11 cvdd p10 p8 n/c cvdd sense* 36 35 34 33 32 31 30 29 28 27 40 39 38 37 43 42 41 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 2 3 4 5 6 7 8 9 68 64 65 66 67 61 62 63 gendac ii ICS5342 d0 d1 d2 d3 d4 d5 cgnd clk1 p14 p15 wr* rs0 rs1 msw cgnd 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 d7 d6 rs2 ICS5342 (68-pin plcc)
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 3 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 3 clk1 11 output memory clock output ?used to time video memory clk0 8 output video clock output ?provides a cmos level pixel or dot clock frequency to graphics controller ?output frequency is determined by values of pll registers cs0 2 input clock select 0 ?the status of cs0-1 determines which frequency is selected on the clk0 (video) output. cs1 3 input clock select 1?status of cs0-1 determines which frequency is selected on clk0 (video) output vref 46 i/o internal reference voltage ?normally connects to a 0.1 m f capacitor to ground ?to use external vref, connect 1.235v reference to this pin rset 42 input resistor set ?pin used to set current level in analog outputs ?usually connected through 1/4w, 1% resistor to ground sense* 68 output monitor sense ?pin is active low when any of red, green, or blue outputs >385mv. sense output is high when all analog outputs are < 275 mv. chip has on-board comparators and internal 1.235 v voltage reference. this signal is used to detect monitor type. blue green red 40 38 37 output output output color signals from dac analog outputs ?each dac comprises several current sources of which outputs are added together according to the applied binary value. the outputs are typically used to drive a crt monitor. p15- p0 13,12,4,1 , 67-64, 58-51 input pixel address lines ?byte-wide information is latched by the rising edge of pclk when using the color palette, and is masked by the pixel mask register. values are used to specify the ram word address in default mode (accessing ram). in hi- color xga, and true color modes, they represent color data for the dacs. ground inputs if they are not used. pclk 59 input pixel clock ?rising edge of pclk controls latching of the pixel address and blank* inputs ?clock also controls progress of these values through the three- stage pipeline of the color palette ram, dac, and outputs strobe* 6 input latches input clock select signals cs0-cs1 blank* 7 input composite blank* signal, active low. when blank* is asserted, outputs of dacs are zero which blacks screen. dacs are automatically powered down to save current during blanking. color palette may still be updated through d0-d7 during blanking. cvdd 9 - clk1 power supply ?connect to dvdd cvdd 27 - clk0 power supply ?connect to avdd avdd 41 - dac power supply ?connect to avdd dvdd 43 - digital power supply xvdd 50 - crystal oscillator power supply?connect to avdd cvdd 61 - clk power supply ?connect to dvdd cgnd 10 - vss for clk1 ?connect to ground. cgnd 26 - vss for clk0 ?connect to ground xgnd 47 - vss for crystal oscillator agnd 36 - dac ground ?connect to ground dgnd 44 - digital ground ?connect to ground cgnd 60 - vss for clk ?connect to ground n/c 28-35, 39,45, 62 - not connected ?leave ?ating or tie to ground pin description (68-pin plcc) symbol pin # type description
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 4 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 4 internal registers rs2 rs1 rs0 register name description (all registers can be written to and read from) the gendac has a single pixel address register which can be accessed through either register address 0,0,0 or 0,1,1 ?reading from either register gives the same result. writing a value to address 0,0,0: ?speci?s an address within the color palette ram ?initializes the color value register writing a value to address 0,1,1: ?speci?s an address within the color palette ram ?loads color value register with contents of location in addressed ram palette and then: ?increments pixel address register 0 1 1 pixel address write writing to this 8-bit register is done before writing one or more color values to color palette ram. 0 1 1 pixel address read writing to this 8-bit register is done before reading one or more color values from color palette ram. 0 0 1 color value the 18-bit color value register acts as a buffer between the microprocessor interface and the color palette. a value may be read from or written to this register using a three-byte transfer sequence. the color value is contained in the least signi?ant 6 bits, d0-d5, of the byte read ?the most signi?ant 2 bits are set to zero. the same 6 bits are used when writing a byte. when reading or writing, data is transferred in the same order ?red byte ?st, then green, then blue. each transfer between the color value register and the color palette replaces the normal pixel mapping operations of the gendac for a single pixel. after writing three de?itions to this register, its contents are written to the location in the color palette ram speci?d by the pixel address register, before that register increments. after reading three de?itions from this register, the contents of the location in the color palette ram speci?d by the pixel address registers are copied into the color value register, and the pixel address register increments. 0 1 0 pixel mask the 8-bit pixel mask register can be used to mask selected bits of the pixel address value applied to the pixel address inputs (p7-p0). a one in a position in the mask register leaves the corre- sponding bit in the pixel address unaltered, while a zero sets that bit to zero. the pixel mask register does not affect the pixel address generated by the microprocessor interface when the pal- ette ram is being accessed. 1 0 0 pll address write writing to this 8-bit register is performed prior to writing one or more pll programming values to the pll parameter register. 1 1 1 pll address read writing to this 8-bit register is performed prior to reading one or more pll programming values from the pll parameter register.
ICS5342 gendac 5 1 1 0 command this 8-bit register selects color mode, for instance 8-bit pseudo color, hi-color, true color, or xga, and dac power down. the registers are reset to pseudo color mode on power up. 1 0 1 pll parameter there are 16 pll parameter registers accessible as indexed by read/write registers. parameter registers 0f and 0d-00 are two bytes long and 0e is one byte long. register 0e is a control reg- ister. the bits of this register include clock select and enable functions, the rest contain pll frequency parameters. after writ- ing the start index address in the pll address register, these reg- isters can be accessed in successive two (or one) bytes. the address register auto increments after one (0e) or two bytes to access the entire register internal registers rs2 rs1 rs0 register name description (all registers can be written to and read from) idt? / ics? 16-bit integrated clock-lut-dac ICS5342 5 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 6 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 6 note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sec- tions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect de- vice reliability. electrical characteristics dc characteristics (note: j) parameter symbol min. max. units test conditions positive supply voltage v dd 4.75 5.25 v input logic ??voltage v ih 2.0 v dd +0.5 v input logic ??voltage v il ?0.5 0.8 v reference current i ref ?.0 ?0 ma reference voltage v ref 1.10 1.35 v digital input current i in 10 m av dd =max, v dd 3 v in 3 gnd off-state digital output current i oz 50 m av dd = max, v dd 3 v in 3 gnd average power supply current i dd 250 ma i o = max, digital outputs unloaded dacs in power down mode i dacoff 50 ma no palette access sense logic ? v ohs 2.4 v i o = -0.4ma sense logic ? v ols 0.4 v i o = 0.4ma clock logic ? v ohc 2.4 v i o = -12.0ma clock logic ? v olc 0.4 v i o = 12.0ma logic ? v oh 2.4 v i o = -3.2ma, note k logic ? v ol 0.4 v i o = 3.2ma, note k xin input clock rise time xclk r* 15 ns ttl levels xin input clock fall time xclk f* 15 ns ttl levels frequency change of clk0 and clk1 over supply and tempera- ture fd 0.05 % with respect to typical frequency power supply voltage........................................................7 v voltage on any other pin.............. gnd 0.5v to v dd + 0.5v temperature under bias ................................ ?40? c to 85? c storage temperature................................... ?65? c to 150? c dc digital output current ......................................... 25 ma analog output current ................................................ 45 ma reference current...................................................... ?5 ma power dissipation ......................................................... 1.0 w absolute maximum ratings
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 7 * characterized values only dac characteristics parameter symbol min max units test conditions maximum output voltage v o (max) 1.5 v i o 10 ma maximum output current i o (max) 21 ma v o 1v full scale error 5 % note a, b dac to dac correlation 2 % note b integral linearity, 6-bit 0.5 lsb note b integral linearity, 8-bit 1 lsb note b full scale settling time*, 6-bit 28 ns note c full scale settling time*, 8-bit 20 ns note c rise time (10% to 90%)* 6 ns note c glitch energy* 200 pv.s note c pll ac characteristics parameter symbol min max units test conditions clock 0 operating range f0 25 135 mhz clock 1 operating range f 1 25 135 mhz output clocks rise time* t r 3 ns 25 pf load, ttl levels output clocks fall time* t r 3 ns 25 pf load, ttl levels duty cycle* d t 40/60 60/40 % jitter, one sigma* j 1s 130 ps ps jitter, absolute* j abs -300 ps 300 ps ps input reference frequency* f ref 5 25 mhz typically 14.318 mhz ac electrical characteristics (note: j) parameter symbol 80 mhz 110mhz 135mhz units test conditions min max min max min max pclk period t chch 12.5 9.09 7.4 ns pclk jitter d t chch * 2.5 +2.5 % note d pclk width low t clch 5 3.6 3 ns pclk width high t chcl 5 3.6 3 ns pixel word setup time t pvch 332ns note e pixel word hold time t chpx 321ns note e blank* setup time t bvch 332ns note e blank* hold time t chbx 321ns note e pclk to valid dac output t chav * 20 20 20 ns note f idt? / ics? 16-bit integrated clock-lut-dac ICS5342 7
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 8 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 8 differential output delay d t chav 2 2 2 ns note g wr* pulse width low t wlwh 50 50 50 ns rd* pulse width low t rlrh 50 50 50 ns register select setup time t svwl 10 10 10 ns write cycle register select setup time t svrl 10 10 10 ns read cycle register select hold time t wlsx 10 10 10 ns write cycle register select hold time t rlsx 10 10 10 ns read cycle wr* data setup time t dvwh 10 10 10 ns wr* data hold time t whdx 10 10 10 ns output turn-on delay t rlqx 555ns rd* enable access time t rlqv 40 40 40 ns output hold time t rhqx 333ns output turn-off delay t rhqz 20 20 20 ns note h successive write inter- val t whwl1 4 (t chch ) 4 (t chch ) 4 (t chch ) cycle note i wr* followed by read interval t whrl1 4 (t chch ) 4 (t chch ) 4 (t chch ) cycle note i successive read interval t rhrl1 4 (t chch) 4 (t chch ) 4 (t chch ) cycle note i rd* followed by write interval t rhwl1 4 (t chch) 4 (t chch ) 4 (t chch ) cycle note i wr* after color write t whwl2 4 (t chch) 4 (t chch ) 4 (t chch ) cycle note i rd* after color write t whrl2 4 (t chch ) 4 (t chch ) 4 (t chch) cycle note i rd* after color read t rhrl2 8 (t chch ) 8 (t chch ) 8 (t chch) cycle note i wr* after color read t rhwl2 8 (t chch ) 8 (t chch ) 8 (t chch ) cycle note i rd* after read address write t whrl3 8 (t chch) 8 (t chch ) 8 (t chch ) cycle note i sense* output delay t sod 111 m s xin input clock rise time t xclkr * 15 15 15 ns ttl levels ac electrical characteristics (note: j) parameter symbol 80 mhz 110mhz 135mhz units test conditions min max min max min max
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 9 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 9 * characterized values only xin input clock fall time t xclkf * 15 15 15 ns ttl levels ac electrical characteristics (note: j) parameter symbol 80 mhz 110mhz 135mhz units test conditions min max min max min max notes: a. full scale error is derived from design equation: {[(f.s.i out )r l ?2.1(i ref )r l ] / [2.1(i ref )r l ]} 100% v black level = 0 v f.s.i out = actual full scale measured output b. r= 37.5 w , i ref = ?8.88 ma c. z i = 37.5 w + 30 pf, i ref = ?8.88 ma d. this parameter is the allowed pixel clock frequency variation. it does not permit the pixel clock period to vary outside the minimum values for pixel clock (t chch ) period. e. the color palettes pixel address is required to be a valid logic level with the appropriate setup and hold times at each rising edge of pclk (this requirement includes the blanking period). f. the output delay is measured from the 50% point of the rising edge of clock to the valid analog output. a valid analog output is de?ed when the analog signal is halfway between its successive values. g. this applies to different analog outputs on the same device. h. measured at 200 mv from steady state output voltage. i. this parameter allows synchronization between opera- tions on the microprocessor interface and the pixel stream being processed by the color palette. j. the following speci?ations apply for v dd = +5v 0.5v, gnd=0. operating temperature = 0?c to 70?c. k. except for sense pin. ac test conditions input pulse levels...................................................v dd to 3v input rise and fall times (10% to 90%) ............................ 3 ns digital input timing reference level ............................... 1.5 v digital output timing reference level .............0.8 v and 2.4 v capacitance c 1 digital input ............................................................... 7 pf c 0 digital output ............................................................. 7 pf c 0a analog output ........................................................ 10 pf clock load general operation the ICS5342 gendac is intended for use as the analog out- put stage of raster scan video systems. it contains a high- speed random access memory of 256 x 18-bit words, three 6/8-bit high-speed dacs, a microprocessor/graphic control- ler interface, a pixel word mask, on-chip comparators, and two user programmable frequency generators. an externally generated blank* signal can be applied to pin 7 of the ICS5342. this signal acts on all three of the ana- log outputs. the blank* signal is delayed internally so that it appears with the correct relationship to the pixel bit stream at the analog outputs. a pixel word mask is included to allow the incoming pixel address to be masked. this permits rapid changes to the effec- clk 25 pf 1.4v 200 w 5342_03
ICS5342 gendac 10 tive contents of the color palette ram to facilitate such oper- ations as animation and flashing objects. operations on the contents of the mask register can also be totally asynchronous to the pixel stream. the ICS5342 also includes dual pll frequency generators providing a video clock (clk0) and a memory clock (clk1), both generated from a single 14.318 mhz crystal. there are eight selectable clk0 frequencies. all eight are programma- ble. there are two selectable and programmable clk1 fre- quencies (fa, fb). default values (shown in tables: ?ideo clock default frequency registers,?and ?emory clock default frequency registers? are loaded into the appropriate registers on power up. video path the gendac supports nine different video modes and is de- termined by bits 4-7 of the command register. the default mode is the 8-bit pseudo color mode. the other modes are the bypass 15-bit, 16-bit and 24 bit true color modes in 8-bit and 16-bit interface, and the 16-bit pseudo color (2:1) mode with 2x clock. the 24-bit true color has sparse and packed modes. pseudo color 8-bit interface in this mode, pixel address, p7-p0 and blank* inputs are sampled on the rising edge of the clock (pclk) and any change appears at the analog outputs after three succeeding rising edges of the pclk. the dac output depends on the data in the color palette ram. 16-bit interface in this mode, pixel address, p15-p0 and blank* inputs are sampled on the rising edge of the clock (pclk) and any change appears at the analog outputs after three succeeding rising edges of the 2 x iclk. iclk frequency is twice the pclk input frequency. the dac output depends on the data in the color palette ram. bypass mode the gendac supports seven different bypass modes: three for byte transfers and four for word transfers. in these modes, the address pins p0-p15 represent color data that is applied directly to the dac. the internal look-up table ram is ig- nored. during byte transfers, the p8-p15 inputs are?on't care.?data is always latched on the rising edge of pclk. byte or word framing is internally synchronized with the ris- ing edge of blank*. dac outputs the outputs of the dacs are designed to be capable of pro- ducing 0.7 v peak white amplitude with an i ref of 8.88 ma when driving a doubly-terminated 75 w load. this corre- sponds to an effective dac output load (r effective ) of 37.5 w . the formula for calculating i ref with various peak white voltage/output loading combinations is given below: note that for all values of i ref and output loading: the reference current i ref is determined by the reference voltage v ref and the value of the resistor connected to r set pin. v ref can be the internal band gap reference voltage or can be overridden by an external voltage. in both cases: dac setup the blank* input to the gendac acts on all three of the dac outputs. when the blank* input is low, the dacs are powered down. the connection between the dac outputs of the ICS5342 and the rgb inputs of the monitor should be regarded as a trans- mission line. impedance changes along the transmission line will result in the reflection of part of the video signal back along the line. these reflections may result in a degradation of the picture displayed by the monitor. rf techniques should be observed to ensure good fidelity. the pcb trace connecting the gendac to the off-board con- nector should be sized to form a transmission line of the cor- rect impedance. correctly matched rf connectors should be used for connection from the pcb to the monitor coaxial cable and from that cable to the monitor. there are two recommended methods of dac termination: double termination and buffered signal. each is described be- low with its relative merits. i ref v peakwhite 2.1 r effective -------------------------------------------- - = v blacklevel 0 = i ref v ref r set = dac v ref ( int ) i ref v ref (ext) 33 34 36 38 39 r set r eff i ref 5342_04 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 10 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 11 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 11 double termination (figure 1) for this termination scheme, a load resistor is placed at both the dac output and the monitor input. the resistor values should be equal to the characteristic impedance of the line. double termination of the dac output allows both ends of the transmission line between the dac outputs and the monitor inputs to be correctly matched.the result should be an ideal reflection-free system. this arrangement is relatively tolerant of variations in trans- mission line impedance (e.g. a mismatched connector) since no reflections occur from either end of the line. a doubly ter- minated dac output will rise faster than any singly terminat- ed output because the rise time of the dac outputs is dependent on the rc time constant of the load. double termination if the gendac drives large capacitive loads (for instance long cable runs), it may be necessary to buffer the dac out- puts. the buffer will have a relatively high input impedance. the connection between the dac outputs and the buffer in- puts should also be considered as a transmission line. the buffer output will have a relatively low impedance. it should be matched to the transmission line between it and the monitor with a series terminating resistor. the transmission line should be terminated at the monitor. buffered signal sense output the gendac contains three comparators, one for each of the dac output r, g and b lines. the reference voltage to the comparators is proportional to the v ref (internal or external) and is typically 0.330 for v ref =1.235 volts. the sense* pin will be driven low when any analog video output is above 0.385 mv. sense* output will be high when all analog out- puts are below 275 mv. this signal is used to detect the type of (or lack of) monitor connected to the system. pll clock the ICS5342 has dual pll frequency generators for generat- ing the video clock (clk0) and memory clock (clk1) need- ed for graphics subsystems. both of these clocks are generated from a single 14.318 mhz crystal or they can be driven from an external clock source. the chip includes the capacitors for the crystal and all of the components needed for the pll loop filters, minimizing board component count. there are eight possible video clock, clk0, frequencies (f0- f7) which can be selected by the external pins cs1-cs0. all clocks are software selectable by setting a bit in the pll con- trol register. frequencies f0-f7 can be programmed for any frequency by writing appropriate parameter values to the pll parameter registers. the default frequencies on power up are commonly used video frequencies (see table ?ideo clock default frequency registers?. at power up, the frequencies can be selected by pins cs2-cs0. there are two programma- ble memory clock frequencies (fa, fb). on power up this fre- quency defaults to the frequency given in the table: ?emoryclock default frequency registers.?the memory clock transition between frequencies is smooth and glitch free if the n2 pll parameter is not changed from its previous set- ting. * with 14.318 mhz input. r load r load monitor ICS5342 ground ground 5342_05 r t r load monitor ICS5342 ground ground r s 5342_06 video clock (clk0) default frequency register * fn vclk (mhz) m & n code comments f0 25.175 7d 50 vga0 (vga graphics) f1 28.322 55 49 vga1 (vga text) f2 31.500 2a 43 vesa 640 x 480 @72 hz f3 36.00 77 4a vesa 800 x 600 @56 hz f4 40.00 79 49 vesa 800 x 600 @60 hz f5 44.889 6f 47 1024 x 768 @43 hz inter- laced f6 65.00 74 2b 1024 x 768 @ 60 hz, 640 x 480 hi-color @ 72 hz f7 75.00 71 29 vesa 1024 x 768 @ 70 hz, true color 640 x 480
ICS5342 gendac 12 microprocessor interface below are listed the six microprocessor interface registers within the ICS5342, and the register addresses through which they can be accessed. asynchronous access to microprocessor interface accesses to all registers may occur without reference to the high speed timing of the pixel bit stream being processed by the gendac. data transfers between the color palette ram and the color value register, as well as modifications to the pixel mask register, are synchronized to the pixel clock by internal logic. this is done in the period between micropro- cessor interface accesses. thus, various minimum periods are specified between microprocessor interface accesses to allow the appropriate transfers or modifications to take place. ac- cess to pll address, pll parameter and to the command reg- ister are asynchronous to the pixel clock. the contents of the palette ram can be accessed via the col- or value register and the pixel address registers. writing to the color palette ram to set a new color definition, a value specifying a location in the color palette ram is first written to the write mode pixel address register. the values for the red, green and blue inten- sities are then written in succession to the color value regis- ter. after the blue data is written to the color value register, the new color definition is transferred to the ram, and the pixel address register is automatically incremented. writing new color definitions to a set of consecutive locations in the ram is made easy by this auto-incrementing feature. first, the start address of the set of locations is written to the write mode pixel address register, followed by the color def- inition of that location. since the address is incremented after each color definition is written, the color definition for the next location can be written immediately. thus, the color def- initions for consecutive locations can be written sequentially to the color value register without re-writing to the pixel ad- dress register each time. reading from the ram to read a color definition, a value specifying the location in the palette ram to be read is written to the read mode pixel address register. after this value has been written, the con- tents of the location specified are copied to the color value register, and the pixel address register automatically incre- ments. the red, green and blue intensity values can be read by a se- quence of three reads from the color value register. after the blue value has been read, the location in the ram currently specified by the pixel address register is copied to the color value register and the pixel address again automatically in- crements. a set of color values in consecutive locations can be read simply by writing the start address of the set to the read mode pixel address register and then sequentially reading the color values for each location in the set. whenever the pixel address register is updated, any unfinished color definition read or write is aborted and a new one may begin. the pixel mask register the pixel address used to access the ram through the pixel interface is the result of the bitwise and-ing of the incoming pixel address and of the contents of the pixel mask register. this pixel masking process can be used to alter the displayed colors without altering the video memory or the ram con- tents. by partitioning the color definitions by one or more bits in the pixel address, such effects as rapid animation, overlays, and flashing objects can be produced. the pixel mask register is independent of the pixel address and color value registers. the command register the command register is used to select the various gendac color modes and to set the power down mode. on power up this register defaults to an 8-bit pseudo color mode. this reg- ister can be accessed by control pins rs2-rs0, or by a special sequence of events for graphics subsystems that do not have the control signal rs2. for graphic systems that do not have rs2, this pin is tied low and an internal flag (hf: hidden flag) is set when the pixel mask register is read four times memory clock (clk1) default frequency register fn mclk (mhz) m & n code comments fa 45.00 4f 2b memory and gui sub- system clock fb 55.00 79 2e memory and gui sub- system clock microprocessor interface registers rs2 rs1 rs0 register name 0 0 0 pixel address (write mode) 0 1 1 pixel address (read mode) 0 0 1 color value 0 1 0 pixel mask 1 0 0 pll address (write mode) 1 0 1 pll parameter 1 1 0 command 1 1 1 pll address (read mode) 0/hf 1 0 command register accessed by (hidden) ?g after special sequence of events. idt? / ics? 16-bit integrated clock-lut-dac ICS5342 12 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 13 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 13 consecutively. once the flag is set, the following read or write to the pixel mask register is directed to the command register. the flag is reset for read or write to any register other than the pixel mask register. the sequence has to be repeated for any subsequent access to the command register. the pll parameter register the clk0 and clk1 of the ICS5342 can be programmed for different frequencies by writing different values to the pll parameter register bank. there are eight registers in the pa- rameter register; seven are two bytes long and one (0e) is one byte long. writing to the pll parameter register to write the pll parameter data, the corresponding address location is first written to the pll address register. for soft- ware compatibility with other chips, two address registers are defined: the write mode pll address register and the read mode pll address register. these are actually a single read/ write register in the ICS5342. the next pll parameter write will be directed to the first byte of the address location speci- fied by the pll address register. the next write to the param- eter register will automatically be to the second byte of this register. at the end of the second write the address is automat- ically incremented. for the one byte ?e?register the address location is incremented after the first byte write. if this fre- quency is selected while programming, the output frequency will change at the end of the second write. reading the pll parameter register to read one of the registers of the pll parameter register the address value corresponding to the location is first written to the pll address register. the next pll parameter read will be directed to the first byte of the address location pointed by this index register. a next read of the parameter register will auto- matically be the second byte of this register. at the end of the second read, the address location is automatically increment- ed. the address register (0e) is incremented after the first byte read.
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 14 functional description this section describes the register address and bit definition for the ramdac and the frequency synthesizer sections. color palette command register (rs0-rs2 = 011) (rs0-rs1 = 01 with hidden flag) by setting bits 4 and 7-5 in the command register the ICS5342 can be programmed for different color modes and the dacs can be turned off for low power operation. bit 7-4 color mode select - these three bits select the color mode of ramdac operation as shown in the following table ?olor mode select?(default is 0 at power up). bit 3-2 (reserved) set to ? for future compatibility. bit 1 test mode - when bit 1 is set checksum accumu- lation is enabled. if bit 0 is also set the oscillator and synthesizers are turned off for minimum noise. bit 0 power down mode of ramdac - when this bit is set to 0 (default is 0), the device operates nor- mally. if this bit is set to 1, the power and clock to the color palette ram and dacs are turned off. the data in the color palette ram are still preserved. the cpu can access without loss of data by internal automatic clock start/stop con- trol. the dac outputs become the same as blank* (sync) level output during power down mode. this bit does not affect the pll clock syn- thesizer function unless test mode is enabled. command registers 7654 3 2 1 0 2103 reserved = 0 test mode snooze color mode select 8-bit interface mode number cm3 (cr4) cm2 (cr7) cm1 (cr6) cm0 (cr5) color mode clock cycles/ pixel bits 0 0000 8-bit pseudo color with palette (default) 1 1 0001 15-bit direct color with bypass (hi-color) 2 3 0010 24-bit true color with bypass (true color) 3 2 0011 16-bit direct color with bypass (xga) 2 1 0100 15-bit direct color with bypass (hi-color) 2 1 0101 15-bit direct color with bypass (hi-color) 2 2 0110 15-bit direct color with bypass (hi-color) 2 3 0111 24-bit true color with bypass (true color) 3 16-bit interface mode number cm3 (cr4) cm2 (cr7) cm1 (cr6) cm0 (cr5) color mode clock cycles/ pixel bits 4 1000 multiplexed 16-bit pseudo color with palette 1/2 5 1001 15-bit direct color with bypass (hi-color) 1 6 1010 16-bit direct color with bypass (xga 1 7 1011 24-bit true color with bypass (true color) 2 8 1100 24-bit packed true color with bypass (true-color) 3/2 1101 reserved 1110 reserved 1111 reserved idt? / ics? 16-bit integrated clock-lut-dac ICS5342 14
ICS5342 gendac 15 color modes the nine selectable color modes are described here. four are eight-bit and five are 16-bit wide pixel input. color modes 0-3 are 8-bit interfaces with bits p0-p7; p8-p15 are ?on? care bits. mode 0 : 8-bit pseudo color (one clock per pixel). this mode is the 8-bit per pixel pseudo color mode. in this mode, inputs p0-p7 are the pixel address for the color palette ram and are latched on the rising edge of every pclk. this is the default mode on power up and it is selected by setting bits cr7-cr4 to 0000. mode 1: (15-bit per color bypass hi-color mode). this mode is the 15-bit per pixel bypass mode. in this mode, inputs p0-p7 are the color data and are input directly to the dac, by- passing the color palette. the two bytes of data are latched in two successive pclk rising edges. ICS5342 supports only the two clock mode and does not support the mode where the data are latched on the rising and the falling edges. for com- patibility, the 15/16 one clock modes are selected as two clock modes in this chip. the low-byte, high byte synchronization is internally done by the rising edge of blank*. each color is 5-bit wide and is packed into two bytes as shown below. this mode can be selected by setting bits cr7-cr4 to 0010, 1000 or 1010. 3lsb = set to zero mode 2: (16-bit per pixel bypass xga mode). this mode is the 16-bit per pixel bypass mode and the p0-p7 inputs to go to the dac directly, bypassing the color palette. the 2 bytes data is latched on two successive rising edges and the low- byte, high-byte synchronization is internally done by the ris- ing edge of blank*. in this mode, blue and red colors are 5 bits wide and green is 6 bits wide. the 2 bytes of data are packed as shown below. this mode can be selected by setting bits cr7-cr4 to 0110 or 1100. 2lsb = set to zero (green) 3lsb = set to zero (blue, red) mode 3: (24-bit per pixel true color mode). this mode is the 24-bit per pixel bypass mode. the three bytes of data are latched on three successive pclk edges and the first byte is synchronized by the rising edge of blank*. in this mode, each of the colors are 8-bit wide and the dac is an 8-bit wide dac. the first byte is blue followed by green and red. this mode can be selected by setting bits cr7-cr4 to 0100 or 1110. the dac outputs changes every three cycles and the pipeline delay from the first byte to output is five cycles. 16 bit color modes modes 4 - 8 use the 16-bit pixel interface. mode 4: (8-bit pseudo color two pixels per clock) in this mode, inputs p0-p15 are latched on the rising edge of every pclk. p0-7 and p8-p15 are used for successive addresses for the palette ram using an internal clock (iclk) that runs at twice the pclk frequency. the dac outputs change twice for every pclk and the pipeline delay from the first word to output is one and one half cycles. this mode can be selected by setting bits cr7-cr4 to 0001. mode 5: (16-bit pixel interface, 15-bit per color bypass hi- color mode) in this mode inputs p0-p15 are the color data and are input directly to the dac, bypassing the color palette. the data is latched by the rising edge of pclk and is pipe- 8-bit pseudo color - mode 0 pixel byte p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0 76543210 lut address 15-bit color - mode 1 second byte first byte pppppppppppppppp 7654321076543210 x765437654376543 x red green blue 16-bit color - mode 2 second byte first byte pppppppppppppppp 7654321076543210 7654376543276543 red green blue 24-bit color - mode 3 third byte second byte first byte pppppppppppppppppppppppp 765432107654321076543210 765432107654321076543210 red green blue multiplexed 8-bit pseudo color word - mode 4 pixel word pppppppp pppppppp 11111198 76543210 543210 76543210 76543210 2nd pixel address 1st pixel address idt? / ics? 16-bit integrated clock-lut-dac ICS5342 15 ICS5342 16-bit integrated clock-lut-dac tsd
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 16 lined to the dac. the pipeline delay from input to dac out- put is three pclk cycles. each color is 5-bit wide as shown below. this mode is selected by setting bits cr7-cr4 to 0011. 3lsb = set to zero mode 6: (16-bit pixel interface, 16-bit per color bypass xga mode) in this mode input p0-p15 are the color data and are in- put directly to the dac bypassing the color palette. the data is latched by the rising edge of pclk and is pipelined to the dac. the pipeline delay, from input to dac output, is three pclk cycles. in this mode blue and red colors are 5 bits wide, and green is 6 bits wide. this mode is selected by set- ting bits cr7-cr4 to 0101. 2lsb = set to zero (green) 3lsb = set to zero (blue, red) mode 7: (16-bit pixel interface, 24-bit per color bypass true color mode) in this mode inputs p0-p15 are the color data and are input directly to the dac bypassing the color pal- ette. two words are latched on two successive rising edge of pclk to form the 24-bit dac input. the first word and the lower byte of the second word form the 24-bit pixel input to the dac. the higher byte of the second word is ignored. the low and high word synchronization is internally done by the rising edge of blank*. the pipeline delay from latching of the first word to dac output is 4 cycles and each pixel is two pixel clocks wide. in this mode, each of the colors are 8-bits wide and the dac is 8-bit wide dac. the first byte is blue followed by green and red. this mode is selected by setting bits cr7-cr4 to 0111. mode 8: (16-bit pixel interface packed 24-bit per color bypass true color mode) in this mode inputs p0-p15 are the color data and are input directly to the dac bypassing the color pal- ette. three words are latched on three successive rising edges of pclk to form two successive 24-bit dac inputs. the 16- bit first word and the lower byte of the second word from the first 24-bit pixel input and the second byte of the second word with the 16 bits of the third word from the second 24-bit pixel input. this cycle repeats every three cycles. the three-word synchronization is internally done by the rising edge of blank*. the pipeline delay from latching of first word to dac output is 3 1/2 cycles and each of the colors are 8-bits wide and dac is 8-bit wide dac. the first byte is blue fol- lowed by green and red. this mode is selected by setting bits cr7-cr4 to 1001. 15-bit color word - mode 5 pixel word pppppppppppppppp 1111119876543210 543210 x765547654376543 x red green blue 16-bit color word - mode 6 pixel word pppppppppppppppp 1111119876543210 543210 7654376543276543 red green blue 24-bit direct color word - mode 7 first word pppppppppppppppp 1111119876543210 543210 7654321076543210 green blue second word pppppppppppppppp 1111119876543210 543210 xxxxxxxx7 6 5 43210 ignored red packed 24-bit word - mode 8 1st dac cycle second word first word pppppppppppppppppppppppp 765432101111119876543210 765432105432109876543210 red green blue 2nd dac cycle third word second word pppppppp pppppppppppppppp 11111198765 4321011111198 543210 5 43210 76543210765 4321076543210 red green blue idt? / ics? 16-bit integrated clock-lut-dac ICS5342 16
ICS5342 gendac 17 frequency generators the ICS5342 clock synthesizer can be reprogrammed through the microprocessor interface for any set of frequencies. this is done by writing appropriate values to the pll parameter register bank (see following table: ?ll parameter regis- ters?. pll address registers the address of the parameter register is written to the pll ad- dress registers before accessing the parameter register. this register is accessed by register select pins rs2-rs0 = 100 or 111. pll parameters registers there are sixteen registers in the pll parameter register (ta- ble 5). registers 00 to 07 are for the clk0 selectable frequen- cy list, register 0a and 0b for clk1 programmable frequency and register 0e is the pll control register. pll control register bits in this register determine internal or external clk0 se- lect. bit 7,6, 3 reserved, set to ? for future compatibility. bit 5 enable internal clock select (incs) for clk0. when this bit is set to 1, the clk0 output fre- quency is selected by bits 2-0 in this register. external pins cs0-cs2 are ignored. bit 4 clk1 select when this bit is set to 0, fa is selected. when it is set to 1, fb is selected. the default is 0 for fa selected at power up. bit 2 - 0 internal clock select for clk0 (incs). these three bits select the clk0 output frequency if bit 5 of this register is on. they are interpreted as an octal number, n, that selects fn. default selects f0. pll data registers the clk0 and clk1 output frequency is determined by the parameter values in this register. these are two-byte registers; the first byte is the m-byte and the second the n-byte. m-byte pll parameter input the m-byte has a 7-bit value (1-127) which is the feedback divider of the pll. n-byte pll parameter input the n-byte contains two parameter values. n1 sets a 5-bit val- ue (1-31) for the input pre scalar and n2 is a 2-bit code for se- lecting 1, 2, 4, or 8 post divide clock output. pll address register 76543210 pll register adr. 76543210 pll parameter registers index r/w register 00 r/w clk0 f0 pll parameters (2 bytes) 01 r/w clk0 f1 pll parameters (2 bytes) 02 r/w clk0 f2 pll parameters (2 bytes) 03 r/w clk0 f3 pll parameters (2 bytes) 04 r/w clk0 f4 pll parameters (2 bytes) 05 r/w clk0 f5 pll parameters (2 bytes) 06 r/w clk0 f6 pll parameters (2 bytes) 07 r/w clk0 f7 pll parameters (2 bytes) 08 r/- (reserved) = 0 (2 bytes 09 r/w clk1 fa pll (2 bytes) 0a r/w clk1 fb pll (2 bytes) 0b r/w (reserved) = 0 (2 bytes 0c r/- (reserved) = 0 (2 bytes) 0d r/- (reserved) = 0 (2 bytes) 0e r/w pll control register (1-byte) 0f r/- (reserved) = 0 (2 bytes) pll control register 76543210 (rv)= 0 (rv)= 0 enbl incs clk1 sel (rv)= 0 internal select xxx m-byte 7 6543210 reserved = 0 m-divider value xxxxxxx n-byte pll parameter input 7 6543210 reserved = 0 n2 - code n1-divider value xxxxxxx idt? / ics? 16-bit integrated clock-lut-dac ICS5342 17 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 18 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 18 n2 post divide code if mode 4 is set in the command register, cr7-cr4 bits equal 0001, and the n2 code must be 10. the block diagram of the pll clock synthesizer is shown in figure 3. based on the m and n values, the output frequency of the clocks is given by the following equation: m and n values should be programmed such that the frequen- cy of the vc0 is within the optimum range for duty cycle, jit- ter and glitch free transition. optimum duty cycle is achieved by programming n2 for values greater than unity. see the next section for a programming example. programming example suppose an output frequency of 25.175 mhz is desired. the reference crystal is 14.318 mhz. the vco should be targeted to run in the 60 to 270 mhz range, so choosing a post divide of 4 gives a vco frequency of: from the table in the previous section, we find n2 = 2 substi- tuting f ref = 14.318 and 2 n2 = 4 into the clock frequency equation in the previous section: by trial and error: m + 2 = 127 m = 125 n1 + 2 = 18 n1 = 16 so the registers are: m = 125d = 1 1 1 1 1 0 1 b n = 0 & n2 code & n1 = 0 & 1 0 & 1 0 0 0 0 n = 0 1 0 1 0 0 0 0 b additional information on programming the frequency generator section of the gendac when programming the gendac pll parameter registers, there are many possible combinations of parameters which will give the correct output frequency. some combinations are better than others, however. here is a method to determine how the registers need to be set: the key guidelines come from the operation of the phase locked loop, which has the following restrictions: 1. this refers to the input refer- ence frequency. most users simply connect a 14.318 mhz crystal to the crystal inputs, so this is not a prob- lem. 2. this is the frequency input to the phase detector. 3. this is the vco frequency. in general, the vco should run as fast as pos- sible, because it has lower jitter at higher frequencies. also, running the vco at multiples of the desired fre- quency allows the use of output divides, which tends to improve the duty cycle. 4. this is the output fre- quency. these rules lead to the following procedure for determining the pll parameters, assuming rules 1 and 4 are satisfied. a. determine the value of n2 (either 1, 2, 4 or 8) by select- ing the highest value of n2, which satis?s the condition n2* fclk < 270 mhz. b. calculate: c. now (m+2) and (n1+2) must be found by trial and error. with a 14.318 mhz reference frequency, there will gen- erally be a small output frequency error due to the reso- lution limit of (m+2) and (n1+2). for a given frequency tolerance, several different (m+2) and (n1+2) combina- tions can usually be found. usually, a few minutes trying n2 post divide code n2 code divider 00 1 01 2 10 4 11 8 f out m 2 + () f ref 2 n 2 n 12 + () -------------------------------- - = 4 25.175 101.021 mhz = 25.175 14.318 ---------------- 4 ? m 2 + n 12 + ---------------- - = 2 mhz f ref 25 mhz << 600khz f ref n 12 + ---------------- - 8 mhz 60mhz m 2 + n 12 + ---------------- - f ref ? 270 mhz f clk 0 and f clk 1 35 mhz m 2 + n 12 + ---------------- - 2 n 2 f out f ref ----------------------- =
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 19 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 19 out numbers with a calculator will produce a workable combination. multiplying possible values of (n1+2) by the desired ratio will indicate approximately the value of m. this method is shown in the example below. a pro- gram could be written to try all possible combinations of (m+2) and (n1+2) (3937 possible combinations). dis- card those outside the error band, and select from those remaining by giving preference to ratios which use lower values of (m+2). lower values of (m+2) and (n1+2) provide better noise rejection in the phase locked loop. example: suppose you have a 14.318 mhz reference crystal and want an output frequency of 66 mhz. you want to limit the vco frequency to 240 mhz and have an error of no great- er than 0.5%. what are the values of the pll data registers? a. 66*8 = 528 > 250 ?vco speed too high 66*4 = 264 > 250 ?vco speed too high 66*2 = 132 < 250 ?vco speed ok, n2 = 2, n2 code = 01 from the post divide code table in the pll data registers section. b. 132/14.31818 = 9.219 this is the desired frequency mul- tiplication ratio. c. setting (n1+2) = 3,4, ...12, 13 and performing some simple calculations yields the following table: (note that n1 cannot be 0). the ratio 83/9 is closest. thus: (n2+2) = 9 n2=7 (m+2) = 83 m = 81 the m-byte pll parameter word is simply 81 in binary, plus bit 7 (which must be set to 0), or 01010001. the n-byte pll parameter word is n2 code (01) concatenated with 5 bits of n2 in binary (00111), or 00100111. once again, bit 7 must be zero. the combination with the least frequency error was chosen, but several other combinations are within the 0.5% tolerance. because the lowest value of (m+2) offers the best damping, the 37/4 combination will have the best power supply rejec- tion. this results in lower jitter due to external noise. example calculation of pll data register values (n1 + 2) (n1 + 2) *9.219 rounded (=m + 2) actual ratio percent error 3 27.657 28 9.33 -1.23 4 36.876 37 9.25 -0.34 5 46.095 46 9.20 0.21 6 55.314 55 9.17 0.57 7 64.533 65 9.29 -0.72 8 73.752 74 9.25 -0.34 9 82.971 83 9.22 -0.03 10 92.19 92 9.20 0.21 11 101.409 101 9.18 0.40 12 110.628 111 9.25 -0.34 13 119.847 120 9.23 -0.13
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 20 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 20 pll clock synthesizer block diagram video clock selection table external select (internal select pll control register) clk 0 frequency cs2 cs1 cs0 bit 2 bit 1 bit 0 000000f0 001001f1 010010f2 011011f3 100100f4 101101f5 110110f6 111111f7 1/(n1+2) f ref phase detect charge pump loop filter vco n2 counter 1/(m1+2) 5342_07
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 21 system timing - pseudo color, mode 0 detailed timing speci?ations ?pseudo color, mode 0 pclk 5342_8 blank p0-p7 red green blue abc d efgh i j k a f f f g g g b c c c b b a a blank blank blank e f gh i j k a a a b b b c c c blank blank blank f f f g g g t pvch plck blank red blue t chav t chav t chav t chbx t bvch t clpx t chcl t chch t clch 5342_09 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 21
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 22 system timing bypass- 15(5/6/5) modes 1,2 system timing bypass true color 24 (8,8,8) mode 3 pclk 1 low byte a high byte a low byte b high byte b 5342_10 234 a b b b a a 56 7 blank p0-p7 dac-rd dac-gr dac-bl pclk 1 25ns 0ns 50ns 75ns 100ns 125ns 5342_11 150ns 23456789 a a bl gr rd bl gr rd b b c c blank p0-p7 dac-bl dac-gr dac-rd idt? / ics? 16-bit integrated clock-lut-dac ICS5342 22
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 23 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 23 system timing - 8-bit pseudo color, mode 4 system timing - 16-bit color, mode 5(5,5,5) and 6((5,6,5) 1 1 1 5342_12 a aceg jl n bdfhkm p k k l j j j l l b c c c d d d b b a a blank blank blank pclk iclk blank p0-p7 p8-p15 red green blue 1 1 1 1 pclk 5342_13 blank p0-p7 red green blue 1 a a a a b b b b blank blank blank cd efgh 2 3 4 5 6 7
ICS5342 gendac 24 system timing - 16-bit direct true color, mode 7 system timing - 24-bit packed color, mode 8 pclk 5342_14 blank p0-p7 red green blue 1 ab ag ar -- bb bg br -- cb cg cr -- db dg dr -- a a a blank blank blank 2 3 4 5 6 7 pclk 5342_15 blank p0-p7 red green blue 1 al am au bl bm bu cl cm cu dl dm du el em eu fl fm fu gl gm a b b b a a blank blank blank blank blank blank 2 3 4 5 6 7 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 24 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 25 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 25 read-write timing basic write cycle timing t wlwh t svwl t wlsx t dvwh t whdx t rlrh t svrl t rlsx t rlqv t rhqx t rlqx t rhqz basic read cycle timing 5342_16 rs0-rs1 d0-d7 rd* wr* rs0-rs1 d0-d7 wr* rd* rs0 wr* rd* write to pixel mask register followed by write write to pixel mask register followed by read read from pixel or pixel address register (read or write) followed by read 5342_17 rs1 t whwl1 t whrl1 read from pixel or pixel address register (read or write) followed by write t rhrl1 t rhwl1
ICS5342 gendac 26 write and read back pixel address register (read mode) write and read back pixel address register (write mode) wit drdbkpiladd rit(rdmd) 5342_18 rs0 rs1 rs2 d0-d7 wr* rd* t whrl1 address address+1 5342_19 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 address address idt? / ics? 16-bit integrated clock-lut-dac ICS5342 26 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 27 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 27 read color value then pixel address register (read mode) color value write followed by any read 5342_20 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 t rhrl1 t rhrl1 t rhrl2 address green red blue address+2 wr* rd* t whwl1 t whwl1 t whwl1 t whrl2 5342_21 rs1 rs2 d0-d7 address green red blue rs0
ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 28 color value write followed by any write color value read followed by any read 5342_22 rs0 rs1 rs2 d0-d7 wr* rd* t whwl1 t whwl1 t whwl1 t whwl2 address green red blue 5342_23 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 t rhrl1 t rhrl1 t rhrl2 address green red blue idt? / ics? 16-bit integrated clock-lut-dac ICS5342 28
ICS5342 gendac 29 color value read followed by any write write and read back pll address register (write mode) 5342_24 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 t rhrl1 t rhrl1 t rhwl2 address green red blue 5342_25 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 address address idt? / ics? 16-bit integrated clock-lut-dac ICS5342 29 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 30 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 30 write and read back pll address register (read mode) read two bytes pll register then pll address register 5342_26 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 address address+1 r d t b t pll r i t th pll add r i t 5342_27 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 t rhrl1 t rhrl1 t rhrl2 pll address pll high pll low adr+1
ICS5342 gendac 31 read one byte pll register then pll address register monitor sense signal 5342_28 rs0 rs1 rs2 d0-d7 wr* rd* t whrl3 t rhrl1 t rhrl1 t rhrl2 address pll adr+1 red green blue sense 0.335v t s 0d 5342_29 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 31 ICS5342 16-bit integrated clock-lut-dac tsd
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 32 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 32 recommended layout via to power plane via to ground plane agnd red avdd cvdd grn blue rset dvdd pclk xvdd xgnd xout xin clk0 36 35 34 33 32 31 30 29 28 27 40 39 38 37 43 42 41 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 1 2 3 4 5 6 7 8 9 68 64 65 66 67 61 62 63 gendac ii ICS5342 clk1 dgnd 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 r4 r2 r2 r4 r5 r1 c2 c2 vaa c1 fb1 c3 - - + c1 0.047 m f chip capacitor c2 0.1 m f chip capacitor c3 10 m f tantalum capacitor fb1 ferrite bead, fair-rite 2743019447 r1 33 ohm r2 100 ohm r3 141 ohm, 1% r4 220 ohm r5 560 ohm y1 parallel resonant crystal cut for c l = 12 pf c2 locate near controller locate near controller c1 c2 r3 vaa c2 y1 vaa c2 vref cgnd dgnd cvdd cgnd 5342_30 board layout and analog signal consider- ations the high performance of the gendac is dependent on care- ful pc board layout. the use of a four layer board (internal power and ground planes, signals on the two surface layers) is recommended. the ground plane layer should be closest to the component side of the board. the layout following this sec- tion shows a suggested configuration. power supply as a high speed cmos device, the gendac may draw large transient currents from the power supply. it is necessary to adopt high-frequency board-layout and power-distribution techniques to assure proper operation of the gendac. this will also minimize radio frequency interference (rfi). dac to dac crosstalk can also be attributed to a high impedance power supply.
idt? / ics? 16-bit integrated clock-lut-dac ICS5342 33 ICS5342 16-bit integrated clock-lut-dac tsd ICS5342 gendac 33 note the power plane is not separated into analog and digital supply regions. the power and ground planes are continuous, not split. power is supplied to the analog power pins through the ferrite bead, and bypassed at the power entry point by c3, a 10 m f tantalum capacitor. analog power connections should be routed as shown in the diagram. they may be routed on the back side so the analog signals are routed without vias. power pins 9 and 43 should be connected to digital power. power pins 27, 41 and 50 are connected to analog power (vaa). ce- ramic decoupling capacitors (indicated by c1 and c2) should be placed as close to the gendac as possible. the power traces should be routed through the capacitor pads and the ground vias should not be shared. the rule is: one pad, one via . the gendac analog ground pins should have multiple vias to the ground plane, if possible. to supply the transient currents required, the impedance in the decoupling path should be kept to a minimum. it is just as important that the connection between the capacitor ground pad and the ground plane be short and direct. it is recommend- ed that the decoupling capacitance between v dd and gnd should be a 0.047 m f to 0.1 m f high frequency capacitor. chip capacitors have the lowest lead inductance and are highly rec- ommended. 0.047 m f chip capacitors are more effective at fre- quencies above 80 mhz than other values in the range of 0.022 m f to 0.1 m f. all supply pins must have a ceramic ca- pacitor connected. a tantalum capacitor with a value between 10 m f and 22 m f is recommended to decouple low frequen- cies. to further reduce power-supply noise, a ferrite bead may be added in series with the positive supply to form a low pass filter, as shown in the layout example. power and ground trac- es to the gendac should be 50 mils wide whenever possi- ble. analog signals all analog and digital i/o lines are not shown. analog signals (dac outputs, v ref , r set ) should only be routed on the top side of the board. dac output termination resistors should be located as close as possible to the gendac for best signal quality. doing this will also reduce rfi. digital input information to minimize differential ground noise between components on the board, the impedance in the ground supply between the gendac and the digital devices driving it should be mini- mized. this or a high impedance ground trace on the control- ler may cause false signals to the gendac. this can appear as glitches on edge sensitive inputs such as rd*, wr*, and strb. splitting the ground plane exacerbates this problem. the combination of series impedance in the ground supply to the gendac and transients in the current drawn by the de- vice, will appear as voltage differences across the gnd pins on the gendac. the effect this will have is to compromise the low time and duty cycle of the output clocks. the pcb traces between the outputs of the ttl devices driv- ing the gendac and the input to the gendac behave like low impedance transmission lines. the trace is driven from a low impedance source and terminated with a high impedance. in accordance with transmission line principles, signal transi- tions will be reflected from the high impedance input to the device. similarly, signal transitions will be inverted and re- flected from the low impedance ttl output. termination is necessary to reduce or eliminate ringing; particularly the un- dershoot caused by reflections. termination may either be se- ries or parallel. series and parallel termination is the recommended technique to use. this is accomplished by plac- ing a resistor in series with the signal at the output of the clock driver. the resistor matches the output buffer impedance to that of the transmission line. at the far end of the line another resistor is added to terminate the transmission line to vcc. to minimize reflections, some experimentation is necessary to find the proper value to use for the series termination. gen- erally, a series resistor with a value around 75 w , and a parallel resistor of 330 w will be satisfactory. since each design will result in a different trace impedance, a resistor of a predeter- mined value may not properly match the signal path imped- ance. the proper value of resistance should be found empirically.
ICS5342 gendac 36 package detail 0.890 - 0.930 (22.61 - 23.62) 0.165 - 0.180 (4.20 - 4.57) 0.102 (2.59) 0.020 (0.51) 0.013 - 0.021 (0.33 - 0.53) 0.045 0.045 inches (millimeters) lead pitch 0.050 typical dimensions: package outline 27 43 9 gendac ii ICS5342 61 0.985 - 0.995 (25.02 - 25.27) 0.950 - 0.958 (24.13 - 24.33) 0.985 - 0.995 (25.02 - 25.27) 0.950 - 0.958 (24.13 - 24.33) pin 1 identifier 68 pin plcc 5342_31 idt? / ics? 16-bit integrated clock-lut-dac ICS5342 36 ICS5342 16-bit integrated clock-lut-dac tsd
ICS5342 16-bit integrated clock-lut-dac tsd ics8705 zero delay, differential-to-lvcmos/lvttl clock generator tsd ics1522 user-programmable video clock generator/ line-locked clock regenerator tsd ics9148-82 frequency generator & integrated buffers for pentium/pro? tsd ics8535-01 low skew, 1-to-4 lvcmos/lvttl-to-3.3v lvpecl fanout buffer tsd ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa xx-xxxx-xxxxx corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support clockhelp@idt.com 408-284-8200 innovate with idt and accelerate your future networks. contact: www.idt.com ics8521 low skew, 1-to-9 differentia l-to-hstl fanout buffer tsd

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