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14 - 1 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er f unctional diagram t ypical applications f eatures g eneral description low noise: 6 db nf high linearity: output ip3 +30 dbm variable gain: 0 to 40 db high bandwidth: dc to 100 mhz precise gain accuracy: 0.5 db gain step excellent magnitude and phase response externally controlled common mode output level parallel or serial gain control read/write serial port interface (spi) 24 lead 4x4 mm smt package 16 mm 2 programmable input impedance (400 differential or 100 differential) the HMC960LP4E is suitable for: ? baseband i/q transceivers ? direct conversion & low if transceivers ? diversity receivers ? adc drivers ? adaptive gain control the HMC960LP4E is a digitally programmable dual channel variable gain amplifer. it supports discrete gain steps from 0 to 40 db in precise 0.5 db steps. it features a glitch free architecture to provide exceptionally smooth gain transitions. the device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth. the HMC960LP4E provides an spi programmable input impedance of 100 differential or 400 differential (default). externally controlled common mode output feature enables the HMC960LP4E to provide a fexible output interface to other parts in the signal path. gain can be controlled via either a parallel interface (gc[6:0]) or via the read/write serial port (spi). housed in a compact 4x4mm (lp4) smt qfn package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifer architectures.
14 - 2 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er t able 1. e lectrical specifcations t a = +25c, vddi, vddq, dvdd = 5v +/-10%, gnd = 0v, 400 differential load unless otherwise stated. parameter conditions min. typ. max. units analog performance gain range 0 40 db gain step size 0.5 db gain step error f = 40 mhz 0.05 0.2 db gain absolute error f = 40 mhz 0.1 0.2 db dc offset [4] measured over all gain settings 0 50 mv signal bandwidth 0.5 db bandwidth 3 db bandwidth over all gain settings 50 100 90 180 mhz mhz noise figure 100 input impedance (100 ohm source) 400 input impedance (400 ohm source) gain: 0 db (min gain) 10 db 20 db 30 db 40 db (max gain) 0 db (min gain) 10 db 20 db 30 db 40 db (max gain) 23 14 7.5 6.5 6 17.5 11 6.7 6.3 6.1 db db db db db db db db db db output noise 0 db gain 40 db gain measured at f = 1 mhz 100 matched input load 9 125 nv/rthz nv/rthz output ip3 0 db gain 40 db gain using two tones near 20 mhz at 2 vppd output 32 33 dbm dbm im3 0 db gain 40 db gain using two tones near 20 mhz at 2 vppd output -75 -80 dbc dbc output ip2 0 db gain 40 db gain using two tones near 20 mhz at 2 vppd output 73 73 dbm dbm im2 0 db gain 40 db gain using two tones near 20 mhz at 2 vppd output -80 -80 dbc dbc sideband suppression (uncalibrated) [1] tested at 20 mhz over all gains 40 55 db i/q channel balance [1] gain phase tested at 20 mhz 0.02 0.15 db degrees i/q channel isolation 60 70 db analog i/o differential input impedance 100 mode 400 mode 80 320 100 400 120 480 full scale differential input 400 differential load 100 differential load min / max gain setting min / max gain setting 2/0.02 1/0.02 vppd vppd input common mode voltage range 1 4 v
14 - 3 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com parameter conditions min. typ. max. units full scale differential output 400 differential load 100 differential load 2 1 vppd vppd output voltage range 0.5 vdd - 0.5 v output common mode voltage range [2] 1 vdd/2 3 v digital i/o tested at 30 mhz operation logic levels digital input low level (vil) 0.4 v digital input high level (vih) 1.5 v digital output low level (vol) 0.4 v digital output high level (voh) vdd - 0.4 v supply related digital i/o power supply analog & digital supplies 4.5 5 5.5 v supply current [3] both i/q channels 70 ma t able 1. e lectrical specifcations, t a = +25c (continued) parameter condition temperature +27 c gain setting 0 db output signal level 2 vppd input/output common mode level 2.5 v programmed impedance 200 per input (400 differential) output load 200 per output (400 differ - ential) supplies analog: +5 v, digital +5 v driver bias setting 10 op-amp bias setting 01 (standard setting) t able 2. t est conditions unless otherwise specifed, the following test conditions were used [1] sideband rejection is only measured in db, but relates to phase/magnitude channel imbalance as follows, for a mismatch of 1 degree phase and 0.1 db magnitude: sbr = -10log[(1+a^2-2acosx)/(1+a^2+2acosx)] where a = 10^(0.1/20) (linear magnitude) and x = 1*pi/180 (radians) [2] output common mode voltage range is specifed for worst case temperature, supply voltage, and bias settings with 2 vppd signal amplitude. for 5 v supply and recommended biasing (op-amp bias =1 and driver bias=2), over 3.5 v is typical. see output ip3 vs. common mode voltage vs. driver bias setting[1] in figure 12 [3] recommend bias setting (op-amp bias =1 and driver bias=2) [4] standard deviation = 15 mv
14 - 4 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er f igure 1. g ain vs. t emperature (40 mhz) f igure 3. g ain vs. t emperature (100 mhz) f igure 2. g ain e rror, absolute & step (40 mhz) f igure 5. f requency r esponse vs. g ain [1] f igure 4. g ain e rror, absolute & step (100 mhz) f igure 6. channel i solation vs. g ain [2] 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 -40 c 27 c 85 c programmed gain (db) measured gain (db) 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 -40 c 27 c 85 c programmed gain (db) measured gain (db) -30 -20 -10 0 10 20 30 40 50 0.1 1 10 100 1000 frequency (mhz) gain (db) 40db gain 0db gain -0.1 -0.05 0 0.05 0.1 0 5 10 15 20 25 30 35 40 absolute gain relative gain programmed gain (db) gain error (db) -0.5 -0.25 0 0.25 0.5 0 5 10 15 20 25 30 35 40 absolute gain relative gain programmed gain (db) gain error (db) -100 -90 -80 -70 -60 -50 -40 -30 -20 0.1 1 10 100 1000 0db 10db 20db 30db 40db frequency (mhz) isolation (dbfs) 40 db gain 0 db gain [1] 2 db gain step increments [2] 10 db gain step increments
14 - 5 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com f igure 7. i m2 vs. f requency & g ain [4] f igure 8. output ip 2 vs. f requency & g ain [4] f igure 9. i m3 vs. f requency and g ain, standard b ias setting [5][7] -115 -110 -105 -100 -95 10 20 30 40 50 60 70 80 0 db 10 db 20 db 30 db 40 db frequency (mhz) im2 (dbc) 10 15 20 25 30 35 40 45 10 100 0db 5db 10db 15db 20db 25db 30db 35db 40db frequency (mhz) oip3 (dbm) greater than 30 db gain setting less than 30 db gain setting 10 15 20 25 30 35 40 45 10 100 0db 5db 10db 15db 20db 25db 30db 35db 40db frequency (mhz) oip3 (dbm) greater than 30 db gain setting less than 30 db gain setting 60 70 80 90 100 110 10 20 30 40 50 60 70 80 0 db 10 db 20 db 30 db 40 db frequency (mhz) oip2 (dbm) f igure 10. i m3 vs. f requency & g ain, high linearity b ias setting [6][7] f igure 11. output ip 3 vs. f requency & g ain, standard b ias setting [5] [7] f igure 12. output ip 3 vs. f requency & g ain, high linearity b ias setting [6] [7] [3] vga gain = 0 db, 2 vpp differential output [4] 300 mvppd output, load impedance = 400 differential [5] amplifier bias setting = 01 (standard setting) [6] amplifier bias setting = 10 (high linearity setting) -100 -90 -80 -70 -60 -50 -40 10 100 0db 5db 10db 15db 20db 25db 30db 35db 40db frequency (mhz) im3 (dbc) gain settings 30 db or greater gain settings less than 30 db -100 -90 -80 -70 -60 -50 -40 10 100 0db 5db 10db 20db 15db 25db 30db 35db 40db frequency (mhz) im3 (dbc) gain settings 30 db or greater gain settings less than 30 db
14 - 6 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er f igure 13. output ip 3 vs. f requency & b ias, g ain = 10 d b [5][6] [7] [9] f igure 14. output ip 3 vs. f requency & b ias, g ain = 30 d b [5][6] [7] [9] 26 28 30 32 34 36 0.5 1 1.5 2 2.5 3 3.5 4 vdd = 4.5 vdd = 4.75 vdd = 5 vdd = 5.25 vdd = 5.5 common mode voltage (v) oip3 (dbm) 4.5 v 5.5 v 26 28 30 32 34 36 0.5 1 1.5 2 2.5 3 3.5 4 4.5 vdd = 4.5 vdd = 4.75 vdd = 5 vdd = 5.25 vdd = 5.5 common mode voltage (v) oip3 (dbm) 4.5 v 5.5 v f igure 15. output ip 3 vs. output common mode, standard b ias setting [3][5] 10 15 20 25 30 35 40 45 10 100 standard bias setting hight linearity bias setting frequency (mhz) oip3 (dbm) f igure 16. output ip 3 vs. output common mode, high linearity b ias settings [3][6] 10 15 20 25 30 35 40 45 10 100 standard bias setting high linearity bias setting frequency (mhz) oip3 (dbm) f igure 17. output voltage vs. i nput voltage for various g ains f igure 18. output vs. e xpected output over g ain [8] 0.1 1 10 0.01 0.1 1 10 0db 5db 10db 15db 20db 25db 30db 35db 40db input voltage (vppd) output voltage (vppd) 40 db gain 0 db gain -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 0db 5db 10db 15db 20db 25db 30db 35db 40db refp1db expected output power (dbm) output power (dbm) 40 db gain 0 db gain 2vppd / 1dbm 1vppd / -5dbm [7] load impedance = 400 differential, 2 vppd output [8] output power (dbm) is measured into 400 output load [9] use the following formulas conversion between dbm, dbv rms , and v ppd , using a 400 differential load: dbv rms = 20log(vppd/2.8284), dbm = 10log((vppd/2.8284) 2 /400x10 -3 ), dbm = dbv rms - 10log(400x10 -3 )
14 - 7 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com f igure 19. output n oise vs. low f requency, 100 r in [10] f igure 20. n oise f igure vs. g ain & i nput i mpedance at 1 mhz 10 100 1000 0.001 0.01 0.1 1 10 100 frequency (mhz) noise (nv/rthz) 40 db gain 0 db gain f igure 21. sideband r ejection vs. g ain 5 10 15 20 25 0 5 10 15 20 25 30 35 40 400 ohm 100 ohm programmed gain (db) noise figure (db) 45 50 55 60 65 70 75 0 5 10 15 20 25 30 35 40 1 mhz 40 mhz programmed gain (db) sideband rejection (dbc) [10] 5 db gain step increments -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 4000 4500 5000 5500 6000 time (nsec) output (v) 6 db gain increase f igure 22. t ransient b ehavior, 10 mhz, 6 d b g ain i ncrease
14 - 8 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er outline drawing part number package body material lead finish msl rating [2] package marking [1] HMC960LP4E rohs-compliant low stress injection molded plastic 100% matte sn msl1 h960 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c p ackage i nformation t able 3. absolute maximum r atings nominal 5 v supply to gnd vddi, vddq, dvdd -0.3 to 5.5 v common mode inputs pins (cmi, cmq) -0.3 to 5.5 v input and output pins iip, iin, iqp, iqn, oip, oin, oqp, oqn -0.3 to 5.5 v digital pins sen, sdi, sck, sdo, gc[6:0] sdo min load impedance -0.3 to 5.5 v 1 k operating temperature range -40 to +85 c storage temperature -65 to +125 c maximum junction temperature 125 c thermal resistance (rth) (junction to ground paddle) 10 c/w electrostatic sensitive device observe handling precautions refow soldering peak temperature time at peak temperature 260 c 40 s esd sensitivity (hbm) 1 kv class 1 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes: [1] package body material: low stress injection molded plastic silica and silicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimensions are in inches [millimeters]. [5] lead spacing tolerance is non-cumulative. [6] pad burr length shall be 0.15mm max. pad burr height shall be 0.25m max. [7] package warp shall not exceed 0.05mm [8] all ground leads and ground paddle must be soldered to pcb rf ground. [9] refer to hittite application note for suggested pcb land pattern.
14 - 9 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com t able 4. p in descriptions pin number function description interface schematic 1 cmq quadrature (q) channel output common mode level 2, 3 oqn, oqp quadrature (q) channel positive and negative differential outputs 4 - 10 gc[6:0] gain control input pins gain is defned as: gc[6:0] = 0d > gain = 0 db gc[6:0] = 1d > gain = 0.5 db gc[6:0] = 2d > gain = 1 db gc[6:0] = 79d > gain = 39.5 db gc[6:0] = 80d > gain = 40 db 11 dvdd digital 5v supply. must be locally decoupled to gnd. 12, 14, 15 sclk, sdi, sen spi data clock, data input and enable respectively. 13 sdo spi data output 16, 17 oip, oin inphase (i) channel negative and positive differential outputs respectively 18 cmi inphase (i) channel output common mode level
14 - 10 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er t able 4. p in descriptions (continued) pin number function description interface schematic 19, 20 iip, iin inphase (i) channel positive and negative differential inputs respectively 21 vddi inphase (i) channel 5 v supply. must be locally decoupled to gnd 22 vddq quadrature (q) channel 5 v supply. must be locally decoupled to gnd 23, 24 iqn, iqp quadrature (q) channel negative and positive differential inputs respectively
14 - 11 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com e valuation p c b the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request. item contents part number evaluation pcb only HMC960LP4E evaluation pcb 131109-HMC960LP4E evaluation kit HMC960LP4E evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software) 131191- HMC960LP4E t able 5. e valuation order i nformation
14 - 12 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er e valuation setup hmc960l p 4 e application i nformation the wide bandwidth, large dynamic range, and excellent noise-linearity trade-off make the HMC960LP4E ideal for automatic gain control applications in the baseband section of a direct down-conversion receiver. matched dual amplifer design provides excellent gain and phase balance between the two channels. externally controlled common mode voltage, and spi programmable input impedance simplify the interface between the HMC960LP4E and other components in the signal path. the HMC960LP4E can be cascaded with hmc900lp5e without the need of any matching circuitry. together, these two components provide a complete baseband line-up that can directly drive adcs such as the 12-bit, dual channel, 320 msps hmcad1520. figure 1. typical receive path block diagram showing HMC960LP4E
14 - 13 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com t heory of operation the HMC960LP4E consists of the following functional blocks 1. input match & gain stage 2. second gain stage 3. output driver & gain stage 4. bias circuit 5. serial port interface 6. parallel port interface i nput match & g ain stage the HMC960LP4E input stage consists of a user selectable 100 or 400 differential input impedance and a programmable gain of 0, 10 or 20 db. a block diagram showing input impedance of the i channel is presented below, q channel is similar. figure 2. input stage block diagram second g ain stage the HMC960LP4E second stage consists of a series of carefully scaled resistors to generate up to 10 db of gain in 0.5 db steps. the gain step is fully determined by resistor ratios and as such the gain precision is relatively independent of both temperature and process variation.
14 - 14 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er output driver & g ain stage the HMC960LP4E output driver consists of a differential class ab driver which is designed to drive typical adc loads directly or can drive up to 200 in parallel with 50 pf to ac ground per differential output. the stage provides a programmable 0 db or 10 db gain via switched resistors. note that the output common mode of the driver is controlled directly via an input pin and can be set as per table 1. electrical specifcations . figure 3. output driver block diagram
14 - 15 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com g ain decode logic the decode logic automatically allocates gain to the three stages so as to minimize output noise and optimize noise fgure. without using decode logic gain can be allocated arbitrarily, as shown in table 11 . decode logic gain allocation, shown in figure 4, can be controlled via the parallel port or the spi, and refects gain control shown in table 10 . figure 4. decode logic gain allocation b ias circuit a band gap reference circuit generates the reference currents used by the different sections. the bias circuit is enabled or disabled as required with the i or q channel as appropriate.
14 - 16 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er serial p ort i nterface the HMC960LP4E features a four wire serial port for simple communication with the host controller. typical serial port operation can be run with sck at speeds up to 30 mhz. the details of spi access for the HMC960LP4E is provided in the following sections. note that the read operation below is always preceded by a write operation to register 0 to defne the register to be queried. also note that every read cycle is also a write cycle in that data sent to the spi while reading the data will also be stored by the HMC960LP4E when sen goes high. if this is not desired then it is suggested to write to register 0 during the read operation so that the status of the device will be unaffected. p ower on r eset and soft r eset the HMC960LP4E has a built in power on reset (por) and a serial port accessible soft reset (sr). por is accomplished when power is cycled for the HMC960LP4E while sr is accomplished via the spi by writing 20h to reg 0h followed by writing 00h to reg 0h. all chip registers will be reset to default states approximately 250 us after power up. serial p ort w rite operation the host changes the data on the falling edge of sck and the HMC960LP4E reads the data on the rising edge. a typical write cycle is shown in figure 5 . it is 32 clock cycles long. 1. the host both asserts sen (active low serial port enable) and places the msb of the data on sdi followed by a rising edge on sck. 2. HMC960LP4E reads sdi (the msb) on the 1st rising edge of sck after sen. 3. HMC960LP4E registers the data bits, d23:d0, in the next 23 rising edges of sck (total of 24 data bits). 4. host places the 5 register address bits, a4:a0, on the next 5 falling edges of sck (msb to lsb) while the HMC960LP4E reads the address bits on the corresponding rising edge of sck. 5. host places the 3 chip address bits, ca2:ca0=[110], on the next 3 falling edges of sck (msb to lsb). note the HMC960LP4E chip address is fxed as 6d or 110b. 6. sen goes from low to high after the 32th rising edge of sck. this completes the write cycle. 7. HMC960LP4E also exports data back on the sdo line. for details see the section on read operation. serial p ort re ad operation the spi can read from the internal registers in the chip. the data is available on sdo pin. this pin itself is tri-stated when the device is not being addressed. however when the device is active and has been addressed by the spi master, the HMC960LP4E controls the sdo pin and exports data on this pin during the next spi cycle. HMC960LP4E changes the data to the host on the rising edge of sck and the host reads the data from HMC960LP4E on the falling edge. a typical read cycle is shown in figure 5 . read cycle is 32 clock cycles long. to specifcally read a register, the address of that register must be written to dedicated reg 0h . this requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. the host asserts sen (active low serial port enable) followed by a rising edge sck. 2. HMC960LP4E reads sdi (the msb) on the 1 st rising edge of sck after sen. 3. HMC960LP4E registers the data bits in the next 23 rising edges of sck (total of 24 data bits). the lsbs of the data bits represent the address of the register that is intended to be read. 4. host places the 5 register address bits on the next 5 falling edges of sck (msb to lsb) while the HMC960LP4E reads the address bits on the corresponding rising edge of sck. for a read operation this is 00000.
14 - 17 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com 5. host places the 3 chip address bits <110> on the next 3 falling edges of sck (msb to lsb). note the HMC960LP4E chip address is fxed as 6d or 110b. 6. sen goes from low to high after the 32 nd rising edge of sck. this completes the frst portion of the read cycle. 7. the host asserts sen (active low serial port enable) followed by a rising edge sck. 8. HMC960LP4E places the 24 data bits, 5 address bits, and 3 chip id bits, on the sdo, on each rising edge of the sck, commencing with the frst rising edge beginning with msb. 9. the host de-asserts sen (i.e. sets sen high) after reading the 32 bits from the sdo output. the 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. this completes the read cycle. note that the data sent to the spi during this portion of the read operation is stored in the spi when sen is de-asserted. this can potentially change the state of the HMC960LP4E. if this is undesired it is recommended that during the second phase of the read operation that reg 0h is addressed with either the same address or the address of another register to be read during the next cycle. figure 5. spi timing diagram
14 - 18 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er dvdd = 5 v 10%, gnd = 0 v t able 6. main s pi t iming characteristics parameter conditions min typ max units t 1 sdi to sck setup time 8 nsec t 2 sdi to sck hold time 8 nsec t 3 sck high duration [1] 10 nsec t 4 sck low duration 10 nsec t 5 sen low duration 20 nsec t 6 sen high duration 20 nsec t 7 sck to sen [2] 8 nsec t 8 sck to sdo out [3] 8 nsec [1] the spi is relatively insensitive to the duty cycle of sck. [2] sen must rise after the 32 nd falling edge of sck but before the next rising sck edge. if sck is shared amongst several devices this timing must be respected. [3] typical load to sdo is 10 pf, maximum 20 pf p arallel p ort i nterface the HMC960LP4E features a seven bit parallel port to aid in real time gain selection. the dynamic performance of the parallel port is specifed below. t able 7. g ain control p arallel p ort t iming characteristics parameter conditions min. typ. max. units f ssp gain control switching rate 20 mhz t ssp allowable skew between gc[6:0] input transitions 10 nsec
14 - 19 if/baseband processing - smt 14 HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com r egister map three registers provide all the required functionality via the spi port. t able 8. r eg 01h - e nable r egister bit name width default description [0] vga_i_enable 1 0 vga i channel enable bit [1] vga_q_enable 1 0 vga q channel enable bit [2:3] spare 2 0 [23:4] unused t able 9. r eg 02h - settings r egister bit name width default description [1:0] opamp_bias[1:0] 2 01 opamp bias setting. 00 -- min bias 11 -- max bias opamp_bias[1:0]=01 recommended for low frequency operation or 10 for improved linearity for higher frequency operation. [3:2] drvr_bias[1:0] 2 01 driver bias setting. 00 -- min bias 11 -- max bias drvr_bias[1:0]=10 recommended (characterized on recommended setting only) [4] rin_50ohm_select 1 0 input impedance setting: 0: rin of 200 ohms selected 1: rin of 50 ohms selected [5] gain_control_from_spi 1 0 source of gain control input 0: gain control taken from parallel port (pins) 1: gain control taken from spi register 3 [6] gain_decode_disable 1 0 bypass gain decoder 0: decoded gain taken from register 3, bits <8:0> 1: undecoded gain taken from register 3, bits <8:0> (spi gain control must be selected) [7] gain_deglitching_disable 1 0 bypass gain deglitcher 0: gain control deglitching active 1: gain control deglitching disabled (applies to spi and parallel port gain control) [23:8] unused
14 - 20 if/baseband processing - smt 14 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC960LP4E v00.0211 dc - 100 mh z dual digit al v a ri a b l e ga in a m p l ifie r with dri v er [1] reg 03h bit assignment depends on the setting of bits 5 and 6 in reg 02h. if reg 02h[5]=0, then all reg 03h bits are ignored (parallel port selected) [2] for reg 02h[5]=1 and reg 02h[6]=0, gain control is via an spi register with decode, and reg 03h[6:0] are used as follows. [3] note that the parallel port gain logic always uses the gain decode logic, and therefore the bit encoding is the same as reg 03h - gain control register when using decode logic. [4] for reg 02h [5]=1 and reg 02h [6]=1, gain control is via an spi register without decode, and reg 03h[6:0] are used as follows. t able 10. r eg 03h - g ain control r egister wh en us ing decode logic [1][2] bit name width default description [6:0] gain[6:0] 7 0000000 reg 02h[5]=1 and reg 02h[6]=0 (i.e. spi gain control & gain decode enabled) gain[6:0] defnes teh vga channel i and q gain of 0-40db as follows... 0000000 - 0 db, minimum gain setting 0000001 - 0.5 db gain 0000010 - 1.0 db gain ... 1001110 - 39 db gain 1001111 - 39.5 db gain 1010000 - 40 db, maximum gain setting reg 02h[5] = 1 and reg 02h[6] = 1 (i.e. spi gain control & gain decode bypassed) [23:7] unused t able 11. r eg 03h - g ain control r egister, wh en n o t using decode logic [3][4] bit name width default description [8:0] gain[8:0] 9 000000000 gain[8:0] defne the vga i and q channel gain when reg 02h[5] = 1 and reg 02h[6] = 1 (i.e. spi gain control and gain decode bypassed) generally the frst 4 bits control the 1st and 3rd stage while the last 5 bits control the 2nd stage gain. x001nnnnn - 1st stage set to 0 db x010nnnnn - 1st stage set to 10 db x100nnnnn - 1st stage set to 20 db 0xxxnnnnn - 3rd stage set to 0 db 1xxxnnnnn - 3rd stage set to 10 db xxxxnnnnn - 2nd stage set as follows: nnnnn = 00000 - set to 0 db nnnnn = 00001 - set to 0.5 db nnnnn = 10011 - set to 9.5 db nnnnn = 10100 - set to 10 db [23:9] unused

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