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? e97841-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. timing generator for progressive scan ccd image sensor 48 pin tqfp (plastic) CXD2434ATQ absolute maximum ratings (ta=25 ?) supply voltage v dd v ss ?.5 to +7.0 v input voltage v i v ss ?.5 to v dd +0.5 v output voltage v o v ss ?.5 to v dd +0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 4.75 to 5.25 v operating temperature topr ?0 to +75 ? description the CXD2434ATQ is an ic developed to generate the timing pulses required by the progressive scan ccd image sensors as well as signal processing circuits. the CXD2434ATQ adds efs operation when using the high-speed electronic shutter and other changes to the cxd2434tq specifications. features external trigger function electronic shutter function supports non-interlaced operation 30 frames/s built-in driver for the horizontal (h) clock base oscillation 1560 f h (24.5454 mhz) applications progressive scan ccd cameras structure silicon gate cmos ic applicable ccd image sensors icx084ak, icx084al
2 CXD2434ATQ t g p u l s e g e n e r a t o r 1 0 1 3 1 4 2 1 1 8 2 2 2 3 1 7 1 6 1 9 3 8 3 9 4 0 r e g i s t e r p s s t r b d c l k d a t a s m d 1 s m d 2 x s u b t e s t 1 t e s t 2 r e s e t r g h 1 h 2 x s h p x s h d x r s x v 1 x v 2 x v 3 x s g c l d c l c k o b u s y w e n i d p b l k x c p o b x c p d m v d h d s t d b y w m s m d e f s e d e c o d e c o u n t e r g a t e 4 1 4 8 2 8 1 1 9 8 7 5 4 3 2 5 2 6 2 9 4 2 4 6 4 7 3 1 3 2 3 3 3 4 3 5 3 6 1 2 4 3 4 4 4 5 6 1 2 1 5 2 0 2 4 2 7 3 0 3 7 o s c o o s c i t r i g e s g e f s v s s v d d v s s v d d v s s v s s v d d v s s 1 / 2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 5 2 6 3 6 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 4 7 4 8 c x d 2 4 3 4 a t q v s s c l c l d c k o r e s e t s t d b y t r i g e s g e f s h d v d t e s t 2 v s s x r s x s h d x s h p v d d x s g x v 1 x v 2 x v 3 v s s h 2 h 1 b u s y w e n i d p b l k x c p o b s c p d m v d d w m t e s t 1 v s s s m d e f s e o s c o o s c i p s s t r b d c l k v s s d a t a s m d 1 s m d 2 r g x s u b v d d block diagram pin configuration (top view) 3 CXD2434ATQ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 o i i i i i i i o o o o o o o o o o o i i i i o o o o o o o o osco osci ps strb dclk v ss data smd1 smd2 rg xsub v dd h1 h2 v ss xv3 xv2 xv1 xsg v dd xshp xshd xrs v ss fse smde v ss test1 wm v dd xcpdm xcpob pblk id wen busy v ss cl cld inverter output for oscillation. inverter input for oscillation. switching for electronic shutter speed input method. (with pull-up resistor) low: serial input, high: parallel input shutter speed setting. (with pull-up resistor) shutter speed setting. (with pull-up resistor) gnd shutter speed setting. (with pull-up resistor) shutter mode setting. (with pull-up resistor) shutter mode setting. (with pull-up resistor) reset gate pulse output. ccd discharge pulse output. power supply. clock output for horizontal ccd drive. clock output for horizontal ccd drive. gnd clock output for vertical ccd drive. clock output for vertical ccd drive. clock output for vertical ccd drive. sensor charge readout pulse output. power supply. sample-and-hold pulse output. sample-and-hold pulse output. sample-and-hold pulse output. gnd switching for external trigger discharge operation. (with pull-up resistor) low: no high-speed discharge, high: high-speed discharge switching for readout timing. (with pull-up resistor) low: esg input valid, high: esg input invalid gnd test. (with pull-down resistor) wen mode setting. (with pull-down resistor) low: effective line, high: xsg synchronization power supply. clamp pulse output. clamp pulse output. blanking cleaning pulse output. line identification output. write enable output. trigger mode flag output. gnd 780 f h clock output. ad conversion pulse output. pin description pin no. symbol i/o description 4 CXD2434ATQ pin no. symbol i/o description 40 41 42 43 44 45 46 47 48 cko reset stdby trig esg efs hd vd test2 o i i i i i i i i 1560 f h clock output. reset. (with pull-up resistor) low : reset, high : normal standby. (with pull-up resistor) low: internal clock supply stopped, high: normal external trigger input. (with pull-up resistor) external readout input. (with pull-up resistor) vertical ccd discharge input. (with pull-up resistor) horizontal sync signal input. vertical sync signal input. test. (with pull-up resistor) electrical characteristics 1. dc characteristics v dd = 4.75 v to 5.25 v topr= ?0 to +75 c item supply voltage input voltage 1 (input pins other than those listed below) input voltage 2 (pin 2) output voltage 1 (output pins other than those listed below) output voltage 2 (pins 21, 22, 23, 38, 39 and 40) output voltage 3 (pin 10) output voltage 4 (pins 13 and 14) output voltage 5 (pin 1) feedback resistor pull-up resistor pull-down resistor current consumption symbol v dd v ih1 v il1 v ih2 v il2 v oh1 v ol1 v oh2 v ol2 v oh3 v ol3 v oh4 v ol4 v oh5 v ol5 r fb r pu r pd i dd conditions i oh =?.5 ma i ol =4.5 ma i oh =?.0 ma i ol =9.0 ma i oh =?.5 ma i ol =13.5 ma i oh =?4.0 ma i ol =24.0 ma v in = v ss or v dd v il =0 v v ih =v dd v dd =5 v min. 4.75 0.7 v dd 0.7 v dd v dd ?.4 v dd ?.4 v dd ?.4 v dd ?.4 v dd /2 typ. 5.0 1 m 50 k 50 k 40 max. 5.25 0.3 v dd 0.3 v dd 0.4 0.4 0.4 0.4 v dd /2 100 k 100 k unit v v v v v v v v v v v v v v v ma 5 CXD2434ATQ 2. ac characteristics 1) waveform characteristics of h1, h2 and rg t r h 1 t w h 1 t f h 1 0 . 9 v d d 0 . 1 v d d 0 . 9 v d d 0 . 1 v d d t f h 2 t w h 2 t r h 2 t r r g t w r g t f r g h 1 h 2 r g 0 . 9 v d d 0 . 1 v d d v dd =5.0 v, topr=25 c, load capacitance of h1 and h2=100 pf, load capacitance of rg=10 pf symbol t rh1 t fh1 t wh1 t rh2 t fh2 t wh2 t rrg t frg t wrg definition h1 rise time h1 fall time h1 high level time h2 rise time h2 fall time h2 low level time rg rise time rg fall time rg high level time min. 25 25 10 typ. 6 5 35 6 5 35 2 2 15 max. 15 15 15 15 5 5 20 unit ns ns ns ns ns ns ns ns ns 6 CXD2434ATQ 2) phase characteristics of h1, h2, rg, xshp, xshd, xrs, cl, cld and cko t h 1 0 . 5 v d d 0 . 5 v d d 0 . 5 v d d t p d 3 t p d 1 0 . 5 v d d 0 . 5 v d d t p d 2 0 . 5 v d d 0 . 5 v d d t p d 4 t p d 5 t w 1 0 . 5 v d d 0 . 5 v d d t w 2 t p d 6 0 . 5 v d d 0 . 5 v d d 0 . 5 v d d t p d 7 0 . 5 v d d t p d 8 t p d 9 0 . 5 v d d 0 . 5 v d d t w 3 t p d 1 0 t w 4 0 . 5 v d d 0 . 5 v d d t w 5 t w 5 0 . 5 v d d 0 . 5 v d d 0 . 5 v d d 0 . 5 v d d t p d 1 1 t p d 1 1 h 1 h 2 r g x s h p x s h d x r s c l d c l c l o v dd =5.0 v, topr=25 c, load capacitance of cl and cko=30 pf, load capacitance of cld, xshp, xshd, xrs and rg=10 pf symbol t h1 t pd1 t pd2 t pd3 t pd4 t pd5 t pd6 t pd7 t pd8 t pd9 t pd10 t pd11 t w1 t w2 t w3 t w4 t w5 definition h1 cycle h2 rising delay, activated by the falling edge of h1 h2 falling delay, activated by the rising edge of h1 h1 rising delay, activated by the rising edge of rg xshp falling delay, activated by the falling edge of rg h1 falling delay, activated by the rising edge of xshp h1 rising delay, activated by the rising edge of xshd cld falling delay, activated by the falling edge of xshd cld falling delay, activated by the rising edge of xrs xrs falling delay, activated by the falling edge of cld cl falling delay, activated by the rising edge of h1 h1 rising (falling) delay, activated by the rising edge of cko xshp pulse width xshd pulse width cld pulse width cl pulse width cko pulse width min. ? ? ? ? ? ? ? 17 0 ? ? 13 15 17 38 17 typ. 82 0 0 0 4 2 2 2 22 8 0 2 18 20 22 41 20 max. 5 5 5 10 7 7 7 27 15 5 7 23 25 27 45 24 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 CXD2434ATQ 3) phase conditions of hd, vd, trig, efs and esg 0 . 5 v d d t s e t u p t h o l d 0 . 5 v d d 0 . 5 v d d c l h d , v d , t r i g e f s , e s g v dd =5.0 v, topr=25 c, load capacitance of cl=30 pf symbol t setup t hold definition hd, vd, trig, efs and esg setup time, activated by cl hd, vd, trig, efs and esg hold time, activated by cl min. 20 5 typ. max. unit ns ns 4) phase characteristics of xv1, xv2, xv3, xsg, pblk, xcpdm, xcpob, busy, wen and id 0 . 5 v d d 0 . 5 v d d t p d c l 1 0 . 5 v d d t p d c l 2 0 . 5 v d d t p d c l 3 0 . 5 v d d c l x v 1 , x v 2 , x v 3 b u s y , w e n , i d x s g , p b l k , x c p d m , x c p o b v dd =5.0 v, topr=25 c, load capacitance of cl=30 pf, load capacitance of xv1, xv2, xv3, xsg, pblk, xcpdm, xcpob, busy, wen and id=10 pf symbol t pdcl1 t pdcl2 t pdcl3 definition xv1, xv2 and xv3 delay, activated by the falling edge of cl busy, wen and id delay, activated by the rising edge of cl xsg, pblk, xcpdm and xcpob delay, activated by the rising edge of cl min. 30 40 40 typ. max. 65 60 55 unit ns ns ns 8 CXD2434ATQ description of functions 1. progressive scan ccd drive pulse generation combining this ic with a crystal oscillator generates a fundamental frequency of 24.5454 mhz. ccd drive pulse generation is synchronized with the hd and vd inputs. set f cl to 780 f hd and fhd to 525 f vd . the various operations are performed by the trig, efs and esg inputs. (see the following items.) 9 CXD2434ATQ 3. electronic shutter 10 CXD2434ATQ ac characteristics for serial input symbol t sdd t hdd t sds t ws t wd definition data setup time, activated by the rising edge of dclk data hold time, activated by the rising edge of dclk dclk setup time, activated by the falling edge of strb strb pulse width dclk pulse width min. 10 ns 10 ns 10 ns 82 ns 82 ns max. 3-2. [parallel input] mode electronic shutter off flickerless high-speed shutter low-speed shutter ps h h h h h h h h h h h h h h h h h h smd1 h l l l l l l l l l h h h h h h h h smd2 h l h h h h h h h h l l l l l l l l strb x x h l h l h l h l h l h l h l h l dclk x x h h l l h h l l h h l l h h l l data x x h h h h l l l l h h h h l l l l exposure time 1/30 s 1/50 s 1/60 s 1/125 s 1/250 s 1/500 s 1/1000 s 1/2000 s 1/4000 s 1/10000 s 2 frm 3 frm 4 frm 5 frm 6 frm 7 frm 8 frm 9 frm 11 CXD2434ATQ 4. external trigger mode external trigger mode starts exposure in sync with the external trigger input. no special pins are required to set this mode. the ic prepares to shift to external trigger mode with the falling edge of the trig pin (note). the timing to shift to external trigger mode varies according to the mode setting. (see the table.) the busy pin maintains high status during external trigger mode. whether or not to discharge the vertical ccd charge is set by fse. note) see the detection timing for vd, trig, efs and esg. mode settings during external trigger (note 1) ps l h h x x smd1 l l l h h smd2 x h l l h description of operation the ic is shifted to external trigger mode by hd, exposure is finished after the set time, and xsg is output. (note 2) (note 3) the ic is shifted to external trigger mode by hd, exposure is finished 1/50 s later, and xsg is output. do not set for external trigger. trigger input is not accepted. note 1) the smd1 and smd2 setting method varies according to the ps status. see ?. electronic shutter? ps=low : set by serial input. ps=high : set by the smd1 and smd2 pins. note 2) the exposure time setting method is the same as the exposure time setting for the electronic shutter. note 3) when fse=high, set the number of exposed lines from 1 to 522. 12 CXD2434ATQ 5. discharge of the vertical ccd during efs is low, discharge of the vertical ccd is performed. during fse is high in the external trigger mode, the vertical control line by line is possible. that is different from discharge operation. the falling in the effective interval of efs is detected, discharge is not performed even if the low status is held until the next effective period. for frames using efs, set electronic shutter off or high-speed electronic shutter. when efs is used, wen (wm=low) may not indicate the proper status. 13 CXD2434ATQ 7. mode settings 7-1. vd input-related note 1) when ps is high, smd1 and smd2 indicate the status of the smd1 and smd2 pins, respectively. when ps is low, these are the corresponding internal register values. see ?. electronic shutter? note 2) operation when ps=high, smd1=low and smd2=low conforms to that when smd1=low and smd2=high. 7-2. trig, esg and efs input-related busy h l smde x h l x discharge period (note 1) exposure period signal output period before trig input after trig input (note 2) (note 3) trig prohibited ic shifted to external trigger mode (note 3) prohibited esg prohibited readout operation (note 4) prohibited prohibited (note 5) efs invalid discharge operation (note 6) (note 7) prohibited note 1) only when fse is high. note 2) valid only during low-speed shutter. note 3) see ?. external trigger mode? note 4) esg input is valid only one time after trig input. do not input esg two times or more. note 5) fix esg to high status when busy is low. note 6) when efs is low, readout is not activated by vd input. see ?-1. vd input-related? note 7) use in electronic shutter off state. note 8) in case any two pins or more among trig, esg, and efs are falled at the same time, the operation is not guaranteed. 7-3. wen mode switching by wm wm l h description of wen operation lines for which the signal from the ccd is valid output high; all other lines output low. output is synchronized with xsg. busy h l smd1 l h x x smd2 h l h x smde x x efs x h l vd input invalid readout operation or the number of accumulated frames is counted. readout operation is performed. invalid 14 CXD2434ATQ application circuit + 5 v c x d 2 4 3 4 a t q c x d 2 3 1 1 a r c x a 2 0 0 6 q i c x 0 8 4 a k / a l c x d 1 2 6 7 a n + 1 5 v 1 0 0 k 1 0 0 0 p 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 3 6 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 4 7 3 7 4 8 r e s e t c i r c u i t application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same . 15 CXD2434ATQ normal operation (vertical synchronization) 1 1 4 5 0 8 5 1 0 1 2 3 4 5 6 7 8 1 2 3 4 4 9 4 v d h d o u t x v 1 x v 2 x v 3 x s g x s u b p b l k x c p o b x c p d m i d w e n ( w m = h i g h ) w e n ( w m = l o w ) b u s y 16 CXD2434ATQ normal operation (horizontal synchronization) 7 8 0 1 1 3 5 3 5 7 8 1 0 7 4 7 5 9 7 1 8 3 9 5 7 2 9 5 3 5 1 2 3 1 1 2 0 1 0 9 9 3 1 1 9 h d c l x v 1 x v 2 x v 3 x s g ( = h i g h ) x s u b h 1 h 2 r g x s h p x s h d x r s p b l k x c p o b x c p d m i d w e n b u s y xsub may be kept high depending on the electronic shutter setting. 17 CXD2434ATQ 7 8 0 1 1 3 5 3 5 7 8 1 0 7 4 7 5 9 7 1 8 3 5 2 0 5 5 1 5 7 6 1 2 3 1 9 3 1 0 9 1 1 9 h d c l x v 1 x v 2 x v 3 x s g x s u b ( = h i g h ) h 1 h 2 r g x s h p x s h d x r s p b l k ( = l o w ) x c p o b x c p d m i d w e n ( = l o w ) b u s y = h i g h ( t r i g ) l o w ( o t h e r s ) normal operation: readout timing (horizontal synchronization) 18 CXD2434ATQ 1 2 7 1 1 4 5 0 8 1 2 3 4 5 6 7 8 1 2 3 4 t r i g v d h d o u t r g x v 1 x v 2 x v 3 x s g x s u b p b l k x c p o b x c p d m i d w e n ( w m = h i g h ) w e n ( w m = l o w ) b u s y external trigger mode: high-speed electronic shutter, discharge (fse=high, smde=high, smd1=low, smd2=high) * see ?. electronic shutter?for the time from trig input to xsg. * the fall of vd is invalid during the period while busy=high. 19 CXD2434ATQ external trigger mode: high-speed electronic shutter, when discharge starts (fse=high, smd1=low, smd2=high) 1 2 3 7 8 0 1 3 5 3 5 4 2 4 9 5 6 6 3 7 7 7 0 7 2 9 5 1 2 3 5 3 1 9 3 t r i g h d c l x v 1 x v 2 x v 3 x s g ( = h i g h ) x s u b h 1 h 2 r g x s h p x s h d x r s p b l k x c p o b x c p d m i d w e n b u s y 20 CXD2434ATQ 4 9 9 5 0 0 h d c l x v 1 x v 2 x v 3 x s g ( = h i g h ) x s u b h 1 h 2 r g x s h p x s h d x r s p b l k = ( l o w ) x c p o b ( = h i g h ) x c p d m ( = h i g h ) i d w e n ( = l o w ) b u s y ( = h i g h ) external trigger mode: high-speed electronic shutter, when discharge finishes (fse=high, smd1=low, smd2=high) 21 CXD2434ATQ 1 1 4 5 0 8 1 2 3 4 5 6 7 8 1 2 3 4 t r i g v d h d o u t r g x v 1 x v 2 x v 3 x s g x s u b p b l k x c p o b x c p d m i d w e n ( w m = h i g h ) w e n ( w m = l o w ) b u s y external trigger mode: high-speed electronic shutter, no discharge (fse=low, smde=high, smd1=low, smd2=x) * see ?. electronic shutter?for the time from trig input to xsg. * the fall of vd is invalid during the period while busy=high. 22 CXD2434ATQ 1 2 3 4 5 6 7 8 1 2 3 4 1 2 7 1 1 4 5 0 8 t r i g e s g v d h d o u t r g x v 1 x v 2 x v 3 x s g x s u b p b l k x c p o b x c p d m i d w e n ( w m = h i g h ) w e n ( w m = l o w ) b u s y example during esg input (fse=high, smde=low, smd1=low, smd2=x) the fall of vd is invalid during the period while busy=high. 23 CXD2434ATQ example during efs input (trigger mode: fse=high, smde=high, smd1=low, smd2=x) 1 2 7 1 6 1 3 9 8 9 9 3 3 9 3 4 0 2 5 6 2 6 4 t r i g e f s v d h d o u t r g x v 1 x v 2 x v 3 x s g x s u b p b l k x c p o b x c p d m i d w e n ( w m = h i g h ) w e n ( w m = l o w ) b u s y 4 2 b i t s 1 0 4 t i m e s the fall of vd is invalid during the period while busy=high. 24 CXD2434ATQ 7 8 0 1 3 5 3 5 1 0 7 7 7 5 6 6 3 4 2 4 9 7 0 1 2 3 5 3 1 9 3 e f s h d c l x v 1 x v 2 x v 3 x s g ( = h i g h ) x s u b ( = h i g h ) h 1 h 2 r g x s h p x s h d x r s p b l k x c p o b x c p d m i d w e n b u s y during efs input, when discharge starts 25 CXD2434ATQ i d e f s h d c l x v 1 x v 2 x v 3 x s g ( = h i g h ) x s u b h 1 h 2 r g x s h p x s h d x r s p b l k = ( l o w ) x c p o b ( = h i g h ) x c p d m ( = h i g h ) w e n ( = l o w ) b u s y ( = l o w ) during efs input, when discharge finishes s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e w e i g h t e p o x y r e s i n s o l d e r p l a t i n g 4 2 a l l o y p a c k a g e s t r u c t u r e 4 8 p i n t q f p ( p l a s t i c ) 0 . 2 g t q f p - 4 8 p - l 0 7 1 t q f p 0 4 8 - p - 0 7 0 7 - a n 0 . 1 a 7 . 0 0 . 2 3 6 2 5 9 . 0 0 . 4 2 4 1 3 1 2 1 4 8 3 7 0 . 5 0 . 2 0 . 1 m 0 . 0 8 d e t a i l a 0 . 5 0 . 2 1 . 0 0 . 2 3 3 + 7 0 . 1 0 . 1 1 . 0 0 . 1 1 . 2 7 m a x 0 . 1 2 5 0 . 0 5 package outline unit : mm CXD2434ATQ 26 |
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