? semiconductor components industries, llc, 2011 march, 2011 ? rev. 0 1 publication order number: NTMD5836NL/d NTMD5836NL power mosfet 40 v, dual n ? channel, soic ? 8 features ? asymmetrical n channels ? low r ds(on) ? low capacitance ? optimized gate charge ? these devices are pb ? free, halogen free/bfr free and are rohs compliant v (br)dss r ds(on) max i d max (notes 1 and 2) channel 1 40 v 12 m @ 10 v 11 a 16 m @ 4.5 v channel 2 40 v 25 m @ 10 v 6.5 a 30.8 m @ 4.5 v 1. surface ? mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces) 2. only selected channel is been powered 1w applied on channel 1: t j = 1 w * 85 c/w + 25 c = 110 c n ? channel 1 http://onsemi.com soic ? 8 case 751 marking diagram * and pin assignment a = assembly location y = year ww = work week = pb ? free package 5836nl ayww 1 8 1 8 s1 g1 s2 g2 d1 d1 d2 d2 (note: microdot may be in either location) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d device package shipping ? ordering information NTMD5836NLr2g soic ? 8 (pb ? free) 2500 / tape & reel d1 s1 g1 d2 s2 g2 n ? channel 2
NTMD5836NL http://onsemi.com 2 maximum ratings (t j = 25 c unless otherwise stated) parameter symbol ch 1 ch 2 unit drain ? to ? source voltage v dss 40 40 v gate ? to ? source voltage v gs 20 20 v continuous drain current r ja (notes 3 and 4) steady state t a = 25 c i d 9.0 5.7 a t a = 70 c 7.2 4.6 power dissipation r ja (notes 3 and 4) t a = 25 c p d 1.5 1.5 w t a = 70 c 0.9 0.9 continuous drain current r ja (notes 3 and 4) t 10s t a = 25 c i d 11 6.5 a t a = 70 c 8.6 4.6 power dissipation r ja (notes 3 and 4) t a = 25 c p d 2.1 1.9 w t a = 70 c 1.3 1.2 pulsed drain current t p = 10 s i dm 43 26 a operating junction and storage temperature t j , t stg ? 55 to +150 c source current (body diode) i s 10 7.0 a single pulse drain ? to ? source avalanche energy (v dd = 40 v, v gs = 10 v, l = 0.1 mh e as 76 22 mj i as 39 21 a lead temperature for soldering purposes (1/8? from case for 10s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. surface ? mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces) 4. only selected channel is been powered 1w applied on channel 1: t j = 1 w * 85 c/w + 25 c = 110 c thermal resistance ratings parameter symbol ch 1 ch 2 unit junction ? to ? ambient steady state (notes 5 and 7) r ja 85 86 c/w junction ? to ? ambient ? t 10 s (notes 5 and 7) r ja 60 65 junction ? to ? ambient steady state (notes 5 and 8) r ja 59 junction ? to ? ambient steady state (notes 6 and 7) r ja 136 136 5. surface ? mounted on fr4 board using 1 in sq pad size (cu area = 1.127 in sq [2 oz] including traces) 6. surface ? mounted on fr4 board using 0.155 in sq (100 mm 2 ) pad size 7. only selected channel is been powered 1w applied on channel 1: t j = 1 w * 85 c/w + 25 c = 110 c 8. both channels receive equivalent power dissipation 1 w applied on each channel: t j = 2 w * 59 c/w + 25 c = 143 c
NTMD5836NL http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition ch min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a ch 1 40 v ch 2 drain ? to ? source breakdown voltage temperature coefficient v (br)dss / t j ch 1 146 mv/ c ch 2 25 zero gate voltage drain current i dss v gs = 0 v, v ds = 40 v t j = 25 c ch 1 1.0 a ch 2 t j = 125 c ch 1 100 ch 2 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v ch 1 100 na ch 2 on characteristics (note 9) gate threshold voltage v gs(th) vgs = vds, i d = 250 a ch 1 1.0 1.8 3.0 v ch 2 1.0 1.8 3.0 negative threshold temperature coefficient v gs(th) / t j ch 1 6.0 mv/ c ch 2 6.0 drain ? to ? source on resistance r ds(on) v gs = 10 v, i d = 10 a ch 1 9.5 12 m v gs = 10 v, i d = 7 a ch 2 20.5 25 v gs = 4.5 v, i d = 10 a ch 1 13 16 m v gs = 4.5 v, i d = 7 a ch 2 25.0 30.8 forward transconductance g fs v ds = 15 v, i d = 10 a ch 1 10.5 s v ds = 15 v, i d = 7 a ch 2 6.0 charges, capacitances & gate resistance input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 20 v ch 1 2120 pf ch 2 730 output capacitance c oss ch 1 315 ch 2 123 reverse transfer capacitance c rss ch 1 225 ch 2 84 9. pulse test: pulse width 300 s, duty cycle 2% 10. switching characteristics are independent of operating junction temperatures
NTMD5836NL http://onsemi.com 4 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min ch test condition symbol charges, capacitances & gate resistance total gate charge q g(tot) v gs = 10v, v ds = 20v, i d = 10a ch 1 36 50 nc v gs = 10 v, v ds = 20 v, i d = 7 a ch 2 16 v gs = 4.5 v, v ds = 20 v, ch1: i d = 10 a, ch2: i d = 7 a ch 1 15 23 ch 2 8.5 11 threshold gate charge q g(th) ch 1 2.4 ch 2 1.0 gate ? to ? source charge q gs ch 1 6.9 ch 2 2.8 gate ? to ? drain charge q gd ch 1 7.2 ch 2 4.0 plateau voltage v gp ch 1 3.2 v ch 2 3.3 gate resistance r g ch 1 1.2 ch 2 2.1 switching characteristics (note 10) turn ? on delay time t d(on) v gs = 4.5 v, v dd = 20 v, ch1: i d = 10 a, ch2: i d = 7 a, r g = 2.5 ch 1 16 ns ch 2 11.5 rise time t r ch 1 22 ch 2 14 turn ? off delay time t d(off) ch 1 26 ch 2 15.5 fall time t f ch 1 8.5 ch 2 3.5 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, ch1: i d = 10 a, ch2: i d = 7 a t j = 25 c ch 1 0.9 1.2 v ch 2 0.85 1.2 t j = 125 c ch 1 0.65 ch 2 0.73 reverse recovery time t rr v gs = 0 v, disd/dt = 100 a/ s, ch1: i d = 10 a, ch2: i d = 7 a ch 1 27 ns ch 2 17 charge time t a ch 1 14 ch 2 11 discharge time t b ch 1 13 ch 2 6.0 reverse recovery charge q rr ch 1 19 nc ch 2 9.0 9. pulse test: pulse width 300 s, duty cycle 2% 10. switching characteristics are independent of operating junction temperatures
NTMD5836NL http://onsemi.com 5 typical performance curves 0 10 20 30 40 50 60 70 012345 v ds , drain ? to ? source voltage (v) i d, drain current (a) figure 1. on ? region characteristics ? channel 1 t j = 25 c 3.1 v 6.5 v 3.9 v 4.5 v v gs = 2.5 v 3.5 v 10v 5.5 v 8.5 v 0 10 20 30 40 50 60 70 2345 v gs , gate ? to ? source voltage (v) i d, drain current (a) figure 2. transfer characteristics ? channel 1 t j = 125 c t j = ? 55 c t j = 25 c v ds 20 v 0.01 0.015 0.02 0.025 0.03 0.035 2345678910 figure 3. on ? resistance vs. gate ? to ? source voltage ? channel 1 v gs , gate ? to ? source voltage (v) r ds(on), drain ? to ? source resistance ( ) t j = 25 c i d = 10 a 0.005 0.01 0.015 0.02 2 6 10 14 18 figure 4. on ? resistance vs. drain current and gate voltage ? channel 1 r ds(on), drain ? to ? source resistance ( ) v gs = 10 v v gs = 4.5 v i d, drain current (a) t j = 25 c 0.8 1 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 figure 5. on ? resistance variation with temperature ? channel 1 t j , junction temperature ( c) i d = 10 a v gs = 4.5 v r ds(on), drain ? to ? source resistance (normalized) 1000 10000 100000 10 20 30 40 figure 6. drain ? to ? source leakage current vs. voltage ? channel 1 v ds , drain ? to ? source voltage (volts) v gs = 0 v i dss , leakage (na) t j = 150 c t j = 125 c
NTMD5836NL http://onsemi.com 6 typical performance curves 0 500 1000 1500 2000 2500 3000 010203040 figure 7. capacitance variation ? channel 1 drain ? to ? source voltage (v) c, capacitance (pf) t j = 25 c c iss c oss c rss v gs = 0 v 0 2 4 6 8 10 0 5 10 15 20 25 30 35 40 figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge ? channel 1 q g , total gate charge (nc) v gs = 20 v i d = 10 a t j = 25 c q gs q gd q t v gs , gate ? to ? source (v) v ds , drain ? to ? source (v) 10 100 1000 1 10 100 figure 9. resistive switching time variation vs. gate resistance ? channel 1 r g , gate resistance ( ) t, time ( ns ) v dd = 20 v i d = 10 a v gs = 4.5 v t r t d(on) t f t d(off) 0 5 10 15 20 0.4 0.5 0.6 0.7 0.8 0.9 1 v sd , source ? to ? drain voltage (v) i s , source current (a) v gs = 0 v t j = 25 c figure 10. diode forward voltage vs. current ? channel 1 0.001 0.01 0.1 1 10 100 0.1 1 10 100 figure 11. maximum rated forward biased safe operating area ? channel 1 v ds , drain ? to ? source voltage (v) i d , drain current (a) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c dc 10 s 1 ms 100 s 1 s 0 20 40 60 80 25 50 75 100 125 150 t j , starting junction temperature ( c) eas, single pulse drain ? to ? source avalanche energy (mj) i d = 39 a figure 12. maximum avalanche energy vs. starting junction temperature ? channel 1
NTMD5836NL http://onsemi.com 7 typical performance curves 0 10 20 30 40 50 012345 v ds , drain ? to ? source voltage (v) i d, drain current (a) figure 1. on ? region characteristics ? channel 2 t j = 25 c 3.6 v 6.5 v v gs = 3 v 4 v 10v 5.5 v 8.5 v 4.5 v 0 10 20 30 40 50 2345 t j = 125 c t j = ? 55 c t j = 25 c v ds 5 v v gs , gate ? to ? source voltage (v) i d, drain current (a) figure 2. transfer characteristics ? channel 2 0.01 0.02 0.03 0.04 0.05 2345678910 figure 3. on ? resistance vs. gate ? to ? source voltage ? channel 2 v gs , gate ? to ? source voltage (v) r ds(on), drain ? to ? source resistance ( ) t j = 25 c i d = 7 a 0.015 0.02 0.025 0.03 2 6 10 14 18 figure 4. on ? resistance vs. drain current and gate voltage ? channel 2 t j = 25 c r ds(on), drain ? to ? source resistance ( ) v gs = 10 v v gs = 4.5 v i d, drain current (a) 0.6 0.8 1 1.2 1.4 1.6 ? 50 ? 25 0 25 50 75 100 125 150 figure 5. on ? resistance variation with temperature ? channel 2 t j , junction temperature ( c) r ds(on), drain ? to ? source resistance (normalized) v gs = 4.5 v i d = 7 a 100 1000 10000 100000 5152535 figure 6. drain ? to ? source leakage current vs. voltage ? channel 2 v ds , drain ? to ? source voltage (v) v gs = 0 v t j = 125 c t j = 150 c i dss , leakage (na)
NTMD5836NL http://onsemi.com 8 typical performance curves 0 200 400 600 800 1000 1200 010203040 figure 7. capacitance variation ? channel 2 v ds , drain ? to ? source voltage (v) c, capacitance (pf) t j = 25 c c iss c oss c rss v gs = 0 v 0 2 4 6 8 10 0 5 10 15 figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge q g , total gate charge (nc) v gs , gate ? to ? source (v) v ds , drain ? to ? source ( v ) v ds = 20 v i d = 7 a t j = 25 c q gs q gd q t 1 10 100 1000 1 10 100 figure 9. resistive switching time variation vs. gate resistance ? channel 2 r g , gate resistance ( ) t, time ( ns ) v dd = 20 v i d = 7 a v gs = 4.5 v t r t d(on) t f t d(off) 0 2 4 6 8 10 12 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 v sd , source ? to ? drain voltage (v) i s , source current (a) v gs = 0 v t j = 25 c figure 10. diode forward voltage vs. current ? channel 2 0.001 0.01 0.1 1 10 100 0.1 1 10 100 figure 11. maximum rated forward biased safe operating area ? channel 2 v ds , drain ? to ? source voltage (v) r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c dc 1 ms 100 s 10 s 1 s i d , drain current (a) 0 5 10 15 20 25 50 75 100 125 15 0 t j , starting junction temperature ( c) eas, single pulse drain ? to ? source avalanche energy (mj) i d = 21 a figure 12. maximum avalanche energy vs. starting junction temperature
NTMD5836NL http://onsemi.com 9 typical performance curves figure 13. thermal response t, pulse time (s) d = 0.5 single pulse 0.2 0.05 0.01 0.1 0.02 r(t) ( c/w) 0.01 0.1 1 10 100 0.0000001 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
NTMD5836NL http://onsemi.com 10 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NTMD5836NL/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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