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| 1. general description the nxp semiconductors SE98A measures temperature from - 40 c and +125 c with jedec grade b 1 c accuracy between +75 c and +95 c communicating via the i 2 c-bus/smbus. it is typically mounted on a dual in-line memory module (dimm) measuring the dram temperature in accordance with the new jedec (jc-42.4) mobile platform memory module thermal sensor component speci?cation. the SE98A thermal sensor operates over the v dd range of 1.7 v to 3.6 v. the SE98A does not include the 2 k spd and is designed for custom dimm where larger spd is required. the temp sensor (ts) consists of an analog-to-digital converter (adc) that monitors and updates its own temperature readings 8 times per second, converts the reading to a digital data, and latches them into the data temperature registers. user-programmable registers, such as shutdown or low-power modes and the speci?cation of temperature event and critical output boundaries, provide ?exibility for dimm temperature-sensing applications. when the temperature changes beyond the speci?ed boundary limits, the SE98A outputs an event signal. the user has the option of setting the event output signal polarity as either an active low or active high comparator output for thermostat operation, or as a temperature event interrupt output for microprocessor-based systems. the event output can even be con?gured as a critical temperature output. the SE98A supports the industry-standard 2-wire i 2 c-bus/smbus serial interface. the smbus timeout function is supported to prevent system lock-ups. manufacturer and device id registers provide the ability to con?rm the identify of the device. three address pins allow up to eight devices to be controlled on a single bus. the SE98A is an improved se98 and is comparable to the thermal sensor in the se97 but with voltage range of 1.7 v to 3.6 v. 2. features n jedec (jc-42.4) dimm temperature sensor n optimized for voltage range: 1.7 v to 3.6 v n shutdown current: 0.1 m a (typ.) and 5.0 m a (max.) n 2-wire interface: i 2 c-bus/smbus compatible, 0 hz to 400 khz n smbus alert and timeout (programmable) n esd protection exceeds 2000 v hbm per jesd22-a114, 250 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma SE98A ddr memory module temp sensor, 1.7 v to 3.6 v rev. 01 5 march 2009 product data sheet
SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 2 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v n available packages: tssop8, hwson8 and hxson8 n 11-bit adc temperature-to-digital converter with 0.125 c resolution n operating current: 250 m a (typ.) and 400 m a (max.) n programmable hysteresis threshold: 0 c, 1.5 c, 3 c, 6 c n over/under/critical temperature event output n b grade accuracy: u 0.5 c/ 1 c (typ./max.) ? +75 c to +95 c u 1 c/ 2 c (typ./max.) ? +40 c to +125 c u 2 c/ 3 c (typ./max.) ?- 40 c to +125 c 3. applications n ddr2 and ddr3 memory modules n laptops, personal computers and servers n enterprise networking n hard disk drives and other pc peripherals 4. ordering information [1] industry standard 2 mm 3mm 0.8 mm package to jedec wce-3, tdfn in 8 mm 4 mm pitch tape 4 k quantity reels. table 1. ordering information type number topside mark package name description version SE98Apw s98a tssop8 plastic thin shrink small outline package; 8 leads; body width 4.4 mm sot530-1 SE98Atp [1] 98a hwson8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 3 0.8 mm sot1069-1 SE98Atl 8al hxson8 plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 3 0.5 mm sot1052-1 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 3 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 5. block diagram fig 1. block diagram of SE98A 002aad756 scl sda event SE98A v ss smbus/i 2 c-bus interface v dd temperature register critical alarm trip upper alarm trip lower alarm trip capability manufacturing id device/rev id smbus timeout/alert configuration hysteresis shut down temp sensor lock protection event output on/off event output polarity event output status clear event output status pointer register band gap temperature sensor 11-bit ds adc por 10 v overvoltage filter a0 a1 a2 r 30 k w to 800 k w r 30 k w to 800 k w r 30 k w to 800 k w SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 4 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 6. pinning information 6.1 pinning 6.2 pin description [1] this input is overvoltage tolerant to support software write protection when applied to spd. fig 2. pin con?guration for tssop8 fig 3. pin con?guration for hwson8 fig 4. pin con?guration for hxson8 SE98Apw a0 v dd a1 event a2 scl v ss sda 002aad757 1 2 3 4 6 5 8 7 terminal 1 index area 1 a0 SE98Atp 002aad758 transparent top view 2 a1 3 a2 4 8 7 6 5 v ss v dd event scl sda terminal 1 index area 1 SE98Atl 002aad910 transparent top view 2 3 4 8 7 6 5 a0 a1 a2 v ss v dd event scl sda table 2. pin description symbol pin type description a0 [1] 1i i 2 c-bus/smbus slave address bit 0 with internal pull-down a1 2 i i 2 c-bus/smbus slave address bit 1 with internal pull-down a2 3 i i 2 c-bus/smbus slave address bit 2 with internal pull-down v ss 4 ground device ground sda 5 i/o smbus/i 2 c-bus serial data input/output (open-drain). must have external pull-up resistor. scl 6 i smbus/i 2 c-bus serial clock input/output (open-drain). must have external pull-up resistor. event 7 o thermal alarm output for high/low and critical temperature limit (open-drain). must have external pull-up resistor. v dd 8 power device power supply (1.7 v to 3.6 v) SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 5 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7. functional description 7.1 serial bus interface the SE98A uses the 2-wire serial bus (i 2 c-bus/smbus) to communicate with a host controller. the serial bus consists of a clock (scl) and data (sda) signals. the device can operate on either the i 2 c-bus standard/fast mode or smbus. the i 2 c-bus standard-mode is de?ned to have bus speeds from 0 hz to 100 khz, i 2 c-bus fast-mode from 0 hz to 400 khz, and the smbus is from 10 khz to 100 khz. the host or bus master generates the scl signal, and the SE98A uses the scl signal to receive or send data on the sda line. data transfer is serial, bidirectional, and is one bit at a time with the most signi?cant bit (msb) transferred ?rst, and a complete i 2 c-bus data is 1 byte. since scl and sda are open-drain, pull-up resistors must be installed on these pins. 7.2 slave address the SE98A uses a 4-bit ?xed and 3-bit programmable (a0, a1 and a2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. the input of each pin is sampled at the start of each i 2 c-bus/smbus access. the a0, a1 and a2 pins are pulled low internally. the a0 pin is also overvoltage tolerant, supporting 10 v software write protection when applied to the spd that shares common address lines. fig 5. slave address r/w 002aab304 0 0 1 1 a2 a1 a0 fixed hardware selectable slave address msb lsb x SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 6 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7.3 event output condition the event output indicates conditions such as the temperature crossing a prede?ned boundary. the event modes are very con?gurable and selected using the con?guration register (config). the interrupt mode or comparator mode is selected using config[0], using either tcrit/upper/lower or tcrit only temperature bands (config[2]) as modi?ed by hysteresis (config[10:9]). the upper/lower (config[6]) and tcrit (config[7]) bands can be locked. figure 6 shows an example of the measured temperature versus time, with the corresponding behavior of the event output in each of these modes. upon device power-up, the default condition for the event output is high-impedance to prevent spurious or unwanted alarms, but can be later enabled (config[3]). event output polarity can be set to active high or active low (config[1]). event status can be read (config[4]) and cleared (config[5]). ? advisory noti?cation: C nxp device: after power-up, bit 3 (1) and bit 2 or bit 0 (leave as 0 or 1) can be set at the same time (e.g., in same byte) but once bit 3 is set (1) then changing bit 2 or bit 0 has no effect on the device operation. C competitor device: does not require that bit 3 be cleared (e.g., set back to (0)) before changing bit 2 or bit 0. C work-around: in order to change bit 2 or bit 0 once bit 3 (1) is set, bit 3 (0) must be cleared in one byte and then change bit 2 or bit 0 and reset bit 3 (1) in the next byte. C se98b will allow bit 2 or bit 0 to be changed even if bit 3 is set. if the device enters shutdown mode (config[8]) with asserted event output, the output remains asserted during shutdown. 7.3.1 event pin output voltage levels and resistor sizing the event open-drain output is typically pulled up to a voltage level from 0.9 v to 3.6 v with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the event pin since it is simply an open-drain output. it could be pulled up to 0.1 v and would not affect the output. from the system perspective, there will be a practical limit. that limit will be the voltage necessary for the device monitoring the interrupt pin to detect a high on its input. a possible practical limit for a cmos input would be 0.4 v. another thing to consider is the value of the pull-up resistor. when a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the event pin. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 7 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v when t amb 3 t th(crit) and t amb < t th(crit) - t hys the event output is in comparator mode and bit 0 of config ( event output mode) is ignored. refer to t ab le 3 for ?gure note information. fig 6. event output condition 002aae324 time temperature ( c) critical event in interrupt mode event in comparator mode software interrupt clear lower boundary alarm upper boundary alarm event in critical temp only mode (1) (2) (1) (3) (4) (3) (5) * (6) (4) (2) t amb t trip(l) - t hys t trip(u) - t hys t th(crit) - t hys t trip(u) - t hys t trip(l) - t hys table 3. event output condition figure note event output boundary conditions event output temperature register status bits comparator mode interrupt mode critical temp only mode bit 15 above critical trip bit 14 above alarm window bit 13 below alarm window (1) t amb 3 t trip(l) hlh000 (2) t amb < t trip(l) - t hys llh001 (3) t amb > t trip(u) llh010 (4) t amb t trip(u) - t hys hlh000 (5) t amb 3 t th(crit) lll110 (6) t amb < t th(crit) - t hys lhh010 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 8 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7.3.2 event thresholds 7.3.2.1 alarm window the device provides a comparison window with an upper trip point and a lower trip point, programmed through the upper boundary alarm trip register (02h), and lower boundary alarm trip register (03h). the upper boundary alarm trip register holds the upper temperature trip point, while the lower boundary alarm trip register holds the lower temperature trip point as modi?ed by hysteresis as programmed in the con?guration register. when enabled, the event output triggers whenever entering or exiting (crossing above or below) the alarm window. ? advisory noti?cation: C nxp device: the event output can be cleared through the clear event bit (cevnt) or smbus alert. C competitor device: the event output can be cleared only through the clear event bit. C work-around: only clear event output using the clear event bit. C there will be no change to the nxp device. the upper boundary alarm trip should always be set above the lower boundary alarm trip. ? advisory noti?cation: C nxp device: requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the alarm window and operating event output. C competitor devices: compares the alarm limit with temperature register at any time, so they get the event output immediately when new upper or lower and event bit 3 (eoctl) are set at the same time. C work-around: wait at least 125 ms before enabling event output. C se98b will compare alarm window and temperature register immediately after setting. 7.3.2.2 critical trip the t th(crit) temperature setting is programmed in the critical alarm trip register (04h) as modi?ed by hysteresis as programmed in the con?guration register. when the temperature reaches the critical temperature value in this register (and event is enabled), the event output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. the event cannot be cleared through the clear event bit or smbus alert. the critical alarm trip should always be set above the upper boundary alarm trip. ? advisory noti?cation: C nxp device: requires one conversion cycle (125 ms) after setting the alarm window before comparing the alarm limit with temperature register to ensure that there is correct data in the temperature register before comparing with the alarm window and operating event output. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 9 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v C competitor devices: compares the alarm limit with temperature register at any time, so they get the event output immediately when new t th(crit) and event bit 3 (eoctl) are set at the same time. C work-around: wait at least 125 ms before enabling event output. intel will change nehalem bios so that t th(crit) is set for more than 125 ms before event bit 3 (eoctl) is enabled and event value is checked. 1. set t th(crit) . 2. doing something else (make sure that exceeds 125 ms). 3. enable the event output bit 3 (eoctl = 1). 4. wait 20 m s. 5. read event value. C se98b will compare alarm window and temperature register immediately after setting. 7.3.3 event operation modes 7.3.3.1 comparator mode in comparator mode, the event output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the upper boundary alarm trip register or below the value programmed in the lower boundary alarm trip register or above the critical alarm trip resister if t th(crit) only is selected). reads/writes on the registers do not affect the event output in comparator mode. the event signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. the comparator mode is useful for thermostat-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 interrupt mode in interrupt mode, event asserts whenever the temperature crosses an alarm window threshold. after such an event occurs, writing a 1 to the clear event bit in the con?guration register de-asserts the event output until the next trigger condition occurs. in interrupt mode, event asserts when the temperature crosses the alarm upper boundary. if the event output is cleared and the temperature continues to increase until it crosses the critical temperature threshold, event asserts again. because the temperature is greater than the critical temperature threshold, a clear event command does not clear the event output. once the temperature drops below the critical temperature, event de-asserts immediately. ? advisory noti?cation: C nxp device: if the event output is not cleared before the temperature goes above the critical temperature threshold event de-asserts immediately when temperature drops below the critical temperature. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 10 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v C competitor devices: if the event output is not cleared before or when the temperature is in the critical temperature threshold, event will remain asserted after the temperature drops below the critical temperature until a clear event command. C work-around: always clear the event output before temperature exceeds the critical temperature. C se98b will keep event asserted after the temperature drops below the critical temperature until a clear event command de-asserts event. 7.4 conversion rate the conversion time is the amount of time required for the adc to complete a temperature measurement for the local temperature sensor. the conversion rate is the inverse of the conversion period which describes the number of cycles the temperature measurement completes in one secondthe faster the conversion rate, the faster the temperature reading is updated. the SE98As conversion rate is at least 8 hz or 125 ms. 7.4.1 what temperature is read when conversion is in progress the SE98A has been designed to ensure a valid temperature is always available. when a read to the temperature register is initiated through the smbus, the device checks to see if the temperature conversion process (analog-to-digital conversion) is complete and a new temperature is available: ? if the temperature conversion process is complete, then the new temperature value is sent out on the smbus. ? if the temperature conversion process in not complete, then the previous temperature value is sent out on the smbus. it is possible that while the smbus master is reading the temperature register, a new temperature conversion completes. however, this will not affect the data (msb or lsb) that is being shifted out. on the next read of the temperature register the new temperature value will be shifted out. 7.5 power-up default condition after power-on, the SE98A is initialized to the following default condition: ? starts monitoring local sensor ? event register is cleared event output is pulled high by external pull-ups ? event hysteresis is defaulted to 0 c ? command pointer is defaulted to 00h ? critical temp, alarm temperature upper and lower boundary trip register are defaulted to 0 c ? capability register is defaulted to 0037h for the b-grade and vhv capability ? operational mode: comparator ? smbus register is defaulted to 00h SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 11 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7.6 device initialization SE98A temperature sensors have programmable registers, which, upon power-up, default to zero. the open-drain event output is default to being disabled, comparator mode and active low. the alarm trigger registers default to being unprotected. the con?guration registers, upper and lower alarm boundary registers and critical temperature window are defaulted to zero and need to be programmed to the desired values. smbus timeout feature defaults to being enabled and can be programmed to disable. these registers are required to be initialized before the device can properly function. except for the spd, which does not have any programmable registers, and does not need to be initialized. t ab le 4 shows the default values and the example value to be programmed to these registers. 7.7 smbus time-out the SE98A supports the smbus time-out feature. if the host holds scl low between 25 ms and 35 ms, the SE98A would reset its internal state machine to the bus idle state to prevent the system bus hang-up. this feature is turned on by default. the smbus time-out is disabled by writing a logic 1 to bit 7 of register 22h. remark: when smbus time-out is enabled, the i 2 c-bus minimum bus speed is limited by the smbus time-out timer, and goes down to only 10 khz. the SE98A has no scl driver, so it cannot hold the scl line low. 7.8 smbus alert the SE98A supports smbus alert when it is programmed for the interrupt mode and when the event polarity bit is set to logic 0. the event pin can be anded with other event or aler t signals from other slave devices to signal their intention to communicate with the host controller. when the host detects event or aler t signal low, it issues an alert response address (ara) to which a slave device would respond with its address. when there are multiple slave devices generating an alert the SE98A performs bus arbitration. if it wins the bus, it responds to the ara and then clears the event pin. remark: either in comparator mode or when the SE98A crosses the critical temperature, the host must also read the event status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. otherwise, the event pin will not get de-asserted. table 4. registers to be initialized register default value example value description 01h 0000h 0209h con?guration register ? hysteresis = 1.5 c ? event output = interrupt mode ? event output is enabled 02h 0000h 0550h upper boundary alarm trip register = 85 c 03h 0000h 1f40h lower boundary alarm trip register = - 20 c 04h 0000h 05f0h critical alarm trip register = 95 c 22h 0000h 0000h smbus register = no change SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 12 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7.9 smbus/i 2 c-bus interface the data registers in this device are selected by the pointer register. at power-up, the pointer register is set to 00, the location for the capability register. the pointer register latches the last location it was set to. each data register falls into one of three types of user accessibility: ? read only ? write only ? write/read same address. a write to this device will always include the address byte and the pointer byte. a write to any register other than the pointer register requires two data bytes. reading this device can take place either of two ways: ? if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will point to one of the temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. ? if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. the data byte has the most signi?cant bit ?rst. at the end of a read, this device can accept either acknowledge (ack) or no acknowledge (nack) from the master (no acknowledge is typically used as a signal for the slave that the master has read its last byte). it takes this device 125 ms to measure the temperature. refer to the timing diagrams in figure 8 , figure 9 , figure 10 and figure 11 on how to program the device. fig 7. how SE98A responds to smbus alert 0 0 0 1 1 a2 alert response address 1 1 0 0 s 0 0 0 start bit read acknowledge 002aab330 a1 a0 0 1 p device address not acknowledge stop bit host nack and sends a stop bit slave acknowledges and sends its slave address. the last bit of slave address is hard coded '0'. master sends a start bit, ara and a read command host detects smbus alert 1 a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 8. smbus/i 2 c-bus write to the pointer register 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write register address wa s start ack by device p stop a ack by device 002aab308 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 13 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 9. smbus/i 2 c-bus write to the pointer register followed by a write data word 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write write register address wa s start by host ack by device a ack by device (cont.) (cont.) 002aab412 123456789123456789 scl d15 d14 d13 d12 d11 d10 d9 sda d7 d6 d5 d4 d3 d2 d1 d0 most significant byte data least significant byte data a by host ack by device p stop by host d8 a ack by device a = ack = acknowledge bit. na = not acknowledge bit. w = write bit = 0. r = read bit = 1. fig 10. smbus/i 2 c-bus write to pointer register followed by a repeat start and an immediate data word read 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write read register address wa s start by host ack by device a ack by device (cont.) (cont.) 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra sr repeated start by host ack by device (cont.) (cont.) 002aab413 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop by host na nack by host SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 14 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7.10 hot plugging the SE98A can be used in hot plugging applications. internal circuitry prevents damaging current back?ow through the device when it is powered down, but with the i 2 c-bus, event or address pins still connected. the open-drain sda and event pins (scl and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver con?ict and bus contention. the 50 ns noise ?lter will ?lter out any insertion glitches from the state machine, which is very robust and not prone to false operation. the device needs a proper power-up sequence to reset itself, not only for the device i 2 c-bus and i/o initial states, but also to load speci?c pre-de?ned data or calibration data into its operational registers. the power-up sequence should occur correctly with a fast ramp rate and the i 2 c-bus active. the SE98A might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. if the scl line is held low, the part will not exit the power-on reset mode since the part is held in reset until scl is released. a = ack = acknowledge bit. na = not acknowledge bit. w = write bit = 0. r = read bit = 1. fig 11. smbus/i 2 c-bus word read from register with a pre-set pointer 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra ack by device (cont.) (cont.) 002aab414 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop na nack by host s start by host SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 15 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8. register descriptions 8.1 register overview this section describes all the registers used in the SE98A. the registers are used for latching the temperature reading, storing the low and high temperature limits, con?guring, the hysteresis threshold and the adc, as well as reporting status. the device uses the pointer register to access these registers. read registers, as the name implies, are used for read only, and the write registers are for write only. any attempt to read from a write-only register will result in reading zeroes. writing to a read-only register will have no effect on the read even though the write command is acknowledged. the pointer register is an 8-bit register. all other registers are 16-bit. a write to reserved registers my cause unexpected results which may result in requiring a reset by removing and re-applying its power. table 5. register summary address por state register name n/a n/a pointer register 00h 0037h capability register (b grade = 0037h) 01h 0000h con?guration register 02h 0000h upper boundary alarm trip register 03h 0000h lower boundary alarm trip register 04h 0000h critical alarm trip register 05h n/a temperature register 06h 1131h manufacturer id register 07h a102h device id/revision register 08h to 21h 0000h reserved registers 22h 0000h smbus register 23h to ffh 0000h reserved registers SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 16 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.2 capability register (00h, 16-bit read-only) table 6. capability register (address 00h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu[9:2] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol rfu[1:0] vhv tres[1:0] wrng hacc bcap reset 00110111 access rrrrrrrr table 7. capability register (address 00h) bit description bit symbol description 15:6 rfu reserved for future use. must be zero. 5 vhv high voltage standoff for pin a0. 1 this part can support a voltage up to 10 v on the a0 pin to support jc42.4 ballot 1435.00. 4:3 tres temperature resolution. 10 0.125 c lsb (11-bit) 2 wrng wider range. 1 can read temperatures below 0 c and set sign bit accordingly 1 hacc higher accuracy (set during manufacture). 1 b grade accuracy 0 bcap basic capability. 1 has alarm and critical trips interrupt capability. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 17 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.3 con?guration register (01h, 16-bit read/write) table 8. con?guration register (address 01h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu hen[1:0] shmd default 00000000 access rrrrrr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol ctlb awlb cevnt estat eoctl cvo ep emd default 00000000 access r/w r/w r/w r/w r/w r/w r/w r/w table 9. con?guration register (address 01h) bit description bit symbol description 15:11 rfu reserved for future use; must be 0. 10:9 hen hysteresis enable 00 disable hysteresis (default) 01 enable hysteresis at 1.5 c 10 enable hysteresis at 3 c 11 enable hysteresis at 6 c when enabled, hysteresis is applied to temperature movement around trigger points. for example, consider the behavior of the above alarm window bit (bit 14 of the temperature register) when the hysteresis is set to 3 c. as the temperature rises, bit 14 will be set to 1 (temperature is above the alarm window) when the temperature register contains a value that is greater than the value in the alarm temperature upper boundary register. if the temperature decreases, bit 14 will remain set until the measured temperature is less than or equal to the value in the alarm temperature upper boundary register minus 3 c. (refer to figure 6 and t ab le 10 ). similarly, the below alarm window bit (bit 13 of the temperature register) will be set to 0 (temperature is equal to or above the alarm window lower boundary trip register) when the value in the temperature register is equal to or greater than the value in the alarm temperature lower boundary register. as the temperature decreases, bit 13 will be set to 1 when the value in the temperature register is equal to or less than the value in the alarm temperature lower boundary register minus 3 c. note that hysteresis is also applied to event pin functionality. when either of the critical trip or alarm window lock bits is set, these bits cannot be altered until unlocked. 8 shmd shutdown mode. 0 enabled temperature sensor (default) 1 disabled temperature sensor when shut down, the thermal sensor diode and analog-to-digital converter (adc) are disabled to save power, no events will be generated. when either of the critical trip or alarm window lock bits is set, this bit cannot be set until unlocked. however, it can be cleared at any time. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 18 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 7 ctlb critical trip lock bit. 0 critical alarm trip register is not locked and can be altered (default). 1 critical alarm trip register settings cannot be altered. this bit is initially cleared. when set, this bit will return a 1, and remains locked until cleared by internal power-on reset. this bit can be written with a single write and do not require double writes. 6 awlb alarm window lock bit. 0 upper and lower alarm trip registers are not locked and can be altered (default). 1 upper and lower alarm trip registers setting cannot be altered. this bit is initially cleared. when set, this bit will retur n a 1 and remains locked until cleared by internal power-on reset. this bit can be written with a single write and does not require double writes. 5 cevnt clear event (write only). 0 no effect (default). 1 clears active event in interrupt mode. writing to this register has no effect in comparator mode. when read, this register always returns zero. 4 estat event status (read only). 0 event output condition is not being asserted by this device (default). 1 event output pin is being asserted by this device due to alarm window or critical trip condition. the actual event causing the event can be determined from the read temperature register. interrupt events can be cleared by writing to the clear event bit. writing to this bit will have no effect. 3 eoctl event output control. 0 event output disabled (default). 1 event output enabled. when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 2 cvo critical event only. 0 event output on alarm or critical temperature event (default) 1 event only if temperature is above the value in the critical temperature register when the critical trip or alarm window lock bit is set, this bit cannot be altered until unlocked. ? advisory note: C jedec speci?cation requires only the alarm window lock bit to be set. C work-around: clear both critical trip and alarm window lock bits. C future 1.7 v to 3.6 v se98b will require only the alarm window lock bit to be set. table 9. con?guration register (address 01h) bit description continued bit symbol description SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 19 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 1ep event polarity. 0 active low (default). 1 active high. when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 0 emd event mode. 0 comparator output mode (default) 1 interrupt mode when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. table 9. con?guration register (address 01h) bit description continued bit symbol description table 10. hysteresis enable action below alarm window bit (bit 13) above alarm window bit (bit 14) above critical trip bit (bit 15) temperature slope threshold temperature temperature slope threshold temperature temperature slope threshold temperature sets falling t trip(l) - t hys rising t trip(u) rising t th(crit) clears rising t trip(l) falling t trip(u) - t hys falling t th(crit) - t hys fig 12. hysteresis: how it works 002aac799 current temperature time temperature set clear clear set clear clear set clear below alarm window (register 05h; bit 13 = baw bit) above alarm window (register 05h; bit 14 = aaw bit) above critical trip (register 05h; bit 15 = act bit) lower alarm threshold upper alarm threshold critical alarm threshold hysteresis hysteresis hysteresis SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 20 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.4 temperature format the 16-bit value used in the following trip point set and temperature read-back registers is 2s complement with the least signi?cant bit (lsb) equal to 0.0625 c. for example: ? a value of 019ch will represent 25.75 c ? a value of 07c0h will represent 124 c ? a value of 1e64h will represent - 25.75 c. the resolution is 0.125 c. the unused lsb (bit 0) is set to 0. bit 11 will have a resolution of 128 c. the upper 3 bits of the temperature register indicate trip status based on the current temperature, and are not affected by the status of the event output. t ab le 11 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b. table 11. degree celsius and temperature data register temperature content of temperature data register status bits = 000b status bits = 111b binary hex binary hex +125 c 000 0 01111101 000 0 07d0h 111 0 01111101 000 0 e7d0h +25 c 000 0 00011001 000 0 0190h 111 0 00011001 000 0 e190h +1 c 000 0 00000001 000 0 0010h 111 0 00000001 000 0 e010h +0.25 c 000 0 00000000 010 0 0004h 111 0 00000000 010 0 e004h +0.125 c 000 0 00000000 001 0 0002h 111 0 00000000 001 0 e002h 0 c 000 0 00000000 000 0 0000h 111 0 00000000 000 0 e000h - 0.125 c 000 1 11111111 111 0 1ffeh 111 1 11111111 111 0 fffeh - 0.25 c 000 1 11111111 110 0 1ffch 111 1 11111111 110 0 fffch - 1 c 000 1 11111111 000 0 1ff0h 111 1 11111111 000 0 fff0h - 20 c 000 1 11110100 000 0 1f40h 111 1 11110100 000 0 ff40h - 25 c 000 1 11100111 000 0 1e70h 111 1 11100111 000 0 fe70h - 55 c 000 1 11001001 000 0 1c90h 111 1 11001001 000 0 fc90h SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 21 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.5 temperature trip point registers 8.5.1 upper boundary alarm trip register (16-bit read/write) the value is the upper threshold temperature value for alarm mode. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid super?uous interrupt activity. table 12. upper boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign ubt[9:6] reset 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ubt[5:0] rfu reset 00000000 access r/w r/w r/w r/w r/w r/w r r table 13. upper boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 ubt upper boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 22 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.5.2 lower boundary alarm trip register (16-bit read/write) the value is the lower threshold temperature value for alarm mode. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off interrupts until a known state can be obtained to avoid super?uous interrupt activity. 8.5.3 critical alarm trip register (16-bit read/write) the value is the critical temperature. the data format is 2s complement with bit 2 = 0.25 c. rfu bits will always report zero. table 14. lower boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign lbt[9:6] reset 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol lbt[5:0] rfu reset 00000000 access r/w r/w r/w r/w r/w r/w r r table 15. lower boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 lbt lower boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0 table 16. lower boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu sign ct[9:6] reset 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol ct[5:0] rfu reset 00000000 access r/w r/w r/w r/w r/w r/w r r table 17. critical alarm trip register bit description bit symbol description 15:13 rfu reserved; always 0 12 sign sign (msb) 11:2 ct critical alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always 0 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 23 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.6 temperature register (16-bit read-only) table 18. temperature register bit allocation bit 15 14 13 12 11 10 9 8 symbol act aaw baw sign temp[10:7] reset 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol temp[6:0] rfu reset 00000000 access rrrrrrrr table 19. temperature register bit description bit symbol description 15 act above critical trip. increasing t amb : 0 t amb SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 25 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 8.9 smbus register table 22. smbus time-out register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu reset 0 0000000 access r rrrrrrr bit 7 6 5 4 3 2 1 0 symbol stmout rfu salrt reset 0 0000000 access r/wrrrrrrr/w table 23. smbus time-out register bit description bit symbol description 15:8 rfu reserved; always 0 7 stmout smbus time-out. 0 smbus time-out is enabled (default) 1 disable smbus time-out when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 6:1 rfu reserved; always 0 0 salrt smbus alert. 0 smbus alert is enabled (default) 1 disable smbus alert when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 26 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 9. application design-in information in a typical application, the SE98A behaves as a slave device and interfaces to the master (or host) via the scl and sda lines. the host monitors the event output pin, which is asserted when the temperature reading exceeds the programmed values in the alarm registers. the a0, a1 and a2 pins are directly connected to the shared spds a0, a1 and a2 pins, otherwise they must be pulled high or low. the sda and scl serial interface pins are open-drain and require pull-up resistors, and are able to sink a maximum current of 3 ma with a voltage drop less than 0.4 v. typical pull-up values for scl and sda are 10 k w , but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. fig 13. typical application 002aad900 host controller SE98A a0 a1 a2 scl sda event v dd 10 k w (3 ) v ss slave master spd a0 a1 a2 v dd v ss scl sda fig 14. SE98A interfacing with 1.1 v host controller 002aad759 host controller SE98A a0 a1 a2 scl sda event v dd 10 k w v ss 3.3 v 0.1 m f 10 k w pca9509 mother board 0.1 m f v cc(b) b2 b1 en v cc(a) a2 a1 10 k w 10 k w scl sda event 0.1 m f 1.1 v SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 27 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 9.1 SE98A in memory module application figure 15 shows the SE98A being placed in the memory module application with the spd. the SE98A is centered in the memory module to provide the function to monitor the temperature of the dram. in the event of overheat, the SE98A triggers the event output and the memory controller can throttle the memory bus to slow the dram, or the cpu can increase the refresh rate for the dram. the memory controller can also read the SE98A and watch the dram thermal behavior. 9.2 layout consideration the SE98A does not require any additional components other than the host controller to measure temperature. a 0.1 m f bypass capacitor between the v dd and v ss pins is located as close as possible to the power and ground pins for noise protection. 9.3 thermal considerations in general, self-heating is the result of power consumption and not a concern, especially with the SE98A, which consumes very low power. in the event the sda and event pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 c. equation 1 is the formula to calculate the effect of self-heating: (1) where: t d = t j - t amb t j = junction temperature t amb = ambient temperature r th(j-a) = package thermal resistance v ol1 = sda output low voltage v ol2 = event output low voltage i ol1 = sda output current low i ol2 = event output current low. fig 15. system application 002aad760 SE98A event dimm dram dram dram dram memory controller smbus cpu spd sda scl t d r th j - a () v dd i dd () v ol1 i ol1 () v ol2 i ol2 () ++ [] = SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 28 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 10. limiting values 11. characteristics table 24. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.3 +4.2 v v n voltage on any other pin sda, scl, event pins - 0.3 +4.2 v v a0 voltage on pin a0 overvoltage input; a0 pin - 0.3 +12.5 v i sink sink current at sda, scl, event pins - 1 +50.0 ma t j(max) maximum junction temperature - 150 c t stg storage temperature - 65 +165 c table 25. characteristics v dd = 1.7 v to 3.6 v; t amb = - 40 c to +125 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit t acc temperature accuracy b grade temperature accuracy; v dd = 1.7 v to 3.6 v t amb =75 cto95 c - 1.0 < 0.5 +1.0 c t amb =40 c to 125 c - 2.0 < 1 +2.0 c t amb = - 40 c to +125 c - 3.0 < 2 +3.0 c t res temperature resolution - 0.125 - c i dd(av) average supply current - 250 400 m a i dd(stb) standby supply current smbus inactive - 0.1 5 m a t conv conversion period - 100 120 ms e f(conv) conversion rate error percentage error in programmed data - 30 - +30 % i lil low-level input leakage current pins a0, a1, a2; v i =v ss - 1.0 - +1.0 m a i pd pull-down current internal; pins a0, a1, a2; v i = 0.3v dd to v dd 0.05 - 4.0 m a z il low-level input impedance pins a0, a1, a2; v i < 0.3v dd 30 - - k w z ih high-level input impedance pins a0, a1, a2; v i 3 0.3v dd 800 - - k w v dd supply voltage 1.7 1.8 or 2.5 or 3.3 3.6 v SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 29 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v [1] high-voltage input voltage applied to pin a0 during rwp and crwp operations of the equivalent spd-included parts. the jedec speci?cation is 7 v (min.) and 10 v (max.). when v dd is 3.6 v, then v i(ov) > 4.8 v + v dd or > 4.8 v + 3.6 v then the minimum voltage is 8.4 v. table 26. smbus dc characteristics v dd = 1.7 v to 3.6 v; t amb = - 20 c to +120 c; unless otherwise speci?ed. these speci?cations are guaranteed by design. symbol parameter conditions min typ max unit v ih high-level input voltage scl, sda; v dd = 1.7 v to 3.6 v 0.7v dd -v dd +1 v v il low-level input voltage scl, sda; v dd = 1.7 v to 3.6 v - - 0.3v dd v v i(ov) overvoltage input voltage pin a0; v i(ov) - v dd > 4.8 v [1] 7.0 - 10 v v th(por)h high-level power-on reset threshold voltage - - 1.7 v v th(rec)por power-on reset recovery threshold voltage for device reset - - 0.5 v i ol(sink)event low-level output sink current on pin event v ol = 0.4 v 6 - - ma i ol(sink)(sda) low-level output sink current on pin sda v ol = 0.5 v 3 - - ma i loh high-level output leakage current v oh =v dd - - 1.0 m a i lih high-level input leakage current pins scl, sda; v i =v dd or v ss - 1.0 - +1.0 m a i lil low-level input leakage current pins scl, sda; v i =v dd or v ss - 1.0 - +1.0 m a c i input capacitance scl, sda pins - 5 10 pf a. i 2 c-bus inactive b. i 2 c-bus active fig 16. average supply current 150 250 350 i dd(av) ( m a) 50 t amb ( c) - 50 125 002aae374 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v 150 250 350 i dd(av) ( m a) 50 t amb ( c) - 50 125 002aae375 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 30 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v i 2 c-bus and temp sensor inactive. v dd = 1.7 v to 3.6 v. fig 17. shutdown supply current fig 18. typical temperature accuracy v ol = 0.4 v. v ol = 0.5 v. fig 19. event output current fig 20. sda output current v dd = 3.0 v to 3.6 v. v dd = 3.0 v to 3.6 v. fig 21. conversion rate fig 22. conversion period 1 3 5 i sd(vdd) ( m a) - 1 t amb ( c) - 40 120 80 040 002aad881 v dd = 3.6 v 3.0 v 2.3 v 1.7 v - 1.0 1.0 3.0 t acc ( c) - 3.0 t amb ( c) 002aae376 0 - 50 125 100 75 50 25 0 - 25 2.0 - 2.0 t amb ( c) - 50 125 002aae377 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v 10 20 30 i ol(sink)event (ma) 0 t amb ( c) - 50 125 002aae378 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v 10 20 30 i ol(sink)sda (ma) 0 t amb ( c) - 40 120 80 040 002aad886 9 11 7 13 15 5 conversion rate (conv/s) 60 120 100 80 140 t conv (ms) 002aad887 t amb ( c) - 40 120 80 040 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 31 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v for temp sensor conversion. from 25 c (air) to 120 c (oil bath). (1) tssop8 (2) hwson8 fig 23. average power-on threshold voltage fig 24. package thermal response v dd = 3.3 v + 150 mv (p-p); 0.1 m f ac coupling capacitor; no decoupling capacitor; t amb =25 c. fig 25. temperature error versus power supply noise frequency 2.0 1.5 2.5 3.0 v th (v) 1.0 t amb ( c) - 40 120 80 040 002aad889 40 80 120 thermal response (%) 0 time (s) 05 4 23 1 002aad891 (1) (2) noise frequency (hz) 10 2 10 8 10 7 10 6 10 3 10 5 10 4 002aad892 1 3 5 temp error (?c) - 1 a. v i = 0.3v dd ; pins a0, a1, a2 b. v i = 0.7v dd ; pins a0, a1, a2 fig 26. typical pull-down current t amb ( c) - 50 125 002aae379 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v 1.0 2.0 3.0 i pd ( m a) 0 t amb ( c) - 50 125 002aae380 100 75 50 25 0 - 25 v dd = 3.6 v 3.0 v 2.3 v 1.7 v 1.0 2.0 3.0 i pd ( m a) 0 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 32 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v [1] delay from sda stop to sda start. [2] delay from sda start to ?rst scl high-to-low transition. [3] delay from scl high-to-low transition to sda edges. [4] a device must internally provide a hold time of at least 200 ns for sda signal (referenced to the v ih(min) of the scl signal) to bridge the unde?ned region of the falling edge of scl. [5] delay from scl low-to-high transition to restart sda. table 27. smbus ac characteristics v dd = 1.7 v to 3.6 v; t amb = - 40 c to +125 c; unless otherwise speci?ed. these speci?cations are guaranteed by design. the ac speci?cations fully meet or exceed smbus 2.0 speci?cations, but allow the bus to interface with the i 2 c-bus from dc to 400 khz. symbol parameter conditions standard mode fast mode unit min max min max f scl scl clock frequency - 100 - 400 khz t low low period of the scl clock 30 % to 30 % 4.7 100 1.3 - m s t high high period of the scl clock 70 % to 70 % 4 - 0.6 - m s t buf bus free time between a stop and start condition [1] 4.7 - 1.3 - m s t hd;sta hold time (repeated) start condition 30 % of sda to 70 % of scl [2] 4 - 0.6 - m s t h(q) data output hold time [3] 300 - 300 - ns t hd;dat data hold time [1] [4] 0-0-ns t vd;dat data valid time from clock 200 - 200 - ns t su;dat data set-up time 250 - 100 - ns t su;sta set-up time for a repeated start condition [5] 4.7 - 0.25 - m s t su;sto set-up time for stop condition 4 - 0.6 - m s t r rise time of both sda and scl signals - 1000 - 300 ns t f fall time of both sda and scl signals - 300 - 300 ns t f(o) output fall time - - - 250 ns t to(smbus) smbus time-out time low period to reset smbus 25 35 25 35 ms t por power-on reset pulse time power supply falling 0.5 - 0.5 - m s SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 33 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v v il = 0.3v dd v ih = 0.7v dd fig 27. de?nition of timing for f/s-mode devices on the i 2 c-bus 002aac938 t f 70 % 30 % sda t f 70 % 30 % s t r 70 % 30 % 70 % 30 % t hd;dat scl 1 / f scl 1 st clock cycle 70 % 30 % 70 % 30 % t r t vd;dat cont. cont. sda scl t su;sta t hd;sta sr t sp t su;sto t buf p s t high 9 th clock t hd;sta t low 70 % 30 % t vd;ack 9 th clock t su;dat SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 34 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 12. package outline fig 28. package outline sot530-1 (tssop8) unit a 1 a max. a 2 a 3 b p l h e l p wy v ce d (1) e (2) z (1) q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.85 0.30 0.19 0.20 0.13 3.1 2.9 4.5 4.3 0.65 6.5 6.3 0.70 0.35 8 0 0.1 0.1 0.1 0.94 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.7 0.5 sot530-1 mo-153 00-02-24 03-02-18 w m b p d z e 0.25 14 8 5 q a a 2 a 1 l p (a 3 ) detail x l h e e c v m a x a y 2.5 5 mm 0 scale tssop8: plastic thin shrink small outline package; 8 leads; body width 4.4 mm sot530-1 1.1 pin 1 index SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 35 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v fig 29. package outline sot1069-1 (hwson8) references outline version european projection issue date iec jedec jeita sot1069-1 mo-229 sot1069-1 note 1. dimension a is including plating thickness. the package footprint is compatible with jedec mo229 dimensions (mm are the original dimensions) hwson8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm unit mm max nom min 0.8 0.04 2.1 2.0 1.9 1.6 1.4 0.5 3.1 3.0 2.9 1.6 1.4 0.45 0.35 0.3 0.2 0.1 0.05 0.05 a (1) a 1 b d d 1 e e 1 e l v y y 1 0 1 2 mm scale terminal 1 index area d h e 1/2 e e h l 85 14 b a d e terminal 1 index area x b a b v m detail x a a 1 c y 1 c y (8 ) 08-06-11 08-07-10 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 36 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v fig 30. package outline sot1052-1 (hxson8) references outline version european projection issue date iec jedec jeita sot1052-1 mo-229 sot1052-1 note 1. dimension a is including plating thickness. the package footprint is compatible with jedec mo229 dimensions (mm are the original dimensions) hxson8: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.5 mm unit mm max nom min 0.5 0.04 2.1 2.0 1.9 1.6 1.4 0.5 3.1 3.0 2.9 1.6 1.4 0.45 0.35 0.3 0.2 0.1 0.05 0.05 a (1) a 1 b d d 1 e e 1 e l v y y 1 0 1 2 mm scale terminal 1 index area d h e 1/2 e e h l 85 14 b a d e terminal 1 index area x b a b v m detail x a a 1 c y 1 c y (8 ) 08-01-11 08-03-11 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 37 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 38 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 31 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 28 and 29 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 31 . table 28. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 29. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 39 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 31. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 30. abbreviations acronym description adc analog-to-digital converter ara alert response address bios basic input/output system cdm charged-device model cmos complementary metal-oxide semiconductor cpu central processing unit crwp clear reversible write protection ddr double data rate ddr2 double data rate 2 ddr3 double data rate 3 dimm dual in-line memory module dram dynamic random access memory esd electrostatic discharge hbm human body model i 2 c-bus inter ic bus i/o input/output lsb least signi?cant bit mm machine model msb most signi?cant bit SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 40 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 15. revision history rdimm registered dual in-line memory module so-dimm small outline dual in-line memory module pc personal computer por power-on reset rwp reversible write protection smbus system management bus spd serial presence detect table 30. abbreviations continued acronym description table 31. revision history document id release date data sheet status change notice supersedes SE98A_1 20090305 product data sheet - - SE98A_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 5 march 2009 41 of 42 nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 16.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. nxp semiconductors SE98A ddr memory module temp sensor, 1.7 v to 3.6 v ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 5 march 2009 document identifier: SE98A_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 serial bus interface . . . . . . . . . . . . . . . . . . . . . . 5 7.2 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.3 event output condition . . . . . . . . . . . . . . . . . . 6 7.3.1 event pin output voltage levels and resistor sizing. . . . . . . . . . . . . . . . . . . . . . . 6 7.3.2 event thresholds . . . . . . . . . . . . . . . . . . . . . . 8 7.3.2.1 alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.2.2 critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.3 event operation modes . . . . . . . . . . . . . . . . . . . 9 7.3.3.1 comparator mode. . . . . . . . . . . . . . . . . . . . . . . 9 7.3.3.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.4 conversion rate. . . . . . . . . . . . . . . . . . . . . . . . 10 7.4.1 what temperature is read when conversion is in progress . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.5 power-up default condition . . . . . . . . . . . . . . . 10 7.6 device initialization . . . . . . . . . . . . . . . . . . . . . 11 7.7 smbus time-out . . . . . . . . . . . . . . . . . . . . . . . 11 7.8 smbus alert . . . . . . . . . . . . . . . . . . . . . . . . 11 7.9 smbus/i 2 c-bus interface . . . . . . . . . . . . . . . . 12 7.10 hot plugging . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 register descriptions . . . . . . . . . . . . . . . . . . . 15 8.1 register overview . . . . . . . . . . . . . . . . . . . . . . 15 8.2 capability register (00h, 16-bit read-only). . . . 16 8.3 con?guration register (01h, 16-bit read/write) 17 8.4 temperature format . . . . . . . . . . . . . . . . . . . . 20 8.5 temperature trip point registers . . . . . . . . . . . 21 8.5.1 upper boundary alarm trip register (16-bit read/write). . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5.2 lower boundary alarm trip register (16-bit read/write). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5.3 critical alarm trip register (16-bit read/write) . . . . . . . . . . . . . . . . . . . . . . 22 8.6 temperature register (16-bit read-only) . . . . . 23 8.7 manufacturers id register (16-bit read-only) . . . . . . . . . . . . . . . . . . . . . . 24 8.8 device id register . . . . . . . . . . . . . . . . . . . . . . 24 8.9 smbus register . . . . . . . . . . . . . . . . . . . . . . . . 25 9 application design-in information . . . . . . . . . 26 9.1 SE98A in memory module application . . . . . . 27 9.2 layout consideration . . . . . . . . . . . . . . . . . . . 27 9.3 thermal considerations . . . . . . . . . . . . . . . . . 27 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 28 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 34 13 soldering of smd packages . . . . . . . . . . . . . . 37 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 37 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 37 13.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 37 13.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 38 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 40 16 legal information . . . . . . . . . . . . . . . . . . . . . . 41 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 16.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 17 contact information . . . . . . . . . . . . . . . . . . . . 41 18 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 |
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