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ds07-12616-1e fujitsu semiconductor data sheet copyright?2007 fujitsu li mited all rights reserved ?check sheet? is seen at the following support page url : http://www.fujitsu.com/global/services/micr oelectronics/product/micom/support/index.html ?check sheet? lists the minimal require ment items to be checked to prevent problems beforehand in system development. be sure to refer to the ?check sheet? for the latest cautions on development. 8-bit proprietary microcontrollers cmos f 2 mc-8fx mb95120 series mb95f128d/f128e/fv100d-101/fv100d-102 description the mb95120 series is general-purpose, single-chip micr ocontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions. note : f 2 mc is the abbreviation of fuji tsu flexible microcontroller. feature ? f 2 mc-8fx cpu core instruction set optimized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instruction bit manipulation instructions etc. ? clock main clock main pll clock sub clock sub pll clock ? timer 8/16-bit compound timer 2 channels 16-bit reload timer 8/16-bit ppg 2 channels 16-bit ppg 2 channels timebase timer watch prescaler (continued)
mb95120 series 2 (continued) ? lin-uart full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? uart/sio full duplex double buffer clock asynchronous (uart) or clock synchronous (sio) serial data transfer capable ? i 2 c* built-in wake-up function ? external interrupt interrupt by edge detection (rising, falling, or both edges can be selected) can be used to recover from lo w-power consumption (standby) modes. ? 8/10-bit a/d converter 8-bit or 10-bit resolution can be selected ? lcd controller (lcdc) 40 seg 4 com (max 160 pixels) with blinking function built-in division resistance for lcd drive/booster : selected by mask option ? low-power consumption (standby) mode stop mode sleep mode watch mode timebase timer mode ? i/o port the number of maximum ports : max 87 port configuration ? general-purpose i/o ports (n-ch open drain) : 2 ports ? general-purpose i/o ports (cmos) : 85 ports ? programmable input voltage levels of port cmos input level / hysteresis input level ? dual operation flash memory erase/write and read can be executed in the differ ent bank (upper bank/lower bank) at the same time. ? flash memory security function protects the content of flash memo ry (flash memory product only) * : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips.
mb95120 series 3 product lineup (continued) mb95f128d mb95f128e type flash memory product rom capacity 60 kbytes ram capacity 2 kbytes reset output no option* 2 clock system dual clock low voltage detection reset no cpu functions number of basic instructions : 136 instruction bit length : 8 bits instruction length : 1 to 3 bytes data bit length : 1, 8, and 16 bits minimum instruction execution time : 61.5 ns (at machine clock frequency 16.25 mhz) interrupt processing time : 0.6 s (at machine clock frequency 16.25 mhz) peripheral functions ports (max 87 ports) general-purpose i/o port (n-ch open drain) : 2 ports general-purpose i/o port (cmos) : 85 ports programmable input voltage levels of port cmos input level / hysteresis input level timebase timer interrupt cycle : 0.5 ms, 2.1 ms, 8. 2 ms, 32.8 ms (at main oscillation clock 4 mhz) watchdog timer reset generated cycle at main oscillation clock 10 mhz : min 105 ms at sub oscillation clock 32.768 khz : min 250 ms wild register capable of replacing 3 bytes of rom data i 2 c master/slave sending and receiving bus error function and arbitration function detecting transmitting direction function start condition repeated generat ion and detection functions built-in wake-up function uart/sio data transfer capable in uart/sio full duplex double buffer variable data length (5/6/7/8-bit), built-in baud rate generator nrz type transfer forma t, error detected function lsb-first or msb-first can be selected clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin-uart dedicated reload timer allowing a wide r ange of communication speeds to be set full duplex double buffer clock asynchronous (uart) or clock synchr onous (sio) serial data transfer capable lin functions available as the lin master or lin slave 8/10-bit a/d converter (12 channels) 8-bit or 10-bit resolution can be selected parameter part number* 1
mb95120 series 4 (continued) *1 : mask rom products are currently under consideration. *2 : for details of option, refer to ? mask option?. *3 : embedded algorithm is a trade ma rk of advanced micro devices inc. note : part number of evaluation product in mb95120 se ries is mb95fv100d-101 (internal division resistance included) or mb95fv100d-102 (lcd booster circuit in cluded) . when using it, the mcu board (mb2146- 301a or MB2146-302A) is required. mb95f128d mb95f128e peripheral functions lcd controller (lcdc) com output : 4 (max) seg output : 40 (max) lcd drive power supply (bias) pin : 4 40 seg 4 com : 160 pixels can be displayed duty lcd mode with blinking function division resistance for lcd drive/ booster : selected by mask option built-in internal division resistance : selected by mask option built-in booster circuit : selected by mask option 16-bit reload timer two clock modes and two counter operating modes can be selected square wave form output count clock : 7 internal clocks and external clock can be selected counter operating mode : reload mode or one-shot mode can be selected 8/16-bit compound timer (2 channels) each channel of the timer ca n be used as ?8-bit timer 2 channels? or ?16-bit timer 1 channel? built-in timer function, pwc function, pwm function, capture function and square wave form output count clock : 7 internal clocks and external clock can be selected 16-bit ppg (2 channels) pwm mode or one-shot mode can be selected counter operating clock : eight selectable clock sources support for external trigger start 8/16-bit ppg (2 channels) each channel of the ppg can be used as ? 8-bit ppg 2 channels ? or ? 16-bit ppg 1 channel ? counter operating clock : eight selectable clock sources watch counter count clock : four selectable clock s ources (125 ms, 250 ms, 500 ms, or 1 s) counter value can be set from 0 to 63 (capab le of counting for 1 minute when selecting clock source 1 second and se tting counter value to 60) watch prescaler 4 selectable interval times (125 ms, 250 ms, 500 ms, or 1 s) external interrupt (12 channels) interrupt by edge detection (rising, fa lling, or both edges can be selected) can be used to recover from standby modes flash memory supports automatic progra mming, embedded algorithm tm * 3 write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of write/erase cycles (minimum) : 10000 times data retention time : 20 years erase can be performed on each block block protection with external programming voltage dual operation flash memory flash security feature for prot ecting the content of the flash standby mode sleep, stop, watch, and timebase timer parameter part number* 1
mb95120 series 5 oscillation stabilization wait time the initial value of the main clock oscillation stabilization wait time is fixed to the maximum value. the maximum value is shown as follows. packages and corresponding products : available : unavailable oscillation stabilization wait time remarks (2 14 ? 2) /f ch approx. 4.10 ms (at main oscillation clock 4 mhz) mb95f128d/f128e mb95fv100d-101/102 fpt-100p-m20 fpt-100p-m06 bga-224p-m08 package part number
mb95120 series 6 differences among products and notes on selecting products ? notes on using evaluation products the evaluation product has not only the functions of th e mb95120 series but also those of other products to support software development for mu ltiple series and models of the f 2 mc-8fx family. the i/o addresses for peripheral resources not used by th e mb95120 series are therefore access-b arred. read/write access to these access-barred addresses may cause per ipheral resources supposed to be unused to operate, resulting in unexpected malfunctions of hardware or software. particularly, do not use word access to odd numbered by te address in the prohibited areas (if these access are used, the address may be read or written unexpectedly). also, as the read values of prohibited addresses on the evaluation product are different to the values on the flash memory and mask rom products, do not use these values in the program. the functions corresponding to certain bits in single- byte registers may not be supported on flash memory products. however, reading or writing to these bits w ill not cause malfunction of the hardware. also, as the evaluation and flash memory products are designed to have identical software operation, no particular precautions are required. ? difference of memory spaces if the amount of memory on the evaluat ion product is different from that of the flash memory product, carefully check the difference in the amount of memory from th e model to be actually used when developing software. for details of memory space, refer to ? cpu core?. ? current consumption for details of current consumption, refer to ? electrical characteristics?. ? package for details of information on each package, refer to ? packages and corresponding products? and ? package dimensions?. ? operating voltage the operating voltage are different between the evaluation and flash memory products. for details of operating voltage, refer to ? electrical characteristics?.
mb95120 series 7 pin assignment (continued) (top view) (fpt-100p-m20) note : the p90 to p95 are not used as a general-purpose ports in the mb95f128e. v ss pg0 p00/int00 p01/int01 p02/int02 p03/int03 p04/int04 p05/int05 p06/int06 p07/int07 p12/uck0 p13/trg0/adtg p14/ppg0 p20/ppg00 p21/ppg01 av cc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 10099 98 97 96 95 94 p22/to00 p23/to01 p24/ec0 p10/ui0 p11/uo0 p50/scl0 p51/sda0 avr p52/ppg1 av ss p30/an00 p31/an01 p32/an02 p33/an03 p34/an04 p35/an05 p36/an06 p37/an07 p40/an08 p43/an11 p53/trg1 p70/to0 p71/ti0 p67/seg39/sin x1a p66/seg38/sot p65/seg37/sck p64/seg36/ec1 p41/an09 p42/an10 p63/seg35/to11 p62/seg34/to10 x0a rst v cc p90/v3 p91/v2 p92/v1 p93/v0 p94/c0 p95/c1 pa0/com0 pa1/com1 pa2/com2 pb1/seg01 pb2/seg02 pb3/seg03 pb4/seg04 pb5/seg05 v cc pb6/seg06 pb7/seg07 pc0/seg08 pa3/com3 pb0/seg00 pc1/seg09 pc2/seg10 pc4 /seg 12 pc3 /seg 11 pc5/seg13 pc6/seg14 pc7/seg15 pd0/seg16 pd1/seg17 pd2/seg18 pd3/seg19 pd4/seg20 pd5/seg21 pd6/seg22 pe1/seg25 pe2/seg26 pe3/seg27 pe4/seg28/int10 pe5/seg29/int11 v ss pe6/seg30/int12 pe7/seg31/int13 p60/seg32/ppg10 pd7/seg23 pe0/seg24 p61/seg33/ppg11 mod x1 x0
mb95120 series 8 (continued) (top view) (fpt-100p-m06) note : the p90 to p95 are not used as a general-purpose ports in the mb95f128e. v ss pg0 p00/int00 p01/int01 p02/int02 p03/int03 p04/int04 p05/int05 p06/int06 p07/int07 p12/uck0 p13/trg0/adtg p14/ppg0 p20/ppg00 p21/ppg01 av cc 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 75 74 73 72 71 80 79 78 77 76 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 100 99 98 97 96 95 94 p22/to00 p23/to01 p24/ec0 p10/ui0 p11/uo0 p50/scl0 p51/sda0 avr p52/ppg1 av ss p30/an00 p31/an01 p32/an02 p33/an03 p34/an04 p35/an05 p36/an06 p37/an07 p40/an08 p43/an11 p53/trg1 p70/to0 p71/ti0 p67/seg39/sin x1a p66/seg38/sot p65/seg37/sck p64/seg36/ec1 p41/an09 p42/an10 p63/seg35/to11 p62/seg34/to10 x0a rst p91/v2 p90/v3 v cc p92/v1 p93/v0 p94/c0 p95/c1 pa0/com0 pa1/com1 pa2/com2 pb1/seg01 pb2/seg02 pb3/seg03 pb4/seg04 pb5/seg05 v cc pb6/seg06 pb7/seg07 pc0/seg08 pa3/com3 pb0/seg00 pc1/seg09 pc2/seg10 pc4 /seg 12 pc3 /seg 11 pc5/seg13 pc6/seg14 pc7/seg15 pd0/seg16 pd1/seg17 pd2/seg18 pd3/seg19 pd4/seg20 pd5/seg21 pd6/seg22 pe1/seg25 pe2/seg26 pe3/seg27 pe4/seg28/int10 pe5/seg29/int11 v ss pe6/seg30/int12 pe7/seg31/int13 p60/seg32/ppg10 pd7/seg23 pe0/seg24 p61/seg33/ppg11 mod x1 x0
mb95120 series 9 pin description (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 14 v ss ? power supply pin (gnd) 2 5 pg0 h general-purpose i/o port 3 6 p00/int00 c general-purpose i/o port the pins are shared with external interrupt input. large current port. 4 7 p01/int01 5 8 p02/int02 6 9 p03/int03 7 10 p04/int04 8 11 p05/int05 9 12 p06/int06 10 13 p07/int07 11 14 p10/ui0 g general-purpose i/o port the pin is shared with uart/sio ch.0 data input. 12 15 p11/uo0 h general-purpose i/o port the pin is shared with uart/sio ch.0 data output. 13 16 p12/uck0 general-purpose i/o port the pin is shared with uart/sio ch.0 clock i/o. 14 17 p13/trg0/ adtg general-purpose i/o port the pin is shared with 16-bit ppg ch.0 trigger input (trg0) and a/d converter trigger input (adtg). 15 18 p14/ppg0 general-purpose i/o port the pin is shared with 16-bit ppg ch.0 output. 16 19 p20/ppg00 h general-purpose i/o port the pins are shared with 8/16-bit ppg ch.0 output. 17 20 p21/ppg01 18 21 p22/to00 general-purpose i/o port the pins are shared with 8/16-bit compound timer ch.0 output. 19 22 p23/to01 20 23 p24/ec0 general-purpose i/o port the pin is shared with 8/16-bit compound timer ch.0 clock input. 21 24 p50/scl0 i general-purpose i/o port the pin is shared with i 2 c ch.0 clock i/o. 22 25 p51/sda0 general-purpose i/o port the pin is shared with i 2 c ch.0 data i/o. 23 26 p52/ppg1 h general-purpose i/o port the pin is shared with 16-bit ppg ch.1 output. 24 27 avr ? a/d converter reference input pin 25 28 av cc ? a/d converter power supply pin
mb95120 series 10 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 26 29 av ss ? a/d converter power supply pin (gnd) 27 30 p30/an00 j general-purpose i/o port the pins are shared with a/d converter analog input. 28 31 p31/an01 29 32 p32/an02 30 33 p33/an03 31 34 p34/an04 32 35 p35/an05 33 36 p36/an06 34 37 p37/an07 35 38 p40/an08 j general-purpose i/o port the pins are shared with a/d converter analog input. 36 39 p41/an09 37 40 p42/an10 38 41 p43/an11 39 42 p53/trg1 h general-purpose i/o port the pin is shared with 16-bit ppg ch.1 trigger input. 40 43 p70/to0 h general-purpose i/o port the pin is shared with 16-bit reload timer ch.0 output. 41 44 p71/ti0 general-purpose i/o port the pin is shared with 16-bit reload timer ch.0 input. 42 45 p67/seg39/ sin n general-purpose i/o port the pin is shared with lin-uart data input (sin) and lcdc seg output (seg39) . 43 46 p66/seg38/ sot m general-purpose i/o port the pin is shared with lin-uart data output (sot) and lcdc seg output (seg38) . 44 47 p65/seg37/ sck general-purpose i/o port the pin is shared with lin-uart clock i/o (sck) and lcdc seg output (seg37) . 45 48 p64/seg36/ ec1 general-purpose i/o port the pin is shared with 8/16-b it compound timer ch.1 clock input ( ec1 ) and lcdc seg output ( seg36 ) . 46 49 p63/seg35/ to11 general-purpose i/o port the pins are shared with 8/16-bit compound timer ch.1 output (to10, to11) and lcdc seg output (seg34, seg35) . 47 50 p62/seg34/ to10 48 51 rst b' reset pin 49 52 x0a a sub clock oscillation pins (32 khz) 50 53 x1a 51 54 v ss ? power supply pin (gnd)
mb95120 series 11 (continued) pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 52 55 x1 a main clock oscillation pins 53 56 x0 54 57 mod b an operating mode designation pin 55 58 p61/seg33/ ppg11 m general-purpose i/o port the pins are shared with 8/16-bit ppg ch.1 output (ppg10, ppg11) and lcdc seg output (seg32, seg33) . 56 59 p60/seg32/ ppg10 57 60 pe7/seg31/ int13 q general-purpose i/o port the pins are shared with external interrupt input (int10 to int13) and lcdc seg output (seg28 to seg31) . 58 61 pe6/seg30/ int12 59 62 pe5/seg29/ int11 60 63 pe4/seg28/ int10 61 64 pe3/seg27 m general-purpose i/o port the pins are shared with lcdc seg output. 62 65 pe2/seg26 63 66 pe1/seg25 64 67 pe0/seg24 65 68 pd7/seg23 m general-purpose i/o port the pins are shared with lcdc seg output. 66 69 pd6/seg22 67 70 pd5/seg21 68 71 pd4/seg20 69 72 pd3/seg19 70 73 pd2/seg18 71 74 pd1/seg17 72 75 pd0/seg16 73 76 pc7/seg15 m general-purpose i/o port the pins are shared with lcdc seg output. 74 77 pc6/seg14 75 78 pc5/seg13 76 79 v cc ? power supply pin
mb95120 series 12 (continued) *1 : fpt-100p-m20 *2 : fpt-100p-m06 *3 : for the i/o circuit type, refer to ? i/o circuit type?. *4 : the p90 to p95 are not used as a general-purpose ports in the mb95f128e. pin no. pin name i/o circuit type* 3 function lqfp * 1 qfp * 2 77 80 pc4/seg12 m general-purpose i/o port the pins are shared with lcdc seg output. 78 81 pc3/seg11 79 82 pc2/seg10 80 83 pc1/seg09 81 84 pc0/seg08 82 85 pb7/seg07 m general-purpose i/o port the pins are shared with lcdc seg output. 83 86 pb6/seg06 84 87 pb5/seg05 85 88 pb4/seg04 86 89 pb3/seg03 87 90 pb2/seg02 88 91 pb1/seg01 89 92 pb0/seg00 90 93 pa3/com3 m general-purpose i/o port the pins are shared with lcdc com output. 91 94 pa2/com2 92 95 pa1/com1 93 96 pa0/com0 94 97 p95 * 4 /c1 s general-purpose i/o port 95 98 p94 * 4 /c0 96 99 p93 * 4 /v0 r general-purpose i/o port the pins are shared with power supply pins for lcdc drive. 97 100 p92 * 4 /v1 98 1 p91 * 4 /v2 99 2 p90 * 4 /v3 100 3 v cc ? power supply pin
mb95120 series 13 i/o circuit type (continued) type circuit remarks a oscillation circuit high-speed side feedback resistance : approx. 1 m ? low-speed side feedback resistance : approx. 24 m ? (evaluation product : approx.10 m ? ) damping resistance : approx.144 k ? (evaluation product : non-damping resistance ) b only for input hysteresis input b? hysteresis input c cmos output hysteresis input g cmos output cmos input hysteresis input with pull-up control h cmos output hysteresis input with pull-up control x0 (x0a) x1 (x1a) n -ch standby control clock input mode input reset input p-ch n-ch standby control external interrupt enable digital output digital output hysteresis input r p-ch n-ch p-ch pull-up control standby control digital output digital output hysteresis input cmos input p-ch n-ch r p-ch pull-up control standby control digital output digital output hysteresis input
mb95120 series 14 (continued) type circuit remarks i n-ch open drain output cmos input hysteresis input j cmos output hysteresis input analog input with pull-up control m cmos output lcd output hysteresis input n cmos output lcd output cmos input hysteresis input n -ch standby control digital output cmos input hysteresis input r p-ch n-ch p-ch pull-up control a/d control standby control analog input digital output hysteresis input digital output p-ch n-ch standby control hysteresis input digital output digital output lcd control lcd output p-ch n-ch lcd control digital output hysteresis input cmos input digital output standby control lcd output
mb95120 series 15 (continued) type circuit remarks q cmos output lcd output hysteresis input r cmos output lcd power supply hysteresis input s cmos output lcd power supply hysteresis input p-ch n-ch standby control digital output hysteresis input lcd control digital output external interrupt control lcd output p-ch n-ch lcd control standby control lcd internal division resistance i/o hysteresis input digital output digital output p-ch n-ch standby control digital output digital output hysteresis input lcd booster i/o
mb95120 series 16 handling devices ? preventing latch-up care must be taken to ensure that maximum vo ltage ratings are not exceeded when they are used. latch-up may occur on cmos ic s if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-withstand voltage pins or if higher than the rating voltage is applied between v cc pin and v ss pin. when latch-up occurs, power supply current increa ses rapidly and might thermally damage elements. also, take care to prevent the analog power supply voltage (av cc , avr) and analog input voltage from exceeding the digital power supply voltage (v cc ) when the analog system powe r supply is turned on or off. ? stable supply voltage supply voltage should be stabilized. a sudden change in power-supply voltage may cause a ma lfunction even within the guaranteed operating range of the v cc power-supply voltage. for stabilization, in principle, keep the variation in v cc ripple (p-p value) in a commercial frequency range (50/60 hz) not to exceed 10 % of the standard v cc value and suppress the voltage variation so that the transient variation rate does not exceed 0.1 v/ms during a mome ntary change such as when the power supply is switched. ? precautions for use of external clock even when an external clock is used, oscillation stabilizatio n wait time is required for power-on reset, wake-up from sub clock mode or stop mode. pin connection ? treatment of unused pin leaving unused input pins unconnect ed can cause abnormal operation or latch-up, leaving to permanent damage. unused input pins should always be pulled up or down through resistance of at least 2 k ? . any unused input/ output pins may be set to output mode and left open, or set to input mode and treat ed the same as unused input pins. if there is unused output pin, make it open. ? treatment of power supply pins on a/d converter connect to be av cc = v cc and av ss = avr = v ss even if the a/d converter is not in use. noise riding on the av cc pin may cause accuracy degradation. so, connect approx. 0.1 f ceramic capacitor as a bypass capacitor between av cc and av ss pins in the vicinity of this device. ? power supply pins in products with multiple v cc or v ss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission le vel, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with the v cc and v ss pins of this device at the low impedance. it is also advisable to connect a cera mic bypass capacitor of approximately 0.1 f between v cc and v ss near this device.
mb95120 series 17 ? mode pin (mod) connect the mod pin directly to v cc or v ss pins. to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mod pin to v cc or v ss pins and to provide a low-impedance connection. ? analog power supply always set the same potential to av cc and v cc pins. when v cc > av cc , the current may flow through the an00 to an11 pins.
mb95120 series 18 programming flash memory microcontrollers using parallel programmer ? supported parallel programmers and adapters the following table lists supported parallel programmers and adapters. note : for information on applicable adapter mode ls and parallel programmers, contact the following: flash support group, inc. tel: +81-53-428-8380 ? sector configuration the individual sectors of flash memory correspond to addresses used for cpu access and programming by the parallel programmer as follows: ? programming method 1) set the type code of the parallel programmer to 17222. 2) load program data to pr ogrammer addresses 71000 h to 7ffff h . 3) programmed by parallel programmer package applicable adapter model parallel programmers fpt-100p-m20 tef110-95f128hspfv af9708 (ver 02.35g or more) af9709/b (ver 02.35g or more) af9723+af9834 (ver 02.08e or more) fpt-100p-m06 tef110-95f128hspf ? mb95f128d/f128e (60 kbytes) *: programmer addresses are corresponding to cpu addresses, used when the parallel programmer programs data into flash memory. these programmer addresses are used for the parallel programmer to program or erase data in flash memory. flash memory cpu address programmer address* sa1 (4 kbytes) 1000 h 71000 h 1fff h 71fff h sa2 (4 kbytes) 2000 h 72000 h 2fff h 72fff h sa3 (4 kbytes) 3000 h 73000 h 3fff h 73fff h sa4 (16 kbytes) 4000 h 74000 h 7fff h 77fff h sa5 (16 kbytes) 8000 h 78000 h bfff h 7bfff h sa6 (4 kbytes) c000 h 7c000 h cfff h 7cfff h sa7 (4 kbytes) d000 h 7d000 h dfff h 7dfff h sa8 (4 kbytes) e000 h 7e000 h efff h 7efff h sa9 (4 kbytes) f000 h 7f000 h ffff h 7ffff h lower bank upper bank
mb95120 series 19 block diagram p14/ppg0 p65/ s eg 3 7/ s ck p67/ s eg 3 9/ s in av cc av ss avr p50/ s cl0 p51/ s da0 p40/an0 8 to p4 3 /an11 p 3 0/an00 to p 3 7/an07 p21/ppg01 p22/to00 p2 3 /to01 p24/ec0 p12/uck0 p62/ s eg 3 4/to10 pe7/ s eg 3 1/int1 3 p6 3 / s eg 3 5/to11 p00/int00 to p07/int07 pg0 p10/ui0 p64/ s eg 3 6/ec1 p71/ti0 p66/ s eg 38 / s ot p70/to0 r s t x0/x1 x0a/x1a mod, v cc p1 3 /trg0/adtg p20/ppg00 p11/uo0 uart/ s io i 2 c lin-uart rom ram f 2 mc- 8 fx cpu p61/ s eg 33 /ppg11 p60/ s eg 3 2/ppg10 p52/ppg1 p5 3 /trg1 p90/v 3 to p9 3 /v0 p94/c0, p95/c1 pa0/com0 to pa 3 /com 3 pb0/ s eg00 to pb7/ s eg07 pc0/ s eg0 8 to pc7/ s eg15 pd0/ s eg16 to pd7/ s eg2 3 pe0/ s eg24 to pe 3 / s eg27 pe4/ s eg2 8 /int10 pe5/ s eg29/int11 pe6/ s eg 3 0/int12 16- b it ppg ch.0 8 /16- b it ppg ch.0 8 /10- b it a/d converter 8 /16- b it ppg ch.1 port port extern a l interr u pt ch. 8 to ch.11 8 /16- b it compo u nd timer ch.0 16- b it relo a d timer 8 /16- b it compo u nd timer ch.1 interr u pt control wild regi s ter re s et control clock control w a tch pre s c a ler w a tch co u nter extern a l interr u pt ch.0 to ch.7 intern a l bus other pin s 16- b it ppg ch.1 lcdc
mb95120 series 20 cpu core 1. memory space memory space of the mb95120 series is 64 kbytes and c onsists of i/o area, data area, and program area. the memory space includes special - purpos e areas such as the general - purpose registers and vector table. memory map of the mb95120 series is shown below. memory map ram 3 .75 k b yte s fl as h memory 60 k b yte s ram 2 k b yte s regi s ter acce ss prohi b ited regi s ter fl as h memory 60 k b yte s 0000 h 00 8 0 h 0200 h 0f 8 0 h 1000 h ffff h extended i/o mb95fv100d-101 mb95fv100d-102 i/o 0000 h 00 8 0 h 0100 h 0200 h 0 88 0 h 0f 8 0 h 1000 h ffff h mb95f12 8 d mb95f12 8 e i/o extended i/o 0100 h
mb95120 series 21 2. register the mb95120 series has two types of registers; dedicat ed registers in the cpu and general-purpose registers in the memory. the dedicated registers are as follows: the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and a direct bank pointer (dp) and the lower 8 bits for use as a condition code register (ccr) . (refer to the diagram below.) program counter (pc) : a 16-bit register to indi cate locations where instructions are stored. accumulator (a) : a 16-bit register for temporary st orage of arithmetic oper ations. in the case of an 8-bit data processing instruction, the lower 1 byte is used. temporary accumulator (t) : a 16-bit register which pe rforms arithmetic operations with the accumulator. in the case of an 8-bit data processing instruction, the lower 1 byte is used. index register (ix) : a 16-bit register for index modification extra pointer (ep) : a 16-bit pointer to point to a memory address. stack pointer (sp) : a 16-bit regi ster to indicate a stack area. program status (ps) : a 16-bit register for storing a register bank pointer, a direct bank pointer, and a condition code register pc a t ix ep sp ps : program counter 16-bit : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status initial value fffd h 0000 h 0000 h 0000 h 0000 h 0000 h 0030 h ps rp ccr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dp2 dp1 dp0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r4 r3 r2 r1 r0 h i il1 il0 n z v c dp ? structure of the program status
mb95120 series 22 the rp indicates the address of the register bank cu rrently being used. the relati onship between the content of rp and the real address conforms to the conversion rule illustrated below: the dp specifies the area for mapping instructions (16 di fferent instructions such as mov a, dir) using direct addresses to 0080 h to 00ff h . the ccr consists of the bits indicating arithmetic operat ion results or transfer data contents and the bits that control cpu operations at interrupt. direct bank pointer (dp2 to dp0) specified address area mapping area xxx b (no effect to mapping) 0000 h to 007f h 0000 h to 007f h (without mapping) 000 b (initial value) 0080 h to 00ff h 0080 h to 00ff h (without mapping) 001 b 0100 h to 017f h 010 b 0180 h to 01ff h 011 b 0200 h to 027f h 100 b 0280 h to 02ff h 101 b 0300 h to 037f h 110 b 0380 h to 03ff h 111 b 0400 h to 047f h h flag : set to ?1? when a carry or a borrow from bit 3 to bi t 4 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. this flag is for decimal adjustment instructions. i flag : interrupt is enabled when this flag is set to ?1?. in terrupt is disabled when this flag is set to ?0?. the flag is cleared to ?0? when reset. il1, il0 : indicates the level of the interrupt currently enabled. processes an inte rrupt only if its request level is higher than the value indicated by these bits. il1 il0 interrupt level priority 00 0 high low = no interruption 01 1 10 2 11 3 n flag : set to ?1? if the msb is set to ?1? as the result of an arithmetic operation. cleared to ?0? when the bit is set to ?0?. z flag : set to ?1? when an arithmetic operation re sults in ?0?. cleared to ?0? otherwise. v flag : set to ?1? if the complement on 2 overflows as a re sult of an arithmetic operation. cleared to ?0? otherwise. c flag : set to ?1? when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to ?0? otherwise. set to the shift-out va lue in the case of a shift instruction. ? rule for conversion of actual addresse s in the general-purpose register area generated address rp upper op code lower "0" "0" "0" "0" "0" "0" "0" "1" r4 r 3 r2 r1 r0 b 2 b 1 b 0 a7 a6 a5 a4 a 3 a2 a1 a0 a15 a14 a1 3 a12 a11 a10 a9 a 8
mb95120 series 23 the following general-purpose registers are provided: general-purpose registers: 8-bit data storage registers the general-purpose registers are 8 bits and located in the register banks on the memory. 1-bank contains 8-register. up to a total of 32 banks can be used on the mb95120 series. th e bank currently in use is indicated by the register bank pointer (rp).8-re gister. up to a total of 32 banks can be used on the mb95120 series. the bank currently in use is specified by the register bank pointer (rp), and the lower 3 bits of op code indicates the general-purpose register 0 (r0) to general-purpose register 7 (r7). r0 r1 r2 r3 r4 r5 r6 r7 r0 this address = 0100 h + 8 (rp) r1 r2 r3 r4 r5 r6 r7 r0 r1 r2 r3 r4 r5 r6 r7 address 100 h 107 h 1f8 h 1ff h bank 31 bank 0 8-bit register bank configuration 32 banks memory area 32 banks (ram area) the number of banks is limited by the usable ram capacitance.
mb95120 series 24 i/o map (continued) address register abbreviation register name r/w initial value 0000 h pdr0 port 0 data register r/w 00000000 b 0001 h ddr0 port 0 direction register r/w 00000000 b 0002 h pdr1 port 1 data register r/w 00000000 b 0003 h ddr1 port 1 direction register r/w 00000000 b 0004 h ? (disabled) ?? 0005 h watr oscillation stabilization wait time setting register r/w 11111111 b 0006 h pllc pll control register r/w 00000000 b 0007 h sycc system clock control register r/w 1010x011 b 0008 h stbc standby control register r/w 00000000 b 0009 h rsrr reset source register r xxxxxxxx b 000a h tbtc timebase timer control register r/w 00000000 b 000b h wpcr watch prescaler control register r/w 00000000 b 000c h wdtc watchdog timer control register r/w 00000000 b 000d h ? (disabled) ?? 000e h pdr2 port 2 data register r/w 00000000 b 000f h ddr2 port 2 direction register r/w 00000000 b 0010 h pdr3 port 3 data register r/w 00000000 b 0011 h ddr3 port 3 direction register r/w 00000000 b 0012 h pdr4 port 4 data register r/w 00000000 b 0013 h ddr4 port 4 direction register r/w 00000000 b 0014 h pdr5 port 5 data register r/w 00000000 b 0015 h ddr5 port 5 direction register r/w 00000000 b 0016 h pdr6 port 6 data register r/w 00000000 b 0017 h ddr6 port 6 direction register r/w 00000000 b 0018 h pdr7 port 7 data register r/w 00000000 b 0019 h ddr7 port 7 direction register r/w 00000000 b 001a h , 001b h ? (disabled) ?? 001c h pdr9 port 9 data register r/w 00000000 b 001d h ddr9 port 9 direction register r/w 00000000 b 001e h pdra port a data register r/w 00000000 b 001f h ddra port a direction register r/w 00000000 b 0020 h pdrb port b data register r/w 00000000 b 0021 h ddrb port b direction register r/w 00000000 b 0022 h pdrc port c data register r/w 00000000 b 0023 h ddrc port c direction register r/w 00000000 b
mb95120 series 25 (continued) address register abbreviation register name r/w initial value 0024 h pdrd port d data register r/w 00000000 b 0025 h ddrd port d direction register r/w 00000000 b 0026 h pdre port e data register r/w 00000000 b 0027 h ddre port e direction register r/w 00000000 b 0028 h , 0029 h ? (disabled) ?? 002a h pdrg port g data register r/w 00000000 b 002b h ddrg port g direction register r/w 00000000 b 002c h ? (disabled) ?? 002d h pul1 port 1 pull-up register r/w 00000000 b 002e h pul2 port 2 pull-up register r/w 00000000 b 002f h pul3 port 3 pull-up register r/w 00000000 b 0030 h pul4 port 4 pull-up register r/w 00000000 b 0031 h pul5 port 5 pull-up register r/w 00000000 b 0032 h pul7 port 7 pull-up register r/w 00000000 b 0033 h , 0034 h ? (disabled) ?? 0035 h pulg port g pull-up register r/w 00000000 b 0036 h t01cr1 8/16-bit compound timer 01 contro l status register 1 ch.0 r/w 00000000 b 0037 h t00cr1 8/16-bit compound timer 00 contro l status register 1 ch.0 r/w 00000000 b 0038 h t11cr1 8/16-bit compound timer 11 contro l status register 1 ch.1 r/w 00000000 b 0039 h t10cr1 8/16-bit compound timer 10 contro l status register 1 ch.1 r/w 00000000 b 003a h pc01 8/16-bit ppg1 control register ch.0 r/w 00000000 b 003b h pc00 8/16-bit ppg0 control register ch.0 r/w 00000000 b 003c h pc11 8/16-bit ppg1 control register ch.1 r/w 00000000 b 003d h pc10 8/16-bit ppg0 control register ch.1 r/w 00000000 b 003e h tmcsrh0 16-bit reload timer control status register (upper byte) ch.0 r/w 00000000 b 003f h tmcsrl0 16-bit reload timer control status register (lower byte) ch.0 r/w 00000000 b 0040 h , 0041 h ? (disabled) ?? 0042 h pcnth0 16-bit ppg status control re gister (upper byte) ch.0 r/w 00000000 b 0043 h pcntl0 16-bit ppg status control re gister (lower byte) ch.0 r/w 00000000 b 0044 h pcnth1 16-bit ppg status control re gister (upper byte) ch.1 r/w 00000000 b 0045 h pcntl1 16-bit ppg status control register (lower byte) ch.1 r/w 00000000 b 0046 h , 0047 h ? (disabled) ?? 0048 h eic00 external interrupt circuit co ntrol register ch.0/ch.1 r/w 00000000 b 0049 h eic10 external interrupt circuit co ntrol register ch.2/ch.3 r/w 00000000 b
mb95120 series 26 (continued) address register abbreviation register name r/w initial value 004a h eic20 external interrupt circuit control register ch.4/ch.5 r/w 00000000 b 004b h eic30 external interrupt circuit control register ch.6/ch.7 r/w 00000000 b 004c h eic01 external interrupt circuit control register ch.8/ch.9 r/w 00000000 b 004d h eic11 external interrupt circuit control register ch.10/ch.11 r/w 00000000 b 004e h , 004f h ? (disabled) ?? 0050 h scr lin-uart serial control register r/w 00000000 b 0051 h smr lin-uart serial mode register r/w 00000000 b 0052 h ssr lin-uart serial status register r/w 00001000 b 0053 h rdr/tdr lin-uart reception/transmission data register r/w 00000000 b 0054 h escr lin-uart extended status control register r/w 00000100 b 0055 h eccr lin-uart extended communication control register r/w 000000xx b 0056 h smc10 uart/sio serial mode control register 1 ch.0 r/w 00000000 b 0057 h smc20 uart/sio serial mode control register 2 ch.0 r/w 00100000 b 0058 h ssr0 uart/sio serial status register ch.0 r/w 00000001 b 0059 h tdr0 uart/sio serial output data register ch.0 r/w 00000000 b 005a h rdr0 uart/sio serial input data register ch.0 r 00000000 b 005b h to 005f h ? (disabled) ?? 0060 h ibcr00 i 2 c bus control register 0 ch.0 r/w 00000000 b 0061 h ibcr10 i 2 c bus control register 1 ch.0 r/w 00000000 b 0062 h ibsr0 i 2 c bus status register ch.0 r 00000000 b 0063 h iddr0 i 2 c data register ch.0 r/w 00000000 b 0064 h iaar0 i 2 c address register ch.0 r/w 00000000 b 0065 h iccr0 i 2 c clock control register ch.0 r/w 00000000 b 0066 h to 006b h ? (disabled) ?? 006c h adc1 8/10-bit a/d converter control register 1 r/w 00000000 b 006d h adc2 8/10-bit a/d converter control register 2 r/w 00000000 b 006e h addh 8/10-bit a/d converter data register (upper byte) r/w 00000000 b 006f h addl 8/10-bit a/d converter data r egister (lower byte) r/w 00000000 b 0070 h wcsr watch counter status register r/w 00000000 b 0071 h ? (disabled) ?? 0072 h fsr flash memory status register r/w 000x0000 b
mb95120 series 27 (continued) address register abbreviation register name r/w initial value 0073 h swre0 flash memory sector writing control register 0 r/w 00000000 b 0074 h swre1 flash memory sector writing control register 1 r/w 00000000 b 0075 h ? (disabled) ?? 0076 h wren wild register address compare enable register r/w 00000000 b 0077 h wror wild register data test setting register r/w 00000000 b 0078 h ? register bank pointer (rp) , mirror of direct bank pointer (dp) ?? 0079 h ilr0 interrupt level sett ing register 0 r/w 11111111 b 007a h ilr1 interrupt level sett ing register 1 r/w 11111111 b 007b h ilr2 interrupt level sett ing register 2 r/w 11111111 b 007c h ilr3 interrupt level sett ing register 3 r/w 11111111 b 007d h ilr4 interrupt level sett ing register 4 r/w 11111111 b 007e h ilr5 interrupt level sett ing register 5 r/w 11111111 b 007f h ? (disabled) ?? 0f80 h wrarh0 wild register address setting register (upper byte) ch.0 r/w 00000000 b 0f81 h wrarl0 wild register address setting register (lower byte) ch.0 r/w 00000000 b 0f82 h wrdr0 wild register data setting register ch.0 r/w 00000000 b 0f83 h wrarh1 wild register address setting register (upper byte) ch.1 r/w 00000000 b 0f84 h wrarl1 wild register address setting register (lower byte) ch.1 r/w 00000000 b 0f85 h wrdr1 wild register data setting register ch.1 r/w 00000000 b 0f86 h wrarh2 wild register address setting register (upper byte) ch.2 r/w 00000000 b 0f87 h wrarl2 wild register address setting register (lower byte) ch.2 r/w 00000000 b 0f88 h wrdr2 wild register data setting register ch.2 r/w 00000000 b 0f89 h to 0f91 h ? (disabled) ?? 0f92 h t01cr0 8/16-bit compound timer 01 cont rol status register 0 ch.0 r/w 00000000 b 0f93 h t00cr0 8/16-bit compound timer 00 cont rol status register 0 ch.0 r/w 00000000 b 0f94 h t01dr 8/16-bit compound timer 01 data register ch.0 r/w 00000000 b 0f95 h t00dr 8/16-bit compound timer 00 data register ch.0 r/w 00000000 b 0f96 h tmcr0 8/16-bit compound timer 00/01 timer mode control register ch.0 r/w 00000000 b 0f97 h t11cr0 8/16-bit compound timer 11 cont rol status register 0 ch.1 r/w 00000000 b 0f98 h t10cr0 8/16-bit compound timer 10 cont rol status register 0 ch.1 r/w 00000000 b 0f99 h t11dr 8/16-bit compound timer 11 data register ch.1 r/w 00000000 b 0f9a h t10dr 8/16-bit compound timer 10 data register ch.1 r/w 00000000 b
mb95120 series 28 (continued) address register abbreviation register name r/w initial value 0f9b h tmcr1 8/16-bit compound timer 10/11 timer mode control register ch.1 r/w 00000000 b 0f9c h pps01 8/16-bit ppg1 cycle setting buffer register ch.0 r/w 11111111 b 0f9d h pps00 8/16-bit ppg0 cycle setting buffer register ch.0 r/w 11111111 b 0f9e h pds01 8/16-bit ppg1 duty setting buffer register ch.0 r/w 11111111 b 0f9f h pds00 8/16-bit ppg0 duty setting buffer register ch.0 r/w 11111111 b 0fa0 h pps11 8/16-bit ppg1 cycle setting buffer register ch.1 r/w 11111111 b 0fa1 h pps10 8/16-bit ppg0 cycle setting buffer register ch.1 r/w 11111111 b 0fa2 h pds11 8/16-bit ppg1 duty setting buffer register ch.1 r/w 11111111 b 0fa3 h pds10 8/16-bit ppg0 duty setting buffer register ch.1 r/w 11111111 b 0fa4 h ppgs 8/16-bit ppg start register r/w 00000000 b 0fa5 h revc 8/16-bit ppg output inversion register r/w 00000000 b 0fa6 h tmrh0/ tmrlrh0 16-bit reload timer/reload regist er (upper byte) ch.0 r/w 00000000 b 0fa7 h tmrl0/ tmrlrl0 16-bit reload timer/reload register (lower byte) ch.0 r/w 00000000 b 0fa8 h , 0fa9 h ? (disabled) ?? 0faa h pdcrh0 16-bit ppg down counter r egister (upper byte) ch.0 r 00000000 b 0fab h pdcrl0 16-bit ppg down counter r egister (lower byte) ch.0 r 00000000 b 0fac h pcsrh0 16-bit ppg cycle setting buffer r egister (upper byte) ch.0 r/w 11111111 b 0fad h pcsrl0 16-bit ppg cycle setting buffer r egister (lower byte) ch.0 r/w 11111111 b 0fae h pduth0 16-bit ppg duty setting buffer register (upper byte) ch.0 r/w 11111111 b 0faf h pdutl0 16-bit ppg duty setting buffer r egister (lower byte) ch.0 r/w 11111111 b 0fb0 h pdcrh1 16-bit ppg down counter r egister (upper byte) ch.1 r 00000000 b 0fb1 h pdcrl1 16-bit ppg down counter r egister (lower byte) ch.1 r 00000000 b 0fb2 h pcsrh1 16-bit ppg cycle setting buffer r egister (upper byte) ch.1 r/w 11111111 b 0fb3 h pcsrl1 16-bit ppg cycle setting buffer r egister (lower byte) ch.1 r/w 11111111 b 0fb4 h pduth1 16-bit ppg duty setting buffer register (upper byte) ch.1 r/w 11111111 b 0fb5 h pdutl1 16-bit ppg duty setting buffer r egister (lower byte) ch.1 r/w 11111111 b 0fb6 h to 0fbb h ? (disabled) ?? 0fbc h bgr1 lin-uart baud rate generator register 1 r/w 00000000 b 0fbd h bgr0 lin-uart baud rate generator register 0 r/w 00000000 b 0fbe h pssr0 uart/sio dedicated baud rate generator prescaler select register ch.0 r/w 00000000 b
mb95120 series 29 (continued) ? r/w access symbols ? initial value symbols note : do not write to the ? (disabled) ?. re ading the ? (disabled) ? returns an undefined value. address register abbreviation register name r/w initial value 0fbf h brsr0 uart/sio dedicated baud rate generator baud rate setting register ch.0 r/w 00000000 b 0fc0 h , 0fc1 h ? (disabled) ?? 0fc2 h aidrh a/d input disable register (upper byte) r/w 00000000 b 0fc3 h aidrl a/d input disable register (lower byte) r/w 00000000 b 0fc4 h lcdcc lcdc control register r/w 00010000 b 0fc5 h lcdce1 lcdc enable register 1 r/w 00110000 b 0fc6 h lcdce2 lcdc enable register 2 r/w 00000000 b 0fc7 h lcdce3 lcdc enable register 3 r/w 00000000 b 0fc8 h lcdce4 lcdc enable register 4 r/w 00000000 b 0fc9 h lcdce5 lcdc enable register 5 r/w 00000000 b 0fca h lcdce6 lcdc enable register 6 r/w 00000000 b 0fcb h lcdcb1 lcdc blinking setting register 1 r/w 00000000 b 0fcc h lcdcb2 lcdc blinking setting register 2 r/w 00000000 b 0fcd h to 0fe0 h lcdram lcdc display ram r/w 00000000 b 0fe1 h , 0fe2 h ? (disabled) ?? 0fe3 h wcdr watch counter data register r/w 00111111 b 0fe4 h to 0fed h ? (disabled) ?? 0fee h ilsr input level select register r/w 00000000 b 0fef h wicr interrupt pin select circuit control register r/w 01000000 b 0ff0 h to 0fff h ? (disabled) ?? r/w : readable/writable r : read only w : write only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
mb95120 series 30 interrupt source table interrupt source interrupt request number vector table address bit name of interrupt level setting register same level priority order (at simultaneous occurrence) upper lower external interrupt ch.0 irq0 fffa h fffb h l00 [1 : 0] high external interrupt ch.4 external interrupt ch.1 irq1 fff8 h fff9 h l01 [1 : 0] external interrupt ch.5 external interrupt ch.2 irq2 fff6 h fff7 h l02 [1 : 0] external interrupt ch.6 external interrupt ch.3 irq3 fff4 h fff5 h l03 [1 : 0] external interrupt ch.7 uart/sio ch.0 irq4 fff2 h fff3 h l04 [1 : 0] 8/16-bit compound timer ch.0 (lower) irq5 fff0 h fff1 h l05 [1 : 0] 8/16-bit compound timer ch.0 (upper) irq6 ffee h ffef h l06 [1 : 0] lin-uart (reception) irq7 ffec h ffed h l07 [1 : 0] lin-uart (transmission) irq8 ffea h ffeb h l08 [1 : 0] 8/16-bit ppg ch.1 (lower) irq9 ffe8 h ffe9 h l09 [1 : 0] 8/16-bit ppg ch.1 (upper) irq10 ffe6 h ffe7 h l10 [1 : 0] 16-bit reload timer ch.0 irq11 ffe4 h ffe5 h l11 [1 : 0] 8/16-bit ppg ch.0 (upper) irq12 ffe2 h ffe3 h l12 [1 : 0] 8/16-bit ppg ch.0 (lower) irq13 ffe0 h ffe1 h l13 [1 : 0] 8/16-bit compound timer ch.1 (upper) irq14 ffde h ffdf h l14 [1 : 0] 16-bit ppg ch.0 irq15 ffdc h ffdd h l15 [1 : 0] i 2 c ch.0 irq16 ffda h ffdb h l16 [1 : 0] 16-bit ppg ch.1 irq17 ffd8 h ffd9 h l17 [1 : 0] 8/10-bit a/d converter irq18 ffd6 h ffd7 h l18 [1 : 0] timebase timer irq19 ffd4 h ffd5 h l19 [1 : 0] watch prescaler/watch counter irq20 ffd2 h ffd3 h l20 [1 : 0] external interrupt ch.8 irq21 ffd0 h ffd1 h l21 [1 : 0] external interrupt ch.9 external interrupt ch.10 external interrupt ch.11 8/16-bit compound timer ch.1 (lower) irq22 ffce h ffcf h l22 [1 : 0] flash memory irq23 ffcc h ffcd h l23 [1 : 0] low
mb95120 series 31 electrical characteristics 1. absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 vcc avcc vss ? 0.3 vss + 4.0 v *2 avr vss ? 0.3 vss + 4.0 *2 power supply voltage for lcd v0 to v3 v ss ? 0.3 v ss + 4.0 v products with lcd internal division resistance* 3 v0 v ss ? 0.3 v ss + 2.0 products with booster circuit* 3 v1 v ss ? 0.3 v ss + 2.0 v2 v ss ? 0.3 v ss + 4.0 v3 v ss ? 0.3 v ss + 6.0 c0, c1 v ss ? 0.3 v ss + 6.0 input voltage* 1 v i1 vss ? 0.3 vss + 4.0 v other than p50, p51* 4 v i2 vss ? 0.3 vss + 6.0 p50, p51 output voltage* 1 v o vss ? 0.3 vss + 4.0 v *4 maximum clamp current i clamp ? 2.0 + 2.0 ma applicable to pins* 5 total maximum clamp current |i clamp | ? 20 ma applicable to pins* 5 ?l? level maximum output current i ol1 ? 15 ma other than p00 to p07 i ol2 15 p00 to p07 ?l? level average current i olav1 ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i olav2 12 p00 to p07 average output current = operating current operating ratio (1 pin) ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma total average output current = operating current operating ratio (total of pins) ?h? level maximum output current i oh1 ? ? 15 ma other than p00 to p07 i oh2 ? 15 p00 to p07
mb95120 series 32 (continued) *1 : the parameter is based on av ss = v ss = 0.0 v. *2 : apply equal potential to avcc an d vcc. avr should not exceed avcc + 0.3 v. *3 : v0 to v3 should not exceed v cc + 0.3 v. *4 : v i1 and vo should not exceed v cc + 0.3 v. v i1 must not exceed the rating voltage. however, if the maximum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i1 rating. *5 : applicable to pins : p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53 ? use within recommended operating conditions. ? use at dc voltage (current). ? + b signal is an input signal that exceeds v cc voltage. the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated va lues, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is lo w, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the v cc pin, and this affects other devices. ? note that if the + b signal is inputted when the mi crocontroller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than t he a/d input pins (lcd drive pins, etc.) cannot accept +b signal input. parameter symbol rating unit remarks min max ?h? level average current i ohav1 ? ? 4 ma other than p00 to p07 average output current = operating current operating ratio (1 pin) i ohav2 ? 8 p00 to p07 average output current = operating current operating ratio (1 pin) ?h? level total maximum output current i oh ? ? 100 ma ?h? level total average output current i ohav ? ? 50 ma total average output current = operating current operating ratio (total of pins) power consumption pd ? 320 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb95120 series 33 ? sample recommended circuits : warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch vcc r ? input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb95120 series 34 2. recommended operating conditions (av ss = v ss = 0.0 v) * : the values vary with the operating frequ ency, machine clock or analog guarantee range. warning: the recommended operating conditions are requir ed in order to ensure the normal operation of the semiconductor device. all of the device?s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol pin name condition value unit remarks min max power supply voltage v cc , av cc ?? 1.8* 3.3 v at normal operation, flash memory product, t a = ? 10 c to + 85 c 2.0* 3.3 at normal operation, flash memory product, t a = ? 40 c to + 85 c 2.6 3.6 evaluation product t a = + 5 c to + 35 c 1.5 3.3 holds condition in stop mode, flash memory product power supply voltage for lcd v0 to v3 ?? v ss v cc v the range of liquid crystal power supply: without up-conversion (the optimal value depends on liquid crystal display elements used.) a/d converter reference input voltage avr ?? 1.8 av cc v operating temperature t a ?? ? 40 + 85 c
mb95120 series 35 3. dc characteristics (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condi- tions value unit remarks min typ max ?h? level input voltage v ih1 p10 (selectable at ui0) , p67 (selectable at sin) ? 0.7 v cc ? v cc + 0.3 v when selecting cmos input level (hysteresis input) v ih2 p50, p51 (selectable at i 2 c) ? 0.7 v cc ? v ss + 5.5 v v ihs1 p00 to p07, p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7, pd0 to pd7, pe0 to pe7 ? 0.8 v cc ? v cc + 0.3 v hysteresis input v ihs2 p50, p51 ? 0.8 v cc ? v ss + 5.5 v v ihm rst , mod ? 0.8 v cc ? v cc + 0.3 v hysteresis input ?l? level input voltage v il p10 (selectable at ui0) , p50, p51 (selectable at i 2 c) p67 (selectable at sin) ? v ss ? 0.3 ? 0.3 v cc v when selecting cmos input level (hysteresis input) ?l? level input voltage v ils p00 to p07 p10 to p14, p20 to p24, p30 to p37, p40 to p43, p50 to p53, p60 to p67, p70, p71, p90 to p95, pa0 to pa3, pb0 to pb7, pc0 to pc7, pd0 to pd7, pe0 to pe7 ? v ss ? 0.3 ? 0.2 v cc v hysteresis input v ilm rst , mod ? v ss ? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d1 p50, p51 ? v ss ? 0.3 ? v ss + 5.5 v
mb95120 series 36 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name conditions value unit remarks min typ max ?h? level output voltage v oh1 output pin other than p00 to p07 i oh = ? 4.0 ma 2.4 ?? v v oh2 p00 to p07 i oh = ? 8.0 ma 2.4 ?? v ?l? level output voltage v ol1 output pin other than p00 to p07, rst i ol = 4.0 ma ?? 0.4 v v ol2 p00 to p07 i ol = 12 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li port other than p50, p51 0.0 v < v i < v cc ? 5 ? + 5 a when the pull-up prohibition setting open-drain output leakage current i liod p50, p51 0.0 v < v i < v ss + 5.5 v ?? 5 a pull-up resistor r pull p10 to p14, p20 to p24, p30 to p37, p40 to p43, p52, p53, p70, p71 v i = 0.0 v 25 50 100 k ? when the pull-up permission setting input capacitance c in other than av cc , av ss , avr, v cc , v ss f = 1 mhz ? 515pf
mb95120 series 37 (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name conditions value unit remarks min typ max power supply current* i cc v cc (external clock operation) f ch = 20 mhz f mp = 10 mhz main clock mode (divided by 2) ? 11.0 14.0 ma at other than flash memory writing and erasing ? 30.0 35.0 ma at flash memory writing and erasing f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ? 17.6 22.4 ma at other than flash memory writing and erasing ? 38.1 44.9 ma at flash memory writing and erasing i ccs f ch = 20 mhz f mp = 10 mhz main sleep mode (divided by 2) ? 4.5 6.0 ma f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ? 7.2 9.6 ma i ccl f cl = 32 khz f mpl = 16 khz sub clock mode (divided by 2) ? 25 35 a i ccls f cl = 32 khz f mpl = 16 khz sub sleep mode (divided by 2) ? 715 a i cct f cl = 32 khz watch mode main stop mode t a = + 25 c ? 210 a i ccmpll f ch = 4 mhz f mp = 10 mhz main pll mode (multiplied by 2.5) ? 10 14 ma f ch = 6.4 mhz f mp = 16 mhz main pll mode (multiplied by 2.5) ? 16.0 22.4 ma
mb95120 series 38 (continued) (v cc = av cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : the power-supply current is determined by the external clock. ? refer to ?4. ac characterist ics (1) clock timing? for f ch and f cl . ? refer to ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . parameter sym- bol pin name conditions value unit remarks min typ max power supply current* i ccspll v cc (external clock operation) f cl = 32 khz f mpl = 128 khz sub pll mode ( multiplied by 4 ) , t a = + 25 c ? 190 250 a i cts f ch = 10 mhz timebase timer mode t a = + 25 c ? 0.4 0.5 ma i cch sub stop mode t a = + 25 c ? 15 a i a av cc f ch = 16 mhz at operating of a/d conversion ? 1.3 2.2 ma i ah f ch = 16 mhz at stopping of a/d conversion t a = + 25 c ? 15 a lcd internal division resistance r lcd ? between v3 and v ss ? 300 ? k ? products with lcd internal division resistance only lcd leakage current i lcdl v0 to v3, com0 to com3 seg00 to seg39 ??? 1 a output voltage for lcd boost v v3 v3 v1 = 1.5 v 4.3 4.5 4.7 v products with booster circuit only v v2 v2 v1 = 1.5 v 2.9 3.0 3.1 v reference voltage for lcd boost v v1 v1 i in = 0.0 a1.41.51.7v reference voltage input impedance r rin v1 ? 8.5 9.8 11 k ? com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 3.6 v ?? 5k ? seg00 to seg39 output impedance r vseg seg00 to seg39 ??? 7k ? lcd leak current i lcdl v0 to v3, com0 to com3 seg00 to seg39 ? ? 1 ? + 1 a
mb95120 series 39 4. ac characteristics (1) clock timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) parameter sym- bol pin name condi- tions value unit remarks min typ max clock frequency f ch x0, x1 ? 1.00 ? 16.25 mhz when using main oscillation circuit 1.00 ? 32.50 mhz when using external clock 3.00 ? 10.00 mhz main pll multiplied by 1 3.00 ? 8.13 mhz main pll multiplied by 2 3.00 ? 6.50 mhz main pll multiplied by 2.5 3.00 ? 4.06 mhz main pll multiplied by 4 f cl x0a, x1a ? 32.768 ? khz when using sub oscillation circuit ? 32.768 ? khz when using sub pll v cc = 2.3 v to 3.3 v clock cycle time t hcyl x0, x1 61.5 ? 1000 ns when using main oscillation circuit 30.8 ? 1000 ns when using external clock t lcyl x0a, x1a ? 30.5 ? s when using sub oscillation circuit input clock pulse width t wh1 t wl1 x0 61.5 ?? ns when using external clock duty ratio is about 30 % to 70 % . t wh2 t wl2 x0a ? 15.2 ? s input clock rise time and fall time t cr t cf x0, x0a ?? 5 ns when using external clock
mb95120 series 40 t hcyl t wh1 t cr 0.2 v cc x0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t cf t wl1 ? input wave form for using external clock (main clock) x0 x1 f ch x0 f ch x1 microcontroller microcontroller c1 c2 ? figure of main clock input port external connection when using a crystal or ceramic oscillator when using external clock open t lcyl t wh2 t cr 0.1 v cc x0a 0. 8 v cc 0. 8 v cc 0.1 v cc 0.1 v cc t cf t wl2 ? input wave form for using external clock (sub clock) x0a x1a f cl x0a f cl x1a microcontroller microcontroller c1 c2 ? figure of sub clock input port external connection when using a crystal or ceramic oscillator when using external clock open
mb95120 series 41 (2) source clock/machine clock (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : clock before setting division due to machine clock di vision ratio selection bit (sycc : div1 and div0) . this source clock is divided by the machin e clock division ratio selection bit (sycc : div1 and div0) , and it becomes the machine clock. further, the source clock can be selected as follows. ? main clock divided by 2 ? pll multiplication of main clock (selec t from 1, 2, 2.5, 4 multiplication) ? sub clock divided by 2 ? pll multiplication of sub clock (sel ect from 2, 3, 4 multiplication) * 2 : operation clock of the microcontroller. machine clock can be selected as follows. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter sym- bol pin name value unit remarks min typ max source clock cycle time* 1 (clock before setting division) t sclk ? 61.5 ? 2000 ns when using main clock min : f ch = 16.25 mhz, pll multiplied by 1 max : f ch = 1 mhz, divided by 2 7.6 ? 61.0 s when using sub clock min : f cl = 32 khz, pll multiplied by 4 max : f cl = 32 khz, divided by 2 source clock frequency f sp ? 0.50 ? 16.25 mhz when using main clock f spl ? 16.384 ? 131.072 khz when using sub clock machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when using main clock min : f sp = 16.25 mhz, no division max : f sp = 0.5 mhz, divided by 16 7.6 ? 976.5 s when using sub clock min : f spl = 131 khz, no division max : f spl = 16 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.250 mhz when using main clock f mpl 1.024 ? 131.072 khz when using sub clock f ch (main oscillation) f cl (sub oscillation) divided by 2 main pll 1 2 2.5 4 divided by 2 sub pll 2 3 4 sclk (source clock) clock mode select bit (sycc: scs1, scs0) mclk (machine clock) division circuit 1 1/4 1/8 1/16 ? outline of clock generation block
mb95120 series 42 ? operating voltage - operating frequency (when t a = ? 10 c to + 85 c) mb95f128d/f128e ? operating voltage - operating frequency (t a = ? 40 c to + 85 c) mb95f128d/f128e 131.072 khz 16.384 khz 1.8 3.6 2.3 32 khz 16.25 mhz 0.5 mhz 3.6 1.8 5 mhz 3 mhz 2.7 source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range 131.072 khz 16.384 khz 2.0 3.3 2.3 32 khz sub pll operation guarantee range source clock frequency (f spl ) operating voltage (v) sub clock mode and watch mode operation guarantee range pll operation guarantee range 16.25 mhz 0.5 mhz 3.3 2.0 7.5 mhz 3 mhz 2.7 source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range main clock mode and main pll mode operation guarantee range
mb95120 series 43 ? operating voltage - operating frequency ( t a = + 5 c to + 35 c) ? mb95fv100d-101/102 131.072 khz 16.384 khz 2.6 3.6 32 khz 10 mhz 0.5 mhz 3 .6 2.6 3 . 3 16.25 mhz 3 mhz source clock frequency (f spl ) operating voltage (v) sub pll, sub clock mode and watch mode operation guarantee range pll operation guarantee range source clock frequency (f sp ) operating voltage (v) pll operation guarantee range main clock operation guarantee range fram, main clock mode and main pll mode operation guarantee range
mb95120 series 44 ? main pll operation frequency [mhz] 16.25 16 15 12 10 7.5 6 5 3 0 3 4 4.062 5 6.4 6.5 8 8 .125 10 [mhz] machine clock frequency (f mp ) source clock frequency (fsp) 2.5 2 1 4
mb95120 series 45 (3) external reset (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : refer to ? (2) source clock/machine clock? for t mclk . *2 : oscillation start time of oscillator is the time that the amplitude reaches 90 %. in the crystal oscillator, the oscillation time is between several ms and tens of ms. in ceramic oscillato rs, the oscillation time is between hundreds of s and several ms. in the external clock, the oscillation time is 0 ms. parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk * 1 ? ns at normal operating oscillation time of oscillator* 2 + 2 t mclk ? s at stop mode, sub clock mode, sub sleep mode, and watch mode t rstl 0.2 v cc rst 0.2 v cc t rstl 0.2 v cc 0.2 v cc 2 t mclk rst x0 ? at normal operating ? at stop mode, sub clock mode, su b sleep mode, watch mode, and power-on internal operating clock internal reset 90 % of amplitude oscillation time of oscillator oscillation stabilization wait time execute instruction
mb95120 series 46 (4) power-on reset (av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden change of power supply voltage may acti vate the power-on reset function. when changing power supply voltages during operation, set the slope of rising within 30 mv/ms as shown below. parameter symbol conditions value unit remarks min max power supply rising time t r ?? 36 ms power supply cutoff time t off ? 1 ? ms waiting time until power-on 0.2 v 0.2 v t off t r 1.5 v 0.2 v v cc v cc 1.5 v v ss hold c ondition in stop mode limiting the slope of rising within 20 mv/ms is recommended.
mb95120 series 47 (5) peripheral input timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns t ilih int00 to int07, int10 to int13, ec0, ec1, ti0, trg0/adtg, trg1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ihil
mb95120 series 48 (6) uart/sio, serial i/o timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) * : refer to ? (2) source clock/machine clock? for t mclk . parameter symbol pin name conditions value unit min max serial clock cycle time t scyc uck0 internal clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns uck uo time t slov uck0, uo0 ? 190 + 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns serial clock ?h? pulse width t shsl uck0 external clock operation output pin : c l = 80 pf + 1ttl. 4 t mclk * ? ns serial clock ?l? pulse width t slsh uck0 4 t mclk * ? ns uck uo time t slov uck0, uo0 0 190 ns valid ui uck t ivsh uck0, ui0 2 t mclk * ? ns uck valid ui hold time t shix uck0, ui0 2 t mclk * ? ns t scyc t ivsh 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t shix t slov 0.8 v 2.4 v 0.8 v 2.4 v uck0 uo0 ui0 0.8 v t slsh t ivsh t shix t slov 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t shsl 2.4 v uck0 uo0 ui0 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc internal shift clock mode external shift clock mode
mb95120 series 49 (7) lin-uart timing sampling at the rising edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to dela y half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns serial clock ?l? pulse width t slsh sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?h? pulse width t shsl sck t mclk * 3 + 95 ? ns sck sot delay time t slove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivshe sck, sin 190 ? ns sck valid sin hold time t shixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95120 series 50 0.8 v 2.4 v t slovi t ivshi t shixi 0.8 v cc 2.4 v 0.8 v sck sot sin t scyc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v t slove t ivshe t shixe 2.4 v 0.8 v t r t f sck sot sin t slsh t shsl 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc internal shift clock mode external shift clock mode
mb95120 series 51 sampling at the falling edge of sampling clock* 1 and prohibited serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 0) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of receptio n data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns serial clock ?h? pulse width t shsl sck external clock operation output pin : c l = 80 pf + 1 ttl. 3 t mclk * 3 ? t r ? ns serial clock ?l? pulse width t slsh sck t mclk * 3 + 95 ? ns sck sot delay time t shove sck, sot ? 2 t mclk * 3 + 95 ns valid sin sck t ivsle sck, sin 190 ? ns sck valid sin hold time t slixe sck, sin t mclk * 3 + 95 ? ns sck fall time t f sck ? 10 ns sck rise time t r sck ? 10 ns
mb95120 series 52 0.8 v 2.4 v t shovi t ivsli t slixi 0.8 v cc 2.4 v 0.8 v sck sot sin t scyc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v t shove t ivsle t slixe 2.4 v 0.8 v t f t r sck sot sin t shsl t slsh 0.8 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 0.2 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb95120 series 53 sampling at the rising edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 0, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of recepti on data is performed at risi ng edge or falling edge of the serial clock. *2 : serial clock delay function is used to del ay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operation output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t shovi sck, sot ? 95 + 95 ns valid sin sck t ivsli sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t slixi sck, sin 0 ? ns sot sck delay time t sovli sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 0.8 v 0.8 v t shovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovli t ivsli t slixi
mb95120 series 54 sampling at the falling edge of sampling clock* 1 and enabled serial clock delay* 2 (escr register : sces bit = 1, eccr register : scde bit = 1) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : provide switch function whether sampling of reception data is performed at rising edge or falling edge of the serial clock. *2 : serial clock delay function is used to delay half clock for the output signal of serial clock. *3 : refer to ? (2) source clock/machine clock? for t mclk . parameter sym- bol pin name conditions value unit min max serial clock cycle time t scyc sck internal clock operating output pin : c l = 80 pf + 1 ttl. 5 t mclk * 3 ? ns sck sot delay time t slovi sck, sot ? 95 + 95 ns valid sin sck t ivshi sck, sin t mclk * 3 + 190 ? ns sck valid sin hold time t shixi sck, sin 0 ? ns sot sck delay time t sovhi sck, sot ? 4 t mclk * 3 ns sck sot sin 2.4 v 2.4 v 0.8 v t slovi 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc 2.4 v 0.8 v t scyc t sovhi t ivshi t shixi
mb95120 series 55 (8) i 2 c timing (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hd;dat have only to be met if the devi ce dose not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, but the requirement t su;dat 250 ns must then be met. parameter symbol pin name conditions value unit standard-mode fast-mode min max min max scl clock frequency f scl scl0 r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeat) start condition hold time sda scl t hd;sta scl0 sda0 4.0 ? 0.6 ? s scl clock ?l? width t low scl0 4.7 ? 1.3 ? s scl clock ?h? width t high scl0 4.0 ? 0.6 ? s (repeat) start condition setup time scl sda t su;sta scl0 sda0 4.7 ? 0.6 ? s data hold time scl sda t hd;dat scl0 sda0 0 3.45* 2 00.9* 3 s data setup time sda scl t su;dat scl0 sda0 0.25 ? 0.1 ? s stop condition setup time scl sda t su;sto scl0 sda0 4.0 ? 0.6 ? s bus free time between stop condition and start condition t buf scl0 sda0 4.7 ? 1.3 ? s s da0 s cl0 t wakeup t hd; s ta t s u;dat t hd; s ta t s u; s ta t low t hd;dat t high t s u; s to t buf f s cl
mb95120 series 56 (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter sym- bol pin name condi- tions value* 2 unit remarks min max scl clock ?l? width t low scl0 r = 1.7 k ? , c = 50 pf* 1 (2 + nm / 2) t mclk ? 20 ? ns master mode scl clock ?h? width t high scl0 (nm / 2) t mclk ? 20 (nm / 2 ) t mclk + 20 ns master mode start condition hold time t hd;sta scl0 sda0 ( ? 1 + nm / 2) t mclk ? 20 ( ? 1 + nm) t mclk + 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode start condition setup time t su;sta scl0 sda0 (1 + nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns master mode bus free time between stop condition and start condition t buf scl0 sda0 (2 nm + 4) t mclk ? 20 ? ns data hold time t hd;dat scl0 sda0 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl0 sda0 ( ? 2 + nm / 2) t mclk ? 20 ( ? 1 + nm / 2) t mclk + 20 ns master mode when assuming that ?l? of scl is not extended, the minimum value is applied to first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl0 (nm / 2) t mclk ? 20 (1 + nm / 2) t mclk + 20 ns minimum value is applied to interrupt at 9th scl . maximum value is applied to interrupt at 8th scl . scl clock ?l? width t low scl0 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl0 4 t mclk ? 20 ? ns at reception start condition detection t hd;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception
mb95120 series 57 (continued) (v cc = 3.3 v, av ss = v ss = 0.0 v, t a = ? 40 c to + 85 c) *1 : r, c : pull-up resistor and load capacitor of the scl and sda lines. *2 : ? refer to ? (2) source clock/machine clock? for t mclk . ? m is cs4 bit and cs3 bit (bit 4 and bit 3) of i 2 c clock control register (iccr) . ? n is cs2 bit to cs0 bit (bit 2 to bit 0) of i 2 c clock control register (iccr) . ? actual timing of i 2 c is determined by m and n values set by the machine clock (t mclk ) and cs4 to cs0 of iccr0 register. ? standard-mode : m and n can be set at t he range : 0.9 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 0.9 mhz < t mclk 1 mhz (m, n) = (1, 22) , (5, 4) , (6, 4) , (7, 4) , (8, 4) : 0.9 mhz < t mclk 2 mhz (m, n) = (1, 38) , (5, 8) , (6, 8) , (7, 8) , (8, 8) : 0.9 mhz < t mclk 4 mhz (m, n) = (1, 98) : 0.9 mhz < t mclk 10 mhz ? fast-mode : m and n can be set at t he range : 3.3 mhz < t mclk (machine clock) < 10 mhz. setting of m and n determines the ma chine clock that can be used below. (m, n) = (1, 8) : 3.3 mhz < t mclk 4 mhz (m, n) = (1, 22) , (5, 4) : 3.3 mhz < t mclk 8 mhz (m, n) = (6, 4) : 3.3 mhz < t mclk 10 mhz parameter sym- bol pin name condi- tions value* 2 unit remarks min max stop condition detection t su;sto scl0 sda0 r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception restart condition detection condition t su;sta scl0 sda0 2 t mclk ? 20 ? ns undetected when 1 t mclk is used at reception bus free time t buf scl0 sda0 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl0 sda0 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl0 sda0 t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl0 sda0 0 ? ns at reception data setup time t su;dat scl0 sda0 t mclk ? 20 ? ns at reception sda scl (at wakeup function) t wake- up scl0 sda0 oscillation stabilization wait time + 2 t mclk ? 20 ? ns
mb95120 series 58 5. a/d converter (1) a/d converter electrical characteristics (avcc = vcc = 1.8 v to 3.3 v, avss = vss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol value unit remarks min typ max resolution ? ?? 10 bit total error ? 3.0 ? + 3.0 lsb linearity error ? 2.5 ? + 2.5 lsb differential linear error ? 1.9 ? + 1.9 lsb zero transition voltage v ot avss ? 1.5 lsb avss + 0.5 lsb avss + 2.5 lsb v 2.7 v avcc 3.3 v avss ? 0.5 lsb avss + 1.5 lsb avss + 3.5 lsb v 1.8 v avcc < 2.7 v full-scale transition voltage v fst avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v 2.7 v avcc 3.3 v avr ? 2.5 lsb avr ? 0.5 lsb avr + 1.5 lsb v 1.8 v avcc < 2.7 v compare time ? 0.6 ? 140 s 2.7 v avcc 3.3 v 20 ? 140 s 1.8 v avcc < 2.7 v sampling time ? 0.4 ? s 2.7 v avcc 3.3 v, at external impedance < 1.8 k ? 30 ? s 1.8 v avcc < 2.7 v, at external impedance < 14.8 k ? analog input current i ain ? 0.3 ?+ 0.3 a analog input voltage v ain avss ? avr v reference voltage ? avss + 1.8 ? avcc v avr pin reference voltage supply current i r ? 400 600 a avr pin, during a/d operation i rh ?? 5 a avr pin, at stop mode
mb95120 series 59 (2) notes on using a/d converter ? about the external impedance of analog input and its sampling time a/d converter with sample and hold circuit. if the ex ternal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the register value and operating frequency or decrease the external im pedance so that the sampling time is longer than the minimum value. also, if the sampling time cannot be suffic ient, connect a capacitor of about 0.1 f to the analog input pin. ? about errors as |avr ? av ss | becomes smaller, values of relative errors grow larger. r c analog input note : the values are reference values. ? analog input equivalent circuit rc 2.7 v avcc 3.6 v 1.7 k ? (max) 14.5 pf (max) 1.8 v avcc < 2.7 v 84 k ? (max) 25.2 pf (max) comparator during sampling : on 0 5 10 15 20 25 30 35 40 0 10 20 30 40 50 60 70 80 90 100 01234 0 2 4 6 8 10 12 14 16 18 20 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] av cc 1.8 v av cc 2.7 v av cc 2.7 v ? the relationship between external impedance and minimum sampling time
mb95120 series 60 (3) definition of a/d converter terms resolution the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, an alog voltage can be divided into 2 10 = 1024. linearity error (unit : lsb) the deviation between the value along a straig ht line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) of a device a nd the full-scale transition point (?11 1111 1111? ?11 1111 1110?) compared with the actual conversion values obtained. differential linear error (unit : lsb) deviation of input voltage, which is required for ch anging output code by 1 lsb, from an ideal value. total error (unit: lsb) difference between actual and theoretical values, caused by a zero transition error, full-scale transition error, linearity error, quantum error, and noise. (continued) v fst 1.5 lsb 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h 1 lsb 0.5 lsb v ot av ss avr av ss v nt avr {1 lsb ( n ? 1 ) + 0.5 lsb} 1 lsb = avr ? av ss 1024 (v) total error of digital output n v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb ideal i/o characteristics total error digital output analog input analog input digital output [lsb] actual conversion characteristic actual conversion characteristic ideal characteristics n : a/d converter digital output value v nt : a voltage at which digital output transits from (n - 1) to n. =
mb95120 series 61 (continued) v (n + 1) t ? v nt 1 lsb av ss avr av ss avr av ss avr v nt av ss avr 001 h 002 h 003 h 004 h 3fc h 3fd h 3fe h 3ff h 001 h 002 h 003 h 004 h 3fd h 3fe h 3ff h n - 2 h n - 1 h n h n + 1 h {1 lsb n + v ot } v nt v ( n + 1 ) t full-scale transition error digital output actual conversion characteristic actual conversion characteristic ideal characteristics analog input v fst (measurement value) zero transition error digital output actual conversion characteristic actual conversion characteristic analog input v ot (measurement value) ? 1 differential linear error in digital output n linear error in digital output n v nt ? {1 lsb n + v ot } 1 lsb linearity error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics differential linear error digital output actual conversion characteristic actual conversion characteristic analog input ideal characteristics v fst (measurement value) v ot (measurement value) n : a/d converter digital output value v nt : a voltage at which digital output transits from (n ? 1) to n. v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] ideal characteristics = =
mb95120 series 62 6. flash memory program/erase characteristics *1 : t a = + 25 c, v cc = 3.0 v, 10000 cycles *2 : t a = + 85 c, v cc = 2.7 v, 10000 cycles *3 : this value comes from the technology qualification (u sing arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . parameter value unit remarks min typ max sector erase time (4 kbytes sector) ? 0.2* 1 3.0* 2 s excludes 00 h programming prior erasure. sector erase time (16 kbytes sector) ? 0.5* 1 12.0* 2 s excludes 00 h programming prior erasure. byte programming time ? 32 3600 s excludes system-level overhead. program/erase cycle 10000 ?? cycle power supply voltage at program/erase 2.7 ? 3.3 v flash memory data retention time 20* 3 ?? year average t a = + 85 c
mb95120 series 63 mask option * : low voltage detection reset and clock supervisor are options of 5-v products. no. part number mb95f128d mb95f128e mb95fv100d-101 mb95fv100d-102 specifying procedure setting disabled setting disabled setting disabled 1 clock mode select ? single-system clock mode ? dual-system clock mode dual-system clock mode changing by the switch on mcu board 2 lcdc booster circuit select ? internal division resistance ? booster circuit internal division resistance booster circuit internal division resistance booster circuit 3 low voltage detection reset* ? with low voltage detection reset ? without low voltage detection reset no no 4 clock supervisor* ? with clock supervisor ? without clock supervisor no no 5 oscillation stabilization wait time fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch fixed to oscillation stabilization wait time of (2 14 ? 2) /f ch
mb95120 series 64 ordering information part number package remarks mb95f128dpmc mb95f128epmc 100-pin plastic lqfp (fpt-100p-m20) mb95f128dpf mb95f128epf 100-pin plastic qfp (fpt-100p-m06) mb2146-301a (mb95fv100d-101pbt) mcu board included lcdc internal division resistance MB2146-302A (mb95fv100d-102pbt) included lcdc booster () 224-pin plastic pfbga (bga-224p-m08)
mb95120 series 65 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html (continued) 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujit s u limited f1000 3 1 s -c-2-1 14.00 0.10(.551 .004) s q 16.00 0.20(.6 3 0 .00 8 ) s q 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.145 0.055 (.0057 .0022) 0.0 8 (.00 3 ) "a" index .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb95120 series 66 (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/f j/datasheet/ef-ovpklv.html 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb95120 series f0701 the information for microcontroller suppor ts is shown in the following homepage. http://www.fujitsu.com/global/s ervices/microelectronics/produ ct/micom/support/index.html fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business promotion dept.

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