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version 3 june 3, 2004 2975 stender way, santa clara, california 95054 telephone: (800) 345-7015 ? fax: (408) 492-8674 printed in u.s.a. ? 2004 integrated device technology, inc. 3.3 volt m13 multiplexer idt82v8313
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best possible product. idt does not assume any responsibility for use of any circuitry described other than t he circuitry embodied in an idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third part ies which may result from its use. no license is granted by implication or otherwise under any patent, patent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products are not authorized for use as critical components in life support devices or systems un less a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of idt. 1. life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose failure to perform can be reasonably expecte d to cause the failure of the life support device or system, or to affect its safety or effectiveness.
table of contents table of contents iv june 3, 2004 *notice: the information in this document is subject to change without notice features ............................................................................................................................... ................................................................................. 1 package ............................................................................................................................... ............................................................................... 2-4 pin descriptions ............................................................................................................................... .......................................................... 5-12 register memory map ............................................................................................................................... ........................................... 13-16 register descriptions ............................................................................................................................... .............................................. 17 master reset/lock status....................................................................................................... ........................................................................ 17 revision/global pmon update .................................................................................................... .................................................................. 17 master bypass configuration.................................................................................................... ...................................................................... 18 master hdlc configuration...................................................................................................... ...................................................................... 19 master loopback configuration .................................................................................................. .................................................................... 20 master interface configuration................................................................................................. ....................................................................... 21 master alarm enable/network requirement bit .................................................................................... ......................................................... 22 master test .................................................................................................................... ................................................................................. 23 master interrupt source #1 ..................................................................................................... ........................................................................ 24 master interrupt source #2 ..................................................................................................... ........................................................................ 25 master interrupt source #3 ..................................................................................................... ........................................................................ 25 ds3 transmit configuration..................................................................................................... ....................................................................... 26 ds3 transmit diagnostic ........................................................................................................ ........................................................................ 27 ds3 pmon interrupt enable/status ............................................................................................... ................................................................ 28 ds3 lcv count lsb.............................................................................................................. ......................................................................... 28 ds3 lcv count msb.............................................................................................................. ........................................................................ 29 ds3 ferr count lsb............................................................................................................. ....................................................................... 29 ds3 ferr count msb............................................................................................................. ...................................................................... 29 ds3 exzs count lsb ............................................................................................................. ....................................................................... 30 ds3 exzs count msb ............................................................................................................. ...................................................................... 30 ds3 perr count lsb............................................................................................................. ....................................................................... 30 ds3 perr count msb............................................................................................................. ...................................................................... 31 ds3 cperr count lsb ............................................................................................................ ..................................................................... 31 ds3 cperr count msb ............................................................................................................ .................................................................... 31 ds3 febe count lsb ............................................................................................................. ....................................................................... 32 ds3 febe count msb ............................................................................................................. ...................................................................... 32 xfdl tsb configuration ......................................................................................................... ....................................................................... 33 xfdl interrupt status .......................................................................................................... ........................................................................... 33 xfdl tsb transmit data ......................................................................................................... ...................................................................... 34 rfdl tsb configuration ......................................................................................................... ....................................................................... 34
idt82v8313 3.3 volt m13 multiplexer table of contents iv june 3, 2004 *notice: the information in this document is subject to change without notice rfdl tsb interrupt control/status .............................................................................................. .................................................................. 35 rfdl tsb status ................................................................................................................ ........................................................................... 36 rfdl tsb receive data.......................................................................................................... ...................................................................... 36 mx23 configuration ............................................................................................................. ........................................................................... 37 demux ais insert register ...................................................................................................... ....................................................................... 38 mx23 mux ais insert register ................................................................................................... ................................................................... 38 mx23 loopback activate register................................................................................................ .................................................................. 39 mx23 loopback request insert register .......................................................................................... ............................................................. 39 mx23 loopback request detect register.......................................................................................... ............................................................ 40 mx23 loopback request interrupt register....................................................................................... ............................................................ 40 feac xboc tsb code............................................................................................................. ..................................................................... 41 rboc configuration/interrupt enable............................................................................................ ................................................................. 41 rboc interrupt status.......................................................................................................... .......................................................................... 42 ds3 frmr configuration ......................................................................................................... ...................................................................... 43 ds3 frmr interrupt enable (ace=0) .............................................................................................. .............................................................. 44 ds3 frmr additional configuration register (ace=1) ............................................................................. .................................................... 45 ds3 frmr interrupt status...................................................................................................... ...................................................................... 46 ds3 frmr status ................................................................................................................ .......................................................................... 47 ds2 frmr configuration ......................................................................................................... ...................................................................... 48 ds2 frmr interrupt enable...................................................................................................... ..................................................................... 49 ds2 framer interrupt status.................................................................................................... ....................................................................... 50 ds2 framer status .............................................................................................................. ........................................................................... 51 ds2 framer monitor interrupt enable/status..................................................................................... ............................................................. 52 ds2 frmr ferr count ............................................................................................................ .................................................................... 52 ds2 frmr perr count (lsb)...................................................................................................... ................................................................ 53 ds2 frmr perr count (msb)...................................................................................................... ............................................................... 53 mx12 configuration and control ................................................................................................. ................................................................... 54 mx12 loopback code select register............................................................................................. .............................................................. 55 mx12 ais insert register ....................................................................................................... ........................................................................ 56 mx12 loopback activate register................................................................................................ .................................................................. 56 mx12 loopback interrupt register ............................................................................................... .................................................................. 57 ds1 transmit and receive edge select ........................................................................................... ............................................................. 57 functional description ............................................................................................................................... ...................................... 59-78 data link ............................................................................................................................... .......................................................................... 79-92 functional timing ............................................................................................................................... .................................................... 93-94 loopback modes ............................................................................................................................... ..................................................... 95-100 dc electrical characteristics ............................................................................................................................... ............... 101-102 absolute maximum ratings ....................................................................................................... ................................................................... 101 recommended operating conditions(1) ............................................................................................ .......................................................... 101 dc electrical characteristics .................................................................................................. ...................................................................... 102
idt82v8313 3.3 volt m13 multiplexer table of contents iv june 3, 2004 *notice: the information in this document is subject to change without notice ac electrical characteristics ............................................................................................................................... ............... 103-114 microprocesser interface timing charac teristics/microprocessor read access ..................................................... ..................................... 103 microprocessor write access .................................................................................................... ................................................................... 104 timing characteristics ......................................................................................................... ......................................................................... 105 transmit ds3 input ............................................................................................................. .......................................................................... 106 transmit overhead input ........................................................................................................ ...................................................................... 106 transmit tributary input ....................................................................................................... ......................................................................... 107 transmit data link input....................................................................................................... ........................................................................ 107 transmit data link eom input................................................................................................... ................................................................... 108 transmit ds3 output ............................................................................................................ ........................................................................ 109 receive ds3 output ............................................................................................................. .........................................................................110 receive overhead output ........................................................................................................ .....................................................................111 transmit overhead output ....................................................................................................... .....................................................................112 receive tributary output ....................................................................................................... ........................................................................112 receive data link output....................................................................................................... .......................................................................113 jtag ............................................................................................................................... ................................................................................. 115-120 jtag timing solutionsl......................................................................................................... .........................................................................115 jtag ac electrical characteristics............................................................................................. ...................................................................116 identification register definitions............................................................................................ .......................................................................116 scan register sizes............................................................................................................ ...........................................................................116 system interface parameters .................................................................................................... ....................................................................117 jtag scan order................................................................................................................ ................................................................... 118-120 ordering information ............................................................................................................................... ............................................. 121 glossary ............................................................................................................................... .................................................................... 123-126 standards ............................................................................................................................... .................................................................. 127-128 index ............................................................................................................................... ............................................................................... 129-130
idt82v8313 3.3 volt m13 multiplexer table of contents iv june 3, 2004 *notice: the information in this document is subject to change without notice
list of tables list of tables vi june 3, 2004 *notice: the information in this document is subject to change without notice table 1 ? pin descriptions .................................................................................................... ................................................................................. 5-11 table 2 ? register memory map .................................................................................................. ......................................................................... 13-16 table 3 ? ferf status (x1 & x2 state).......................................................................................... ........................................................................... 62 table 4 ? c-bit parity mode ds3 c-bit assignments.............................................................................. ................................................................... 63 table 5 ? ds3 feac loopback control message .................................................................................... ................................................................. 65 table 6 ? ds3 feac alarm and status message.................................................................................... .................................................................. 65 table 7 ? ds1 bit oriented codes command and response message.................................................................. .................................................. 67 table 8 ? ds1 bit oriented priority message.................................................................................... ......................................................................... 67 table 9 ? ds1 bit oriented codes reserved messages ............................................................................. .............................................................. 67 table 10 ? data link format.................................................................................................... .................................................................................. 68 table 11 ? max jitter tolerance on ds if cat ii................................................................................ ......................................................................... 70
idt82v8313 3.3 volt m13 multiplexer list of tables vi june 3, 2004 *notice: the information in this document is subject to change without notice
list of figures list of figures viii june 3, 2004 *notice: the information in this document is subject to change without notice figure 1 ds3 framer block....................................................................................................... ......................................................................... 59 figure 2 ds3 frame .............................................................................................................. ............................................................................ 59 figure 3 b3zs coding ............................................................................................................ ........................................................................... 60 figure 4 transmit boc ........................................................................................................... ........................................................................... 66 figure 5 receive boc ............................................................................................................ ........................................................................... 66 figure 6 jitter definition ...................................................................................................... ............................................................................... 69 figure 7 maximum jitter tolerance on dsn interface inputs....................................................................... ...................................................... 70 figure 8 m23 multiplexer block.................................................................................................. ........................................................................ 71 figure 9 ds3 stuff block........................................................................................................ ............................................................................ 72 figure 10 ds2 framer block...................................................................................................... .......................................................................... 73 figure 11 ds2 frame ............................................................................................................ ............................................................................. 73 figure 12 g.747 frame format .................................................................................................... ....................................................................... 74 figure 13 m12 block ............................................................................................................. ............................................................................... 77 figure 14 ds2 stuff block....................................................................................................... ............................................................................. 78 figure 15 xfdl.................................................................................................................. .................................................................................. 79 figure 16 xfdl polled mode...................................................................................................... ......................................................................... 80 figure 17 xfdl interrupt mode ................................................................................................... ........................................................................ 81 figure 18 xfdl interrupt service routine........................................................................................ ................................................................... 81 figure 19 xfdl dma mode......................................................................................................... ........................................................................ 82 figure 20 xfdl normal data sequence ............................................................................................. ................................................................ 83 figure 21 xfdl underrun sequence................................................................................................ ................................................................... 84 figure 22 tdlint timing normal data tx.......................................................................................... ................................................................ 85 figure 23 tdleomi timing eomi after crc......................................................................................... ............................................................. 86 figure 24 rfdl ................................................................................................................. ................................................................................. 87 figure 25 rfdl polled mode...................................................................................................... ......................................................................... 88 figure 26 rfdl interrupt driven mode............................................................................................ .................................................................... 89 figure 27 rfdl interrupt service routine........................................................................................ ................................................................... 89 figure 28 rfdl dma mode......................................................................................................... ........................................................................ 90 figure 29 rfdl normal data and abort sequence ................................................................................... ......................................................... 91 figure 30 receive ds3 oh serial stream.......................................................................................... ................................................................. 93 figure 31 transmit ds3 oh serial stream......................................................................................... ................................................................. 93 figure 32 functional receiv e oh timing low-speed................................................................................ ......................................................... 93 figure 33 functional receive timing pmon........................................................................................ ............................................................... 94 figure 34 functional receive oh timing high-speed ............................................................................... ......................................................... 94 figure 35 ds3 diagnostic loopback............................................................................................... ..................................................................... 96 figure 36 ds3 line loopback ..................................................................................................... ........................................................................ 97 figure 37 ds2/g.747 demultiplex loopback........................................................................................ ............................................................... 98 figure 38 ds1/e1 demultiplex loopback ........................................................................................... ................................................................. 99 figure 39 microprocessor read access timing ..................................................................................... ........................................................... 103 figure 40 microprocessor write access timing.................................................................................... ............................................................. 104 figure 41 receive ds3 input timing .............................................................................................. ................................................................... 105 figure 42 transmit ds3 input timing ............................................................................................. ................................................................... 106 figure 43 transmit overhead input timing ........................................................................................ ............................................................... 106 figure 44 transmit tributary input timing....................................................................................... .................................................................. 107 figure 45 transmit data link input timing....................................................................................... ................................................................. 107
list of figures viii june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 46 transmit data link eom input timing................................................................................... ............................................................ 108 figure 47 transmit ds3 output timing ............................................................................................ ................................................................. 109 figure 48 receive ds3 output timing ............................................................................................. ................................................................. 110 figure 49 receive overhead output timing ........................................................................................ ............................................................. 111 figure 50 transmit overhead output timing ....................................................................................... ............................................................. 112 figure 51 receive tributary output timing ....................................................................................... ................................................................ 112 figure 52 receive data output link output timing ................................................................................ .......................................................... 113 figure 53 standad jtag timing ................................................................................................... .................................................................... 115
? 2004 integrated device technology, inc. *notice: the information in this document is subject to change without notice dsc -6143/2 idt an the idt logo are registered trademarks of integrated device technology, inc. 1 june 3, 2004 ? ? ? m23 mux ds3 tx framer txds1clk1-4 b3zs encoder tx3pos/tx3d tx3clk tx3neg/tx3fp m12 mux #2-7 txds1d1-4 txds1clk5-28 txds1d5-28 xboc tx feac 1 2-7 m21 mux #1 b3zs decoder rx3pos/rx3d rx3clk rx3neg/rx3fp rboc rx feac rfdl rx rdlclk pmon rdlsig/rdleom rx o/h access roclk,rodat,rmfp,rmsf, rohp,rohhclk rohfp,roh,rlos,rexz, rais,roof,reed,rferf 6143 drw01 rxds1clk1-4 rxds1d1-4 rxds1clk5-28 rxds1d5-28 1 2-7 a8/trs a7-0 d7-0 ale cs wr rd rst int xfdl tx hdlc tx o/h access m12 mux #1 m32 mux ds2 rx framer #1 ds2 rx framer #2-7 ds3 rx framer m21 mux #2-7 jtag ds2 tx framer #1 ds2 tx framer #2-7 microprocessor port tdleomi tdlclk/tdlint tdlsig/tdludr toh toen tohclk gd2clk tdi tdo trst tclk rdlclk/rdlint td2clk ? ? ? ? ? ? ? ? ? timfp tohfp ticlk tms 3.3 volt m13 multiplexer features: ? full featured single chip m13-ideal for upgrading existing multi-line t1/e1 line cards to single line channelized t3 service ? small footprint 17mm x 17mm bga package and 208 pin pqfp packages available ? 3.3v operation with 5v tolerant i/o ? 28 independent ds1 clock inputs each with programmable clock edge adapter ? 28 independent ds1 outputs eatch with programmable clock edge adapter ? m12 bypass for direct input of ds2 in to the m23 multiplexer ? programmable clock edge ? supports m23 or c-bit parity format formats ? g.747 formats for e1 to be multiplexed onto a ds3 ? ds2 lof detectors and ds2 ais ds2 x-bit access ? ds2 transmit/receive x-bit control/status ? ds2 f, m, and x bit insertion ? ds2 ferf and ais under microprocessor control ? transmission of rai and reserved bit under microprocessor control ? programmable preemptive inversion of c-bits for remote loopback ? ds3 idle signal generators ? ds3 los, lof, p-bit parity, c-bit parity, ais and idle detectors ? ds3 x-bit access ? ds3 transmit and receive ais generation and detection ? ds3 m-frame and m-subframe boundary indications idt82v8313
package 2 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice package pbga: 1mm pitch, 17mm x 17mm (bb208-1, order code: bb) top view a b c d e f g h j k l m n p r t 12345678910111213141516 a1 ball pad corner 6143 drw02 tclk td2clk td1 dat1 rd1 dat1 rd1 clk1 rd1 dat2 td1 dat3 rd1 clk3 rd1 clk4 td1 clk5 td1 clk6 td1 clk7 rd1 dat8 rd1 clk8 td1 dat9 rd1 dat9 tpos_ dat gd2clk timfp td1 clk1 td1 dat2 td1 clk2 rd1 dat3 gnd td1 clk4 rd1 dat5 rd1 dat6 rd1 dat7 td1 dat8 td1 clk8 rd1 clk9 td1 clk9 tneg_ mfp ticlk rais tdlclk _int tdlsig_ udr rd1 clk2 td1 clk3 td1 dat4 rd1 dat4 td1 dat5 td1 dat6 td1 dat7 rd1 clk7 td1 clk10 rd1 dat10 td1 dat10 rodat roclk rmfp rdlclk _int tdleomi gnd rd1 clk5 rd1 clk6 td1 clk11 rd1 dat11 tdi dat11 rd1 clk10 rohp tohclk tohfp rdlsig _eom td1 clk12 rd1 dat12 td1 dat12 rd1 clk11 rmsfp toh tohen rohfp td1 clk13 rd1 dat13 td1 dat13 rd1 clk12 roh rohclk rlos v cc gnd gnd gnd gnd rd1 dat14 td1 dat14 rd1 clk13 rclk roof_ red rferf gnd gnd gnd gnd td1 dat5 rd1 clk14 td1 clk14 rneg_ lcv rpos_ dat rexz gnd gnd gnd gnd rd1 dat15 td1 clk15 rd1 clk15 d1 d0 int gnd gnd gnd gnd td1 dat16 rd1 dat16 td1 clk16 d5 d4 d3 d2 rd1 clk16 td1 dat17 rd1 dat17 td1 clk17 ale cs d7 d6 rd1 clk17 td1 dat18 rd1 dat18 td1 clk18 a2 a1 a0 rd1 dat28 td1 clk27 v cc td1 clk23 td1 clk22 rd1 clk18 td1 dat19 rd1 dat19 a4 a3 ex_ rst td1 clk28 jtag_ tdi rd1 clk26 rd1 dat26 td1 clk25 rd1 dat25 rd1 clk24 jtag_ tclk rd1 dat23 rd1 dat22 td1 clk21 td1 clk19 rd1 clk19 a5 a8 rd rd1 cl k28 rd1 clk27 td1 dat27 jtag_ tdo rd1 clk25 jtag_ tms td1 clk24 td1 dat24 td1 dat23 td1 dat22 rd1 dat21 rd1 clk20 td1 dat20 a6 a7 wr jtag _ trst td1 dat28 rd1 dat27 td1 clk26 td1 dat26 td1 dat25 rd1 dat24 rd1 clk23 rd1 clk22 rd1 clk21 td1 dat21 td1 clk20 rd1 dat20 v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc
package 3 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice pqfp: 0.50mm pitch, 28mm x 28mm (ds208-1, order code: ds) top view note: 1. jtag 2. nc = no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 pin 1 157 158 159 160 161 162 163 164 165 166 167 169 168 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 104 103 101 100 99 98 97 96 95 94 92 93 90 89 88 87 86 85 84 83 82 81 80 79 77 76 75 74 73 72 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 102 91 78 71 6143 drw03 td1clk9 rd1clk9 td1dat10 rd1dat10 td1clk10 rd1clk10 td1dat11 rd1dat11 td1clk11 nc (2) rd1clk11 td1dat12 rd1dat12 td1clk12 rd1clk12 td1dat13 nc (2) rd1dat13 td1clk13 rd1clk13 td1dat14 rd1dat14 td1clk14 rd1clk14 gnd nc (2) td1dat15 rd1dat15 td1clk15 rd1clk15 td1dat16 nc (2) rd1dat16 td1clk16 rd1clk16 v cc td1dat17 nc (2) rd1dat17 td1clk17 rd1clk17 td1dat18 rd1dat18 nc (2) td1clk18 gnd rd1clk18 td1dat19 rd1dat19 td1clk19 rd1clk19 td1dat20 rd1dat20 td11clk20 rd1clk20 td1dat21 rd1dat21 td1clk21 rd1clk21 td1dat22 gnd v cc rd1dat22 nc (2) td1clk22 rd1clk22 td1dat23 rd1dat23 td1clk23 rd1clk23 td1dat24 jtag_tclk (1) rd1dat24 td1clk24 rd1clk24 td1dat25 gnd jtag_tms (1) rd1dat25 td1clk25 rd1clk25 td1dat26 rd1dat26 jtag_tdo (1) td1clk26 rd1clk26 td1dat27 rd1dat27 td1clk27 jtag_tdi (1) rd1clk27 td1dat28 rd1dat28 td1clk28 timfp jtag_trst (1) v cc gnd rst rd wr a8 a7 a6 a5 a4 a3 a2 a1 a0 ale cs d7 v cc d6 d5 nc (2) d4 d3 d2 gnd d1 d0 int rdlsig/rdleom rdlclk/rdlint rneg/rlcv rpos/rdat nc (2) gnd rclk/vclk rexz roof/rred rferf rlos rohclk roh rohfp tohen toh rmsfp tohfp tohclk nc (2) rohp rmfp roclk v cc gnd rodat gd2clk tneg/tmfp rais tpos/tdat tclk ticlk tdlclk/tdlint td2clk tdlsig/tdludr tdleomi td1dat1 rd1dat1 td1clk1 gnd v cc rd1clk1 nc (2) td1dat2 rd1dat2 td1clk2 rd1clk2 gnd gnd td1dat3 v cc rd1dat3 td1clk3 rd1clk3 gnd td1dat4 gnd rd1dat4 td1clk4 rd1clk4 td1dat5 nc (2) rd1dat5 td1clk5 rd1clk5 td1dat6 rd1dat6 td1clk6 nc (2) rd1clk6 td1dat7 rd1dat7 td1clk7 rd1clk7 nc (2) v cc gnd td1dat8 rd1dat8 td1clk8 rd1clk8 td1dat9 rd1dat9 rd1clk28
package 4 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
pin description 5 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice pin descriptions table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description rclk receive clock i 26 h1 this is the ds3 receive clock input. rclk is nominally a 44.736 mhz, 50% duty cycle clock. rpos/rdat receive positive pulse/receive data i 29 j2 in dual rail mode, this pin is rpos and represents the positive pulses of a b3zs-encoded signal. in single rail mode, this pin is rdat and represents the unipolar ds3 input data. the m13 can be configured to sample data on either the rising or falling edge of rclk. rneg/rlcv receive negative pulse/ receive line code violation i 30 j1 in dual rail mode, this pin is rneg and represents the negative pulses of a b3zs-encoded signal. in single rail mode, this pin is rlcv and can be used to insert line code violations on the ds3 input. the m13 can be configured to sample data on either the rising or falling edge of rclk. roclk receive output clock o 10 d2 the ds3 receive output clock is a buffered version of the input rclk. like the rclk, this is nominally a 44.736 mhz, 50% duty cycle clock. rexz, rlos, rmfp, rmsfp, and rodat are updated on the falling edge of roclk. rodat receive output data o 7 d1 this is a 44.736 mb/s ds3 nrz receive data stream decoded from the b3zs line signal. rodat is aligned to the frame alignment signals rmfp, rmsfp, and rohp. rodat is updated in the falling edge of roclk. rmfp receive m- frame pulse o 11 d3 the receive m-frame pulse signal and marks the first bit in the m-frame (x1) of the ds3 data on rodat. in an oof (out of frame) condition the m13 internal counters will maintain the old m-frame alignment position. when the framer regains frame alignment the rmfp timing will be updated to the new timing. this may result in a change of frame alignment. rmfp is updated on the falling edge of roclk. rmsfp receive m- subframe frame pulse o 16 f1 the receive m-subframe pulse signal and marks the first bit of each m-subframe (x, p, and m) in each m-subframe of t he ds3 on rodat. in an oof (out of frame) condition the m13 internal counters will maintain the old m-frame alignment position. when the framer regains frame alignment the rmsfp timing will be updated to the new timing. this may result in a change of frame alignment. rmsfp is updated on the falling edge of roclk. rohp receive overhead pulse o 12 e1 the receive overhead pulse signal and marks the overhead bit positions (x, p, m, c, and f) in the ds3 data on rodat. in an oof (out of frame) condition the m13 internal counters will maintain the old frame alignment position. when the framer regains frame alignment, the rohp timing will be updated to the new timing. this may result in a change of frame alignment. rohp is updated in the falling edge of roclk. rohclk receive overhead clock o 21 g2 the receive overhead clock and transitions on each overhead bit. rohclk is nominally a 526 khz. rais, rferf, rferr, ridl, roh, rohfp, and roof are updated on the falling edge of rohclk. roh receive overhead data o 20 g1 the receive overhead data signal transmits the overhead bits, c, f, m, p, and x bits from the receive ds3 stream. roh is updated on the falling edge of rohclk. rohfp receive overhead frame pulse o 19 f4 the receive overhead frame pulse is used to mark the positions of the overhead bits within the overhead stream, roh. rohfp will remain high during the x1 overhead bit. rohfp is updated on the falling edge of rohclk. rlos receive loss of signal o 22 g3 the receive loss of signal will remain high when the dual rail nrz format stream is selected or when a loss of signal condition is detected (175 successive zeros on rpos and rneg). when the one?s density is greater than 33% for 175 +/i 1 bit period on the rpos and rneg inputs, rlos will be set low. rlos is updated on the falling edge of roclk.
pin description 6 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice rexz receive excessive zeros o 25 j3 the receive excessive zero indicates the detection of an excessive zero condition. when 3 or more successive zeros are received on the ds3 bipolar stream rexz pulses high for one roclk cycle. in the uni-polar mode, rexz is low. rexz is updated on the falling edge of roclk. rais receive alarm indication signal o 4 c3 the receive alarm indication signal is used to indicate and ais (alarm indication) in the received ds3 signal. the rais will be set high when the ais pattern has been detected for 2.23 ms or 13.5 ms as programmed by software. when the ais pattern is absent in the ds3 signal for 2.23 ms or 13.5 ms the rais will be set low. rais is updated on the falling edge of rohclk. roof/rred receive out of frame/receive red alarm o 24 h2 roof/rref will be roof when the redo bit in the master alarm enable register is 0 and will indicate an receive out-of-frame error. when no out-of-frame errors exist the roof will be low. roof will be high when there is an out-of-frame condition: 3 out of 16 (default) or 3 out of 8 consecutive f-bit errors are detected, or when more m-bit errors are detected in 3 out of 4 consecutive m-frames. roof is updated on the falling edge of rohclk. roof/rred will be rred when the redo bit the master alarm enable register is 1 and will indicate an out-of-frame condition or a ds3 loss of signal condition. a ds3 out-of-frame condition is considered when there are no transitions for 2.23 ms or 13.5 ms (software programmable) and rred will be set high. rred will be reset low when the out-of-frame condition or loss of signal condition are absent for 2.23 or 13.5 ms. rred is updated on the falling edge of rohclk. rferf receive far end receive failure o 23 h3 the receive far end receive failure reflects the internal state of the internal ferf but the rferf state is delayed by two m-frames. ferf is set high when both x1 and x2 are 0 in the m-frame. when x1 and x2 are both high in the m-frame, ferf is set low. otherwise, ferf remains in its previous state when x1 x2 in the current frame. the rferf latency is used to provide better than 99.99% chance of freezing (holding ferf in its previous state) upon a valid state value during an out-of-frame. rferf is updated every m-frame on the falling edge on rohclk. rdlclk/ rdlint receive data link clock/ receive data link interrupt o 31 d4 rdlclk/rdlint will be rdlclk when the rexhdlc bit in the master hdlc configuration register is set to 1 and is used as the receive data link clock when an external hdlc receiver is selected. the rdlclk is the clock for the external processing of the data link signal extracted by the ds3 framer. rdlclk is nominally a 28.2 khz clock that is low for at least 1.9us per cycle and is updated 3 times per m-frame. rdlclk is updated on the falling edge of the rohclk. rdlclk/rdlint will be rdlint when the rexhdlc bit in the master hdlc configuration register is set to 0 and is used as the data link interrupt when an internal hdlc receiver is selected. when an hdlc receiver event occurs the rdlint will reflect a change in status. by reading the interrupt enable/status register, the interrupt will be cleared, both the register and the rdlint pin. rdlint is updated on the falling edge of rohclk. rdlint is a configurable active low open-drain out or active high open-drain output. in the case where an external dma device is used, rdlint would be directly connected, however if the interrupt is being handled by a microprocessor, the rfdl may be wired-ored with the int output. in this later case, rdlint should be configured as a active-low open drain output. table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description
pin description 7 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice rdlsig/ rdleom receive data link signal/ receive data link end of message o 32 e4 rdlsig/rdleom will be rdlsig when the rexhdlc bit in the master hdlc configuration register is set to 1 and is used as the receive data link signal when an external hdlc receiver is selected. the rdlsig is the c-bit message used in c-bit parity mode and transmits the three c-bits from the fifth m-subframe in the ds3 frame. rdlsig is updated on the falling edge of the rdlclk. rdlsig/rdleom will be rdleom when the rexhdlc bit in the master hdlc configuration register is set to 0 and is used as the receive end of message signal when an internal hdlc receiver is selected. rdleom is used to denote the last byte of a sequence that is read from the hdlc receiver or to denote an overflow condition in the receive hdlc buffer. rdleom is updated on the fall- ing edge of rohclk. in order to clear/deassert the rdleom the supervising micropro- cessor must read the interrupt enable/status register. in the case where rdleom would be connected to a supervising microprocessor, an external dma is used. the rdleom would be programmed to be active-low, open-drain and wired-ored with the int to signal the microprocessor that the a complete message is ready. rd1clk1-28 receive ds1 clock o *see tqfp table below for details. *see bga table below for details, rd1clk1-28 are the receive ds1 clocks used in conjunction with the rd1dat. these clocks are at the t1 nominal rate of 1.544mhz, but will have jitter due to the demultiplexing and destuffing processes. rd1dat28-1 can be programmed to update on either the rising or falling edge of rd1clk. for g.747, the internal m12 multiplexers still uses the rd1clks to clock rd1dat out, however every fourth clock, rd1clk4, 8, 12, 16, 20, 24, and 28 clocks, is unused and in turn output low. these clocks run at the nominal rate of 2.048mhz but will have jitter due to the demultiplexing and destuffing processes. if a ds2 is inserted into the m13, thereby bypassing the m12 multiplexer, every fourth clock rd1clk4, 8, 12, 16, 20, 24, and 28 can be used as a ds2 clock. in this case the unused clocks for that group will output low. the ds2 clock has a nominal rate of 6.312mhz. rd1dat1-28 receive ds1 data o *see tqfp table below for details. *see bga table below for details rd1dat1-28 is the ds1 data demultiplexed from the incoming ds3 stream. rd1dat1-28 are updated on either the rising or falling edge of the corresponding rd1clk1-28. in g.747, where the m12 multiplexers mux e1 data, rd1dat 4, 8, 12, 16, 20, 24, and 28 are held low, while the remaining streams operate at a nominal 2.048mhz data rate. m12 multiplexers are bypassed and ds2 data is output the fourth stream of the group is used to output data. the remaining three streams of the group will be held low. td1clk1-28 transmit ds1 clock i *see tqfp table below for details. *see bga table below for deatils the transmit ds1 clock, td1clk1-28 is used to sample incoming data on td1dat1-28 to be multiplexed into a ds3. the m13 expects a nominal 1.544mhz clocks and expects minimal jitter and wander of a standard ds1. td1dat1-28 are sampled on either the rising or falling edge of td1clk1-28. in g.747 multiplexing not all td1 inputs are used. in this case, every fourth input (td1clk4, 8, 12, 16, 20, 24, and 28) is unused, ignored and must be tied to gnd. the remaining clocks should be running at a nominal rate of 2.048mhz and expects minimal jitter and wander of a standard ds1. when the internal m12 multiplexers are bypassed, the m13 device will use every fourth clock (td1clk4, 8, 12, 16, 20, 24, and 28) as the ds2 input clock. in this case, the remaining clocks are unused, ignored and the unused inputs must be tied to gnd. td1dat1-28 transmit ds1 data i *see tqfp table below for details. *see bga table below fo details the transmit ds1 data td1dat is the input data that is multiplexed in to a ds3. input data can be programmed to sample on either the rising or falling edges of td1clk1-28. in g.747, where the m12 multiplexers mux e1 data, every fourth data stream (td1dat4, 8, 12, 16, 20, 24, and 28) is ignored and must be tied to gnd. in cases where a ds2 is inserted directly into the m23 stage, every fourth td1dat (td1dat4, 8, 12, 16, 20, 24, and 28) can be used. in this case the remaining td1dat streams of the group are ignored and must be tied to gnd. table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description
pin description 8 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice gd2clk generated ds2 clock o 6 b2 in m13 and c-bit parity modes, this is the transmit generated ds2 clock. in m13 operation this clock is nominally a 6.311993 mhz clock which translates to a 39.1% stuffing ratio. in c-bit parity mode this clock is nominally a 6.3062723 mhz clock, which translates to a stuffing rate of 100% (used for c-bit parity). the gd2clk may be tied directly to the td2clk clock. td2clk transmit ds2 clock i 206 a2 the td2clk is the transmit ds2 clock and is the clock used in the m12 multiplexer. td2clk is nominally a 6.312 mhz, 50% duty cycle clock and can be derived from the gd2clk. tdlsig/ tdludr transmit data link signal/ transmit data underrun o 205 c5 the tdlsig/tdludr will be transmit data link, tdlsig, when the texhdlc bit in the master hdlc configuration register is a logic 1. when an external hdlc receiver is selected, tdlsig will carry the the three c-bits in m-subframe #5 in the ds3. when c-bit parity mode is not enabled tdlsig is ignored. tdlsig is sampled on the rising edge of tdlclk.the tdlsig/tdludr will be the transmit data link underrun, tdludr, when the texhdlc bit in the master hdlc configuration register is a logic 0. when an internal hdlc receiver is selected, tdludr is asserted when an internal hdlc transmitter underruns. tdludr can be cleared (deasserted) by writing to the xfdl interrupt status register. tdludr is a programmable polarity, open-drain output. on reset, tdlsig/tdludr is tdlsig. the texhdlc register should be programmed after reset to the appropriate mode. when an external dma is used, tdludr will be configured as an active-low output and wired-ored with the int output and routed to the supervising microprocessor. in that way, in the case of a transmit buffer underrun the supervising microprocessor will be notified. tdlclk/ tdlint transmit data link clock/ transmit data link interrupt o 207 c4 the tdlclk/tdlint will be transmit data link clock, tdlclk, when the texhdlc bit in the master hdlc configuration register is a logic 1. when an external hdlc receiver is selected, tdlclk will provide the timing for the external maintenance data link inserted by the ds3. tdlclk is nominally a 28.2 khz clock which is low for at least 1.9us per cycle. tdlclk is updated on the falling edge of the tohclk and cycles three times per m-frame (one for each c-bit). the tdlclk/tdlint will be the transmit data link interrupt, tdlint, when the texhdlc bit in the master hdlc configuration register is a logic 0. when an internal hdlc receiver is selected, tdlint is asserted when the last data byte is written to the internal hdlc transmitter. a write to the xfdl configuration register will end the current message transmission while a write to the xfdl transmit data register will provide more data. tdlint is a programmable polarity, open-drain output. on reset, tdlclk/tdlint is tdlint. the texhdlc register should be programmed after reset to the appropriate mode. when an external dma is used, tdlint will be configured as an active-low output and wired-ored with the int output and routed to the supervising microprocessor. in that way, the supervising microprocessor will be notified and can service the xfdl. tdlemoi transmit data link end of message input i 204 d5 the transmit data link end of message input, tdlemoi, is an alternate method for an external dma controller to signal the end of the transmitted message to the hdlc transmitter. as the tdlemoi is an alternative to writing the xfdl configuration register, appropriately the tdlemoi will set the eom bit in the xfd: configuration register. the tdlemoi input may be asserted before or after the write of the last byte, but must be asserted before the next byte (within 210 us of the last assertion of tdlint or the int bit in the xfdl status register). if no data transmission is pending, tdlemoi is ignored. table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description
pin description 9 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ticlk transmit input clock i 1 c2 the transmit input clock, ticlk, provides the timing for the ds3 input. ticlk is nominally a 44.736 mhz, 50% duty cycle clock. timfp is sampled on the rising edge of ticlk. timfp transmit input m-frame frame pulse i 208 b3 the transmit m-frame pulse, timfp, provides the timing/alignment of the m-frame within the ds3 data, tdat. the first bit (x1) of the m-frame on tdat will occur within several ticlk cycle and will be confirmed by the output on tmfp. timfp may be pulled low if this kind of feedback is not required. timfp is sampled on the rising edge of ticlk. toh transmit overhead data i 17 f2 the transmit overhead data, toh, represents the overhead bits (c, f, m, p, and x) that may be inserted into the transmitted ds3. toh is sampled on the rising edge of tohclk. tohen transmit overhead enable i 18 f3 the transmit overhead insertion, tohen, is the enable signal that is used in conjunction with the toh, data input. when tohen is high the associated data on toh will be inserted in to the ds3. when the tohen is low, the internal ds3 framer generates and inserts the ds3 overhead bits into the output ds3 stream. tohen is sampled on the rising edge of tohclk. tohfp transmit overhead frame pulse o 15 e3 the transmit overhead frame position, tohfp, marks the beginning of the first m-frame, and aligns the toh data to the ds3 m-frame. tohfp will be high during the x1 overhead bit position. tohfp is updated on the falling edge of tohclk. tohclk transmit overhead clock o 14 e2 the transmit overhead clock, tohclk, provides the timing transmit overhead bits. tohclk is nominally a 526 khz clock. tohfp is updated on the falling edge of tohclk. toh and tohen are sampled on the rising edge of tohclk. jclk transmit ds3 clock o 2 a1 the transmit clock, tclk, provides timing for other circuitry to synchronize with the ds3 transmitter. tclk is nominally a 44.736 mhz, 50% duty cycle clock. tpos/tdat transmit ds3 positive pulse/ transmit ds3 data o 3 b1 in dual rail mode, tpos/tdat, is tpos and represents the positive pulses of a b3zs-encoded line. tpos is updated on the falling edge of tclk by default but may be configured to update on the rising edge of tclk. in single rail mode, tpos/tdat, is tdat and represents the unipolar ds3 output data. like the tpos, tdat is updated on the falling edge of tclk by default but may be configured to update on the rising edge of tclk. tneg/tmfp transmit ds3 negative pulse/ transmit multi- frame pulse o 5 c1 in dual rail mode, tneg/tmfp, is tneg and represents the negative pulses of a b3zs-encoded line. tneg is updated on the falling edge of tclk by default but may be configured to update on the rising edge of tclk. in single rail mode, tneg/tmfp, is tmfp and represents the transmit multi-frame pulse. tmfp will be high during the first bit of the ds3 multiframe output on tdat. tmfp is updated on the falling edge of tclk by default but may be configured to update on the rising edge of tclk. int interrupt o 33 k3 int is the output interrupt pin. when an interrupt occurs in any of the tsbs, ds2 frmr, ds3 frmr, mx12, mx23, pmon, or rboc, int will go low, unless the interrupt is masked. in order to clear int , all pending interrupt tsbs must be read and cleared, oth- erwise int will remain low. int is an open drain output so it can be wired-ored with other active-low open-drain output pins of the device. cs chip select i 45 m2 this active low input is used by a microprocessor to activate the microprocessor port. cs must go low for at least once after powerup. if cs is not used it must be tied to an inverted version of rst . rd microprocessor read i 57 r3 this active low input controls the direction of the data bus lines (d0-7) during a micropro- cessor access. when rd is low, d0-7 are output. wr microprocessor write i 56 t3 this active low input controls the direction of the data bus lines (d0-7) during a micropro- cessor access. when wr is low, d0-7 are input. table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description
pin description 10 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice d0-7 microprocessor data i/o *see tqfp table below for details *see bga table below for deatils these pins are the data bits of the microprocessor port. a0-8 microprocessor address i *see tqfp table below for details *see bga table below for details these address lines access all internal memories. rst reset i 58 p3 this input puts the idt82v8313 into a reset state that clears the device internal counters and registers. the reset pin must be held low for a minimum of 100ns to properly reset the device. this pin has a weak internal pull-up resistor. ale address latch enable i 46 m1 the address latch enable is an active high input that will latch the a0-7 address bus. the ale is used in a multiplexed address/data microprocessor environment. the ale has a weak internal pull-up resistor. vcc vcc i *see tqfp table below for details *see bga table below for details this is the +3.3 volt power supply for the core of the device. vcc vcc i *see tqfp table below for details *see bga table below for details this is the +3.3 volt power supply for the i/o of the device. gnd ground i *see tqfp table below for details *see bga table below for details ground rail. tdi jtag test serial data in i p5 jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up when not driven. tdo jtag test serial data out o r7 jtag serial data is output on this pin on the falling edge of tck. this pin is held in high- impedance state when jtag scan is not enabled. trst jtag test reset i t4 asynchronously initializes the jtag test acce ss port controller by putting it in the test- logic-reset state. this pin is pulled high by an internal pull-up when not driven. this pin should be pulsed low on power-up, or held low, to ensure that the idt72v71660 is in the normal functional mode. tclk jtag test clock i p11 provides the clock to the jtag test logic. tms jtag test mode select i r9 jtag signal that controls the state transitions of the test access port controller. this pin is pulled high by an internal pull-up when not driven. table 1 ? pin descriptions symbol name i/o tqfp pin no. bga pin no. description
pin description 11 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice tqfp pin number table symbol name i/o pin number rd1clk1-28 receive ds1 clock o 198, 193, 186, 180, 175, 170, 166, 159, 155, 151, 146, 142, 137, 133, 127, 122, 116, 110, 106, 102, 98, 91, 87, 82, 76, 71, 66, 62. rd1dat1-28 receive ds1 data o 202, 195, 188, 182, 177, 173, 168, 161, 157, 153, 149, 144, 139, 135, 129, 124, 118, 114, 108, 104, 100, 94, 89, 84, 78, 74, 69, 64. td1clk1-28 transmit ds1 clock i 201, 194, 187, 181, 176, 172, 167, 160, 156, 152, 148, 143, 138, 134, 128, 123, 117, 112, 107, 103, 99, 92, 88, 83, 77, 72, 68, 63. td1dat1-28 transmit ds1 data i 203. 196, 190, 184, 179, 174, 169, 162, 158, 154, 150, 145, 141, 136, 130, 126, 120, 115, 109, 105, 101, 97, 90, 86, 81, 75, 70, 65. d0-7 microprocessor data i/o 34, 35, 37, 38, 39, 41, 42, 44. a0-8 microprocessor address i 47, 48, 49, 50, 51, 52, 53, 54, 55. vcc vcc i 9, 43, 60, 95, 121, 164, 189, 199. gnd ground i 8, 11, 27, 36, 59, 80, 96, 111, 132, 163, 183, 185, 191, 192, 200. bga pin number table symbol name i/o pin description rd1clk1-28 receive ds1 clock o a 5, c6, a8, a9, d11, d12, c13, a14, b15, d16, e16, f16, g16, h16, j16, l13, m13, n14, r16, r15, t13, t12, t11, p10, r8, p6, r5, r4. rd1dat1-28 receive ds1 data o a4, a6, b7, c9, b10, b11, b12, a13, a16, c15, d14, e14, j14, k15, l15, m15, n16, j15, r14, p13, t10, p9, p7, t6, n4. td1clk1-28 transmit ds1 clock i b4, b6, c7, b9, a10, a11, a12, b14, b16, c14, d13, e13, f13, h16, j15, k16, l16, m16, p15, t15, p14, n13, n12, r10, p8, t7, n5, p4. td1dat1-28 transmit ds1 transmit i a3, b5, a7, c8, c10, c11, c12, b13, a15, c16, d15, e15, f1 5, g15, h14, k14, l14, m14, n15, r16, t14, r13, r12, r11, t9, t8, r6, t5. d0-7 microprocessor data i/o k2, k1, l4, l3, l2, l1, m4, m3. a0-8 microprocessor address i n3, n2, p2, p1, r1,t1, t2, r2. vcc vcc i g4, h4, j4, k4, n6, n7, n8, n9, n10, n11, k13, j13, k13, g13, d6, d7, d8, d9, d10. gnd ground i b8, d6, g7-g10, h7-h10, j7-j10, k7-k10.
pin description 12 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
register memory map 13 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice register memory map table 2 ? register memory map reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name 00 h r/w ds3rcact ds3tcact ds2tcact - - - - reset master reset/clock status 01 h r id7 id6 id5 id4 id3 id2 id1 id0 revision/global pmon update 02 h r/w exd2clk byp7 byp6 byp5 byp4 byp3 byp2 byp1 master bypass configuration 03 h r/w rexhdlc texhdlc - - reompol tudrpol rintpol tintpol master hdlc configuration 04 h r/w - - - lineais1 lineais2 llbe dlbe master loopback configuration 05 h r/w - - - tinv tfall tuni rinv rfall master interface configuration 06 h r/w tnr rnr altfebe redo red2alme ds2alme red3alme ds3alme master alarm enable/network requirement bit 07 h r/w - - - - dbctrl - hizdata hizio master test 08 h r reg2 reg3 xfdlint mx23 ds3frmr rfdli nt rfdleom rboc master interrupt source #1 09 h r xfdludr ds2frmr7 ds2frmr6 ds2frmr5 ds2frmr4 ds 2frmr3 ds2frmr2 ds2frmr1 master interrupt source #2 0a h r ds3pmon mx12 7 mx12 6 mx12 5 mx12 4 mx12 3 mx12 2 mx12 1 master interrupt source #3 0b h ---------reserved 0c h r/w cbtran ais idl ferf sbow - - cbit ds3 tran configuration 0d h r/w dlos dlcv - dferr dmerr dcperr dperr dfebe ds3 tran diagnostic 0e h - 11 h ---------reserved 11 h r/w - - - - - inte intr ovr ds3 pmon interrupt enable/status 12 h - 13 h -- - - - - - - reserved 14 h r lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 ds3 pmon lcv count (lsb) 15 h r lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 ds3 pmon lcv count (msb) 16 h r ferr7 ferr6 ferr5 ferr4 ferr3 ferr2 ferr1 ferr0 ds3 pmon ferr count (lsb) 17 h r - - - - - - ferr9 ferr8 ds3 pmon ferr count (msb) 18 h r exzs7 exzs6 exzs5 exzs4 exzs3 exzs2 exzs1 exzs0 ds3 pmon exzs count (lsb)
register memory map 14 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 19 h r exzs15 exzs14 exzs13 exzs12 exzs11 exzs10 exzs9 exzs8 ds3 pmon exzs count (msb) 1a h r perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 ds3 pmon perr count (lsb) 1b h r - - perr13 perr12 perr11 perr10 perr9 perr8 ds3 pmon perr count (msb) 1c h r cperr7 cperr6 cperr5 cperr4 cperr3 cperr2 cperr1 cperr0 ds3 pmon cperr count (lsb) 1d h r - - cperr13 cperr12 cperr11 cperr10 cperr9 cperr8 ds3 pmon cperr count (msb) 1e h r febe7 febe6 febe5 febe4 febe3 febe2 febe1 febe0 ds3 pmon febe count (lsb) 1f h r - - febe13 febe12 febe11 febe10 febe9 febe8 ds3 pmon febe count (msb) 20 h r/w - - - eom inte abt crc en xfdl tsb configuration 21 h r/w - - - - - - int udr xfdl tsb interrupt status 22 h r/w td7 td6 td5 td4 td3 td2 td1 td0 xfdl tsb transmit data 23 h ----------reserved 24 h r/w - - - - - - tr en rfdl tsb configuration 25 h r/w - - - - - intc1 intc0 int rfdl interrupt control/status 26 h r fe ovr flg eom crc nvb2 nvb1 nvb0 rfdl tsb status 27 h r rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 rfdl tsb receive data 28 h r/w - - - - lbcod1 lbcode0 cbe inte mx23 configuration 29 h r/w - dais7 dais6 dais5 dais4 dais3 dais2 dais1 mx23 demux ais insert 2a h r/w - mais7 mais6 mais5 mais4 mais3 mais2 mais1 mx23 mux ais insert 2b h r/w - lba7 lba6 lba5 lba4 lba3 lba2 lba1 mx23 loopback activate 2c h r/w 0 ilbe7 ilbe6 ilbe5 ilbe4 ilbe3 ilbe23 ilbe1 mx23 loopback request insert 2d h r - lbrd7 lbrd6 lbrd5 lbrd4 lb rd3 lbrd2 lbrd1 mx23 loopback request detect 2e h r - lbri7 lbri6 lbri5 lbri4 lbri3 lbri2 lbri1 mx23 loopback request interrupt 2f h - 30 h ---------reserved 31 h r/w - - bc5 bc4 bc3 bc2 bc1 bc0 feac xboc code table 2 ? register memory map reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name
register memory map 15 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 32 h r/w - - - - - idle avc boce feac rboc configuration/ interrupt enable 33 h r idlei boci boc5 boc4 bo c3 boc2 boc1 boc0 feac rboc interrupt status 34 h r/w aispat fdet mbdis m3o8 uni refr aisc cbe ds3 frmr configuration 35 h ace=0 ace=1 r/w cofae - rede - cbite aisones ferfe bpvo idle exzso aise extype oofe salgo lose algotype ds3 frmr interrupt enable/additional configuration 36 h r cofai redi cbiti ferfi idli aisi oofi losi ds3 frmr interrupt status 37 h r/w ace redv cbitv ferfv idlv aisv oofv losv ds3 frmr status 38 h - 3f h ---------reserved 40 h r/w g747 - word m2o5 mdbis ref - - ds2 #1 frmr perr configuration 41 h r/w cofae - rede ferfe rese aise oofe - ds2 #1 frmr perr interrupt enable 42 h r cofai - redi ferfi resi aisi oofi - ds2 #1 frmr perr interrupt status 43 h r - - redv ferfv resv aisv oofv - ds2 #1 frmr perr status 44 h r/w - - - - - inte intr ovr ds2 #1 frmr monitor interrupt enable/status 45 h r ferr7 ferr6 ferr5 ferr4 ferr3 ferr2 ferr1 ferr0 ds2 #1 frmr ferr count 46 h r perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 ds2 #1 frmr perr count (lsb) 47 h r - - - perr12 perr11 perr10 perr9 perr8 ds2 #1 frmr perr count (msb) 48 h r/w g747 pinv minv finv zais xferf xres inte ds2 #1 mx12 configuration and control 49 h r/w - - - - - - lbcode1 lbcode0 ds2 #1 mx12 loopback code select 4a h r/w mais4 mais3 mais2 mais1 dais4 dais3 dais2 dais1 ds2 #1 mx12 ais insert 4b h r/w ilbr4 ilbr3 ilbr2 ilbr1 lba4 lba3 lba2 lba1 ds2 #1 mx12 loopback active 4c h r lbri4 lbri3 lbri2 lbri1 lbrd4 lbrd3 lbrd2 lbrd1 ds2 #1 mx12 loopback interrupt table 2 ? register memory map reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name
register memory map 16 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice note: all reserved registers should not be read/written 4d h r/w txesel4 txesel3 txesel2 txesel1 rxesel4 rxesel3 rxeles2 rxesel2 ds1 #1 transmit and receive edge select 50 h - 57 h r/w ds2 #4 mx12 registers 58 h - 5d h r/w ds2 #2 mx12 registers 60 h - 67 h r/w ds2 #3 frmr registers 68 h - 6d h r/w ds2 #3 mx12 registers 70 h - 77 h r/w ds2 #4 frmr registers 78 h - 7d h r/w ds2 #4 mx12 registers 80 h - 87 h r/w ds2 #5 frmr registers 88 h - 8d h r/w ds2 #5 mx12 registers 90 h - 97 h r/w ds2 #6 frmr registers 98 h - 9d h r/w ds2 #6 mx12 registers a0 h a1 h a2 h a3 h a4 h a5 h a6 h a7 h r/w g747 cofae cofai - - ferr7 perr7 - - cofae - - - ferr6 perr6 - word rede redi redv - ferr5 perr5 - m2o5 ferfe ferfi ferfv - ferr4 perr4 perr12 mdbis rese resi resv - ferr3 perr3 perr11 ref aise aisi aisv inte ferr2 perr2 perr10 - oofe offi oofv intr ferr1 perr1 perr9 - - - - ovr ferr0 perr0 perr8 ds2 #7 frmr registers a8 h a9 h aa h ab h ac h ad h r/w g747 - mais4 ilbr4 lbr4 txesel4 pinv - mais3 ilbr3 lbr3 txesel3 minv - mais2 ilbr2 lbr2 txesel2 finv - mais1 ilbr1 lbr1 txesel1 xais - dais4 lba4 lbdr4 rxesel4 xferf - dais3 lba3 lbdr3 rxesel3 xref lbcode1 dais2 lba2 lbdr2 rxesel2 inte lbcode0 dais1 lba1 lbdr1 rxesel1 ds2 #7 mx12 registers ae h - ff h ---------reserved 100 h - 1ff h ---------reserved table 2 ? register memory map reg r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name
register description 17 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice register descriptions master reset/clock status read/write addresses: 00 h reset value: 00 h bit name description 7 ds3rcact (ds3 receive clock activity) the ds3 receive clock activity (ds3rcact) bit indicates at least one low to high transaction has occurred on the rclk input since the last read of this register. the ds3rcact bit is set to a logic 1 by a rising edge on the rclk input and is cleared to a logic 0 by a read of this register. 6 ds3tcact (ds3 transmit clock activity) the ds3 transmit clock activity (ds3tcact) bit indicates at least one low to high transaction has occurred on the td2clk input since the last read of this register. the ds3tcact bit is set to a logic 1 by a rising edge on the ticlk input and is cleared t o a logic 0 by a read of this register. 5 ds2tcact (ds2 transmit clock activity) the ds2 transmit clock activity (ds2tcact) bit indicates at least one low to high transaction has occurred on the ticlk input since the last read of this register. the ds2tcact bit is set to a logic 1 by a rising edge on the td2clk input and is cleared to a logic 0 by a read of this register. note that if the td2clk signal is absent for a period of time (i.e., td2clk clock failure), the d3mx must be reset once the td2clk signal is restored. 4-1 unused must be zero for normal operation. 0 reset (software reset) the reset bit implements a software reset. if the reset bit is a logic1, the entire d3mx is held in reset. this bit is not self -clearing; therefore, a logic 0 must be written to br ing the d3mx out of reset. holding the d3mx in a reset clears the reset bit, thus deasserting the software reset. revision/global pmon update read/write addresses: 01 h reset value: 00 h bit name description 7-0 id 7-0 (identification bits) the version identification bits id 7-0, are set to a fixed value representing the version number of the d3mx. these bits can be read by software to determine the version number. writing to this register causes all performance monitor counters (ds3 and ds2/g.747) to be updated simultaneously. 76543210 0 ds3tcact ds2tcact 0 0 0 0 reset 7 ds3rcact 76543210 0 id6 id5 id4 id3 id2 id1 id0 7 id7
register description 18 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master bypass configuration read/write addresses: 02 h reset value: 00 h bit name description 7 exd2clk (external ds2 clk) the exd2clk bit selects between an internally generated ds2 clock and the clock input on the td2clk pin. if exd2clk is a logic 0, the ds2 clock for the multiplexing side becomes the generated clock derived from the ds3 transmit ticlk clock. the generated ds2 clock is nominally 6.306272 mhz while in c-bit parity mode and while in m23 mode, it is nominally 6.311993 mhz. if exd2clk is a logic 1, the transmit ds2 clock becomes td2clk. 6-0 byp 7-1 (m12 bypass) the byp 7-1bits allow for each of the seven mx12blocks to be indi vidually bypassed so that the external ds2 may be multiplexed and duplexed directly without the intermediate m12 multiplexing. if byp[n] is a logic 1, the following applies: 1. a nominally 6.312 mhz clock is expected on td1clk(4n). 2. a data stream synchronous to td1clk(4n) is expected on td1dat(4n). 3. the clocks on td1clk(4n-1), td1clk(4n-2) and td 1clk(4n-3) have no effect and should be tied to ground. 4. the data streams in td1dat(4n-1), td1clk(4n-2) and td1clk(4n-3) are ignored and should be tied to ground. 5. a nominally 6.312 mhz clock is presented on rd1clk(4n). 6. a data stream synchronous to rd1clk(4n) is presented on rd1dat(4n). 7. the signals on rd1clk(4n-1), rd1clk(4n-2),r d1clk(4n-3), rd1dat(4n-1), rd1dat(4n-2) and rd1dat(4n-3) are always low. 76543210 0 byp7 byp6 byp5 byp4 byp3 byp2 byp1 7 exd2clk
register description 19 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master hdlc configuration read/write addresses: 03 h reset value: 40 h bit name description 7 rexhdlc (receive external hdlc) the state of the receive external hdlc (rexhdlc) bit determines weather the c-bit parity path maintenance data link is terminat ed by the internal hdlc receiver or by an external hdlc receiver. when the rexhdlc bit is a logic 0, the internal hdlc receiver is selected; the rdlclk/rdlint pin is configured to output the interrupt signal (rdlint) from the internal hdlc receiver and the rdlsig/rdleom pin is configured to output the end-of-message signal (rdleom) from the internal hdlc receiver. when the rexhdlc bit is a logic 1, the use of an external hdlc receiver is selected; the rdlsig/rdleom pin is configured to output the data stream (rdlsig) and the rdlclk/rdlint pin is configured to output the data link clock signal (rdlclk). the rexhdlc bit is cleared to logic 0 upon reset. 6 texhdlc (transmit external hdlc) the state of the transmit external hdlc (texhdlc) bit determines weather the c-bit parity path maintenance data link is sourced by the internal hdlc transmitter or by an external hdlc transmitter. when the texhdlc bit is a logic 0, the internal hdlc transmit ter is selected; the tdlclk/tdlint pin is configured as an output to present the interrupt signal (tdlint) from the internal hdlc t rans- mitter and the tdlsig/tdludr pin is configured to output the underrun signal (tdludr) from the internal hdlc transmitter. when the texhdlc bit is a logic 1, the use of an external hdlc transmitter is selected; the tdlsig/tdludr pin is configured to output the data link data stream (tdlsig) and the tdlclk/tdlint pin is configured to output the data link clock signal (tdlclk) . the texhdlc bit is set to logic 1 upon reset. 5-4 unused must be zero for normal operation. 3reompol (receive end-of-mes- sage polarity) the receive end-of-message polarity (reompol) bit determines the assertion level of the rdleom output. if reompol is a logic 0, the rdleom output is an active low open-drain output. if reompol is a logic 1, the rdleom output is asserted high and always has a strong drive. if the rexhdlc bit is a logic 1, this bit has no effect. 2 tudrpol (transmit underflow polarity) the transmit underflow polarity (tudrpol) bit determines the assertion level of the tdludr output. if tudrpol is a logic 0, the tdludr output is an active low open-drain output. if tudrpol is a logic 1, the tdludr output is asserted high and always has a strong drive. if the texhdlc bit is a logic 1, this bit has no effect. 1rintpol (receive interrupt polarity) the receive interrupt polarity (rintpol) bit determines the assertion level of the rdlint output. if rintpol is a logic 0, the rdlint output is an active low open-drain output. if rintpol is a logic 1, the rdlint output is asserted high and always has a strong drive. if the rexhdlc bit is a logic 1, this bit has no effect. 0tintpol (transmit interrupt polarity) the transmit interrupt polarity (tintpol) bit determines the assertion level of the tdlint output. if tintpol is a logic 0, the tdlint output is an active low open-drain output. if tintpol is a logic 1, the tdlint output is asserted high and always has a strong drive. if the texhdlc bit is a logic 1, this bit has no effect. 76543210 0 texhdlc 0 0 reompol tudrpol rintpol tintpol 7 rexhdlc
register description 20 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master loopback configuration read/write addresses: 04 h reset value: 00 h bit name description 7-4 unused must be zero for normal operation. 3-2 lineais 1-2 (line alarm indica- tion signal) the line ais (lineais 1-0) bits allow the generation of various ais patterns on the tdat output when tuni is set to logic 1, or on the tpos and tneg outputs when tuni is set to logic0, independent of the data stream being transmitted. the lineais 1-0 option is expected to be used when the diagnostic loopback is invoked, ensuring that only a valid ds3 stream enters the network. the lin- eais 1-0 bits select one of the following ais patterns for transmission: the lineais 1-0=01 option is compatible with tr-tsy000009 section 3.7 objectives.if the intention is to loopback the ais, the a is bit in the ds3 tran configuration register should be written instead. 1 llbe (diagnostic loopback enable) the diagnostic loopback enable (llbe) bit allows the looping back of the received ds3 into the transmitted ds3 path. if the llb e bit is a logic 1, the rpos, rneg, and rclk signals are connected in ternally to replace the signals normally output on the tpos, tneg, and tclk pins. 0dlbe (diagnostic loop- back enable) the diagnostic loopback enable (dlbe) bit allows the looping back of the transmitted ds3 into the receive ds3 path for diagnost ic purposes. if the dlbe bit is a logic 1, the tpos, tneg, and tclk signals are connected internally to replace the signals normal ly input on the rpos, rneg, and rclk pins. 76543210 0 0 0 0 lineais1 lineais2 llbe dlbe 7 0 lineais 1-0 ais transmitted 00 none 01 framed, repetitive 1010... pattern with c-bits forced to logic 0 10 framed, repetitive 1111... pattern with c-bits forced to logic 0 11 unframed, all-ones pattern
register description 21 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master interface configuration read/write addresses: 05 h reset value: 00 h bit name description 7-5 unused must be zero for normal operation. 4tinv (ds3 transmit edge invert) the transmit invert (tinv) bit enables data inversion of the ds3 transmit interface. when tinv is a logic 1, the tpos and tneg signals are active low. when tinv is a logic 0, the tpos and tneg signals are active high. inversion only takes place when the ds3 transmit interface is configured for dual rail operation. 3trise (ds3 transmit edge falling) the transmit falling edge select (trise) bit configures the updating edge used on the ds3 transmit interface. when trise is a l ogic 1, the ds3 transmit interface is updated on the rising edge of tclk. when trise is a logic 0, the ds3 transmit interface is upd ated on the falling edge of tclk. 2tuni (ds3transmit unipolar) the transmit unipolar (tuni) bit configures the ds3 transmit interface for unipolar or dual rail operation. when tuni is a logi c 1, the ds3 transmit interface is configured as tdat and tmfp. when tuni is a logic 0, the ds3 transmit interface is configured as tpos and tneg. 1rinv (ds3 receive edge invert) the receive invert (rinv) bit enables data inversion of the ds3 receive interface. when rinv is a logic 1, the rpos and rneg signals are active low. when rinv is a logic 0, the rpos and rneg signals are active high. inversion only takes place when the ds3 receive interface is configured for dual rail operation. 0rfall (ds3 receive edge falling) the receive falling edge select (rfall) bit configures the sampling edge used on the ds3 receive interface. when rfall is a log ic 1, the ds3 receive interface is sampled on the falling edge of rclk. when rfall is a logic 0, the ds3 receive interface is samp led on the rising edge of rclk. 76543210 0 0 0 tinv trise tuni rinv rfall 7 0
register description 22 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master alarm enable/network requirement bit read/write addresses: 06 h reset value: 80 h bit name description 7tnr (transmit network requirement) the transmit network requirement (tnr) bit determines the value inserted into the network requirement (n r ) bit transmitted in the second c-bit in m-subframe 1 when in ds3 c-bit parity mode. a logic 1 in the tnr bit causes a one to be transmitted in the n r overhead bit timeslot. the tnr bit is set to a logic 1 upon either a hardware or software reset. if c-bit parity is not selecte d, the tnr bit has no effect. note that the serial control input, tohen, takes precedence over the effect of this bit when tohen is assert ed during the network requirement bit position. while tohen is asserted at the second c-bit position of m-subframe 1, the data on the toh input is transmitted in the n r , bit. 6 rnr (receive network requirement) the receive network requirement (rnr) bit reflects the real time value of the network requirement (n r ) bit presented in the second c-bit in m-subframe 1 when in ds3 c-bit parity mode. the rnr bit is a logic 1 if a logic one occurs in the n r overhead bit timeslot. if c-bit parity is not selected, the value of rnr is meaningless and random. 5 altfebe (alternate far end block error) the alternate far end block error (altfebe) bit selects the erro r conditions detected to define a febe indication. if altfebe i s a logic 1, a febe indication is generated in the outgoing c-bit parity ds3 transmit stream if a c-bit parity error occurred in th e last received m-frame. if no c-bit parity error occurred, no febe is ge nerated. if altfebe is a logic 0, a febe indication is ge nerated if either one or more framing bit errors or a c-bit parity error has occurred in the last received m-frame. if no framing bit e rrors nor c-bit parity errors have occurred, then no febe is generated. 4redo (red ds2 alarm out- put enable) the red ds2 alarm output enable (redo) bit selects the type of signal output on the roof/rred pin. if redo is a logic 1, ds3 red status signal is available on the roof/rred output pin. if redo is a logic o, ds3 oof status signal is available on the roof/rred output pin. 3red2alme (red ds2 alarm enable) the red ds2 alarm enable (red2alme) bit works in conjunction with the ds2alme and enables detection of ds2 red condition to be used in place of ds2/g.747 out-of-frame in the above criteria for demultiplexed ais generation. when ds2alme is set to lo gic 1 and red2alme is set to logic 1, the occurrence of oof for 53 consecutive ds2/g.747 ?m-frames? causes a ds2 red alarm condition and generates the ds1 ais. when ds2alme is set to logic 1 and red2alme is set to 0, any occurrence of oof generates the ds1 ais. if ds3alme is a logic 0, the red3alme bit is ignored. 2 ds2alme (ds2 alarm enable) the ds2 alarm enable (ds2alme) bit allows the automatic generation of ais in the ds1s demultiplexed from a ds2 or g.747 stream which is in an alarm condition. if ds2alme is a logic 1, a ds2 or g.747 out-of-frame (oof) condition (i.e. immediately a fter 2-of-n f-bit errors where n is 4 or 5, or 3-of-4 m-frames containing m-bit errors for ds2, or immediately after 4 consecutive f raming word errors for g.747) or detection of ds2 or g.747 ais causes each of the associated ds1s to be replaced by an unframed all on es pattern immediately. if ds2alme is a logic 0, ais can still be generated in the demultiplexed ds1s under software control by se tting the bits in the appropriate mx12 ais insert register. note that the removal of the auto all-ones insertion is performed upon th e first ds2 m-frame or g.747 frame pulse after the ds2 frmr has found frame alignment. 1red3alme (red ds3 alarm enable) the red ds3 alarm enable (red3alme) bit works in conjunction with the ds3alme and enables detection of ds3 red alarm condition to be used in place of ds3 loss if signal and ds3 out-of-frame in the above criteria for demultiplexed ais generation . when ds3alme is set to logic 1 and red3alme is set to logic 1, the occurrence of los or oof for 127 consecutive m-frames (or 21 consecutive m-frames, if fdet is set to logic 1 in the ds3 frmr configuration register) causes a ds3 red alarm condition and generates the ds2 ais. when ds3alme is set to logic 1 and red3alme is set to 0, any occurrence of los or oof generates the ds2 ais. if ds3alme is a logic 0, the red3alme bit is ignored. 0 ds3alme (ds3 alarm enable) the ds3 alarm enable (ds3alme) bit allows the automatic generation of ais in all of the demultiplexed ds2s upon a ds3 alarm condition. if ds3alme is a logic 1, a ds3 loss of signal (>175 zeros), a ds3 out-of-frame (oof) condition (i.e. immediately aft er 3-of-n f-bit errors where n is 8 or 16, or 3-of-4 m-frames containing m-bit errors). ds3 idle code detection or ds3 ais detecti on causes all of the ds2s to be replaced by an unframed all ones pattern immediately. generation of ais continues while the detect ed alarm condition persists. if ds3alme is a logic 0, ais can still be generated in the demultiplexed ds2s under software control by setting the bits in the mx23 demux ais insert register. 76543210 0 rnr altfebe redo red2alme ds2alme red3alme ds3alme 7 tnr
register description 23 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master test read/write addresses: 07 h reset value: 00 h bit name description 7-4 unused must be zero for normal operation. 3dbctrl (data bus control) the dbctrl bit is used to pass control of the data bus to the cs pin. while the dbctrl is set, holding the cs pin high causes the d2mx to drive the data bus and holding the cs pin low tri-states the data bus. the dbctrl bit overrides the hizdata bit. the dbc- trl bit is used to measure the drive capability of the data bus driver pads. 2 unused must be zero for normal operation. 1- 0 hizdata, hizio (hi-z data) (hi-z i/o) the hizdata and hizio bits control the tri-state modes of the d3mx. while the hizio bit is a logic 1, all output pins of the d3 mx. while the hizio bit is a logic 1, all output pins of the d3mx except the data bus are held in a high-impedance state. the microproces sor inter- face is sill active. while the hizdata bit is a logic 1, the data bus is also held in a high-impedance state which inhibits mic roprocessor read cycles. 6543210 0 0 0dbctrl0hizdatahizio 0 7
register description 24 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master interrupt source #1 read/write addresses: 08 h reset value: 00 h bit name description 7reg2 (red alarm 2) if reg2 bit is a logic 1, at least one bit in the master interrupt source #2 register is set, that is, at least one ds2 farmer or the xfdl is generating an interrupt. 6reg3 (red alarm 3) if reg3 bit is a logic 1, at least one bit in the master interrupt source #3 register is set, that is, at least one m12 multipl exer is gen- erating an interrupt. 5xfdlint (transmit facility data link interrupt) if xfdlint bit is a logic 1, the xdfl tsb is generating an interrupt (also visible on the tdlint output when configured for int ernal hdlc, i.e. texhdlc=0) 4mx23 (mx23 tx interrupt) if mx23 bit is a logic 1, the mx23 frmr tsb is generating an interrupt due to the detection of a ds2 loopback request. 3ds3frmr (d3 framer interrupt) if ds3frmr bit is a logic 1, the ds3 frmr tsb is generating an interrupt. register 36h should be read to determine which event in ds3 frmr has caused to interrupt. 2rfdlint (receive facility data link interrupt) if rfdlint bit is a logic 1, the rfdl tsb is generating an inte rrupt (also visible on the rfdlint output when configured for in ternal hdlc, i.e. rexhdlc=0). 1rfdleom (receive facility data link end of message interrupt) if rfdleom bit is a logic 1, the rfdl tsb is generating an interrupt due to an end of message occurrence (also visible on the rdleom output when configured for internal hdlc, i.e. rexhdlc=0). 0rboc (receive bit oriented code interrupt) if rboc bit is a logic 1, the feac rboc tsb is generating an interrupt. register 33h should be read to determine which event in rboc has caused to interrupt. 76543210 0 reg3 xfdlint mx23 ds3frmr rfdlint rfdleom rboc 7 reg2
register description 25 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice master interrupt source #2 read/write addresses: 09 h reset value: 00 h bit name description 7 xfdludr (transmit facility data link underrun interrupt) this bit allows software to determine whether the xfdl tsb produced an underrun condition. if the xfdludr bit is a logic 1, the xfdl tsb is generating an interrupt due to an underrun of the transmit data buffer (also v isible on the tdludr output when configured for internal hdc, i.e. texhdlc=0). reading this register does not remove the interrupt indication; the corresponding tsb?s interrupt status register must be read to remove the interrupt indication. 6-0 ds2frmr 7-1 (ds2 framer interrupt) these bits allow software to determine which of the seven ds2 framer tsbs produced the interrupt on the intb output pin. reading this register does not remove the interrupt indication; the corresponding tsb?s interrupt status register must be read to remove the interrupt indication. master interrupt source #3 read/write addresses: 0a h reset value: 00 h bit name description 7 ds3pmon (ds3 performance monitor interrupt) ds3 pmon tsb produced the interrupt on the intb output pin. 6-0 m12 7-1 (m12 performance monitor interrupt) these bits correspond to which m12 tsb produced an interrupt. reading this register does not remove the interrupt indication; t he corresponding tsb?s interrupt status register must be read to remove the interrupt indication. 76543210 0 ds2frmr 7 ds2frmr 6 ds2frmr 5 ds2frmr 4 ds2frmr 3 ds2frmr 2 ds2frmr 1 7 xfdludr 76543210 0 mx12 7 mx12 6 mx12 5 mx12 4 mx12 3 mx12 2 mx12 1 7 ds3pmon
register description 26 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 transmit configuration read/write addresses: 0c h reset value: 00 h bit name description 7cbtran (ds3 c-bit transmit configuration) the cbtran bit controls the c-bits during ais transmission. when cbtran is a logic 0, the c-bits are overwritten with zeros dur - ing ais transmission (as is currently specified in ansi t1.107a section 8.1.3.1). the only exception is the network requirement bit, which is forced to the tnr register value. when cbtran is a logic 1 and the m23 application is enabled the c-bits pass through transparently during ais transmission. when cbtran is a logic 1, and the c-bit parity application is enabled, the c-bits are ov er- written with the appropriate c-bit parity functions during ais transmission. 6ais (ds3alarm indication signal configuration) the ais bit enables transmission of the alarm indication signal. when ais is a logic 1, the transmit ds3 payload (on the tdat/ tpos and tneg outputs) is overwritten with the pattern 1010... 5idl (ds3 idle pattern configuration) the idl bit enables transmission of the alarm indication signal and the idle signal. when idl is a logic 1, the transmit ds3 pa yload is overwritten with the pattern 1100... 4ferf (ds3 far end receive failure configuration) the ferf bit enables transmission of far end receive failure in the outgoing ds3 stream. when ferf is a logic 1, the x1 and x2 overhead bit positions in the ds3 stream are set to logic 0. when ferf is a logic 0, the x1 and x2 overhead bit positions in th e ds3 stream are set to logic 1. 3 sbow (ds3 stuff bit opportunity window configuration) the sbow bit selects weather to insert the bit from the toh input into the stuff opportunity bit or into the f4 bit. when sbow is a logic 1, the bit from the toh input is inserted into the stuff opportunity bit. when sbow is a logic 0, the bit from the toh in put is inserted into the f4 bit. 2-1 unused must be zero for normal operation. 0cbit (ds3 c-bit parity configuration) the cbit bit enables the c-bit parity application. when cbit is a logic 1, c-bit parity is enabled, and the associated function s are inserted in the c-bit positions of the incoming ds3 stream. when cbit is a logic 0, the m23 application is selected, and the c- bits are passed transparently through the ds3 tran. 76543210 0 ais idl ferf sbow 0 0 cbit 7 cbtran
register description 27 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 transmit diagnostic read/write addresses: 0d h reset value: 00 h bit name description 7dlos (ds3 loss of signal) the dlos controls the insertion of loss of signal in the outgoing ds3 stream. when dlos is set to a logic 1, the data on output s tpos, tneg, and tdat are forced to continuous zeros. 6dlcv (ds3 line code viola- tion) the dlcv controls the insertion of a single line code violation in the outgoing ds3 stream. when dlcv is set to a logic 1, a li ne code violation is inserted by generating an incorrect polarity of violation in the next b3zs signature. the data being transmit ted must therefore contain periods of three consecutive zeros in order for the line code violation to be inserted. for example line code violations may not be inserted when transmitting ais, but will be inserted when transmitting the idle signal. this bit is autom atically cleared upon insertion of the line code violation. 5 unused must be zero for normal operation. 4dferr (ds3 f-bit errors) the dferr controls the insertion of framing errors (f-bit errors) in the outgoing ds3 stream. when dferr is set to a logic 1, a nd the f-bits are inverted before insertion in the ds3 stream. 3dmerr (ds3 m-bit errors) the dmerr controls the insertion of framing errors (m-bit errors) in the outgoing ds3 stream. when dmerr is set to a logic 1, a nd the m-bits are inverted before insertion in the ds3 stream. 2 dcperr (ds3 c-bit parity errors) the dcperr controls the insertion of c-bit parity errors in the outgoing ds3 stream. when dcperr is set to a logic 1, and the c - bit parity application is enabled, the three c-bits in m-subframe 3 are inverted before insertion in the ds3 stream. 1 dperr (ds3 p-bit errors) the dperr controls the insertion of parity errors (p-bit errors) in the outgoing ds3 stream. when dperr is set to a logic 1, an d the p-bits are inverted before insertion in the ds3 stream. 0dfebe (ds3 far end block errors) the dfebe controls the insertion of far end block errors in th e outgoing ds3 stream. when dfebe is set to a logic 1, and the c- bit parity application is enabled, the three c-bits in m-subframe 4 are set to a logic 0. 76543210 0 dlcv 0 dferr dmerr dcperr dperr dfebe 7 dlos
register description 28 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 pmon interrupt enable/status read/write addresses: 11 h reset value: 00 h bit name description 7-3 unused must be zero for normal operation. 2inte (ds3 performance monitor interrupt enable) a logic 1 in the inte bit position enables the ds3 pmon to generate a microprocessor interrupt and assert the intb output when the counter values are transferred to the holding registers. a logic 0 in the inte bit position disables the ds3 pmon from gene rat- ing an interrupt. when the tsb is reset, the inte bit is set to logic 0, disabling the interrupt. the interrupt is cleared when this reg- ister is read. 1intr (ds3 interrupt) the interrupt (intr) bit indicates the current status of the internal interrupt signal. a logic 1 in this bit position indicate s that a trans- fer of counter values to the holding registers has occurred; a logic 0 indicates that no transfer has occurred. the intr bit is set to logic 0 when this register is read. the value of the intr bit is not affected by the value of the inte b it. 0ovr (ds3 overrun) the overrun (ovr) bit indicates the overrun status of the holding registers. a logic 1 in this bit position indicates that a pr evious interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have been overwritten. a logic 0 indicates that no overrun has occurred. this bit is reset to logic 0 when this register is read. ds3 lcv count lsb read/write addresses: 14 h reset value: 00 h bit name description 7-0 lcv 7-0 (ds3 line code violation) these bits indicate the number of ds3 line code violation (lcv) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either lcv count register. 76543210 00000inteintrovr 7 0 76543210 0 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 7 lcv7
register description 29 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 lcv count msb read/write addresses: 15 h reset value: 00 h bit name description 7-0 lcv 15-8 (ds3 line code violation) these bits indicate the number of ds3 line code violation (lcv) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either lcv count register . ds3 ferr count lsb read/write addresses: 16 h reset value: 00 h bit name description 7-0 ferr 7-0 (ds3 far end receive error) these bits indicate the number of ds3 framing error (ferr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either ferr count registe r. ds3 ferr count msb read/write addresses: 17 h reset value: 00 h bit name description 7-2 unused must be zero for normal operation. 1-0 ferr 9-8 (ds3 far end receive error) these bits indicate the number of ds3 framing error (ferr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either ferr count registe r. 76543210 0 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 7 lcv15 76543210 0 ferr6 ferr5 ferr4 ferr3 ferr2 ferr1 ferr0 7 ferr7 76543210 000000ferr9ferr8 7 0
register description 30 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 exzs count lsb read/write addresses: 18 h reset value: 00 h bit name description 7-0 exzs 7-0 (ds3 excessive zero suppression) these registers indicate the number of summed excessive zeros (exzs) that occurred during the previous accumulation interval. one or more excessive zeros occurrences within an 85 bit block is counted as one summed excessive zero. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either ferr count registe r. ds3 exzs count msb read/write addresses: 19 h reset value: 00 h bit name description 7-0 exzs 7-0 (ds3 excessive zero suppression) these registers indicate the number of summed excessive zeros (exzs) that occurred during the previous accumulation interval. one or more excessive zeros occurrences within an 85 bit block is counted as one summed excessive zero. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either ferr count registe r. ds3 perr count lsb read/write addresses: 1a h reset value: 00 h bit name description 7-0 perr 7-0 (ds3 parity error) these bits indicate the number of p-bit parity error (perr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either exzs count registe r or writing to the global pmon update register 0x01. 76543210 0 exzs6 exzs5 exzs4 exzs3 exzs2 exzs1 exzs0 7 exzs7 76543210 0 exzs14 exzs13 exzs12 exzs11 exzs10 exzs9 exzs8 7 exzs15 76543210 0 perr6 perr5 perr4 perr3 perr2 perr1 perr0 7 perr7
register description 31 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 perr count msb read/write addresses: 1b h reset value: 00 h bit name description 7-0 perr 13-8 (ds3 parity error) these bits indicate the number of p-bit parity error (perr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either exzs count registe r. ds3 cperr count lsb read/write addresses: 1c h reset value: 00 h bit name description 7-0 cperr 7-0 (ds3 c-bit parity error) these bits indicate the number of c-bit parity error (cperr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either cperr count regist er. ds3 cperr count msb read/write addresses: 1d h reset value: 00 h bit name description 7-6 unused must be zero for normal operation. 5-0 cperr 13-8 (ds3 c-bit parity error) these bits indicate the number of c-bit parity error (cperr) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either cperr count regist er. 76543210 0 0 perr13 perr12 perr11 perr10 perr9 perr8 7 0 76543210 0 cperr6 cperr5 cperr4 cperr3 cperr2 cperr1 cperr0 7 cperr7 76543210 0 0 cperr13 cperr12 cperr11 cperr10 cperr9 cperr8 7 0
register description 32 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 febe count lsb read/write addresses: 1e h reset value: 00 h bit name description 7-0 febe 7-0 (ds3 far end bit error) these bits indicate the number of far en d block error (febe) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either febe count registe r. ds3 febe count msb read/write addresses: 1f h reset value: 00 h bit name description 7-0 febe 13-8 (ds3 far end bit error) these bits indicate the number of far en d block error (febe) events that occurred during the previous accumulation interval. a transfer operation of all counter registers within the selected pmon can be triggered by writing to either febe count registe r. 76543210 0 febe6 febe5 febe4 febe3 febe2 febe1 febe0 7 febe7 76543210 0 0 febe13 febe12 febe11 febe10 febe9 febe8 7 0
register description 33 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice xfdl tsb configuration read/write addresses: 20 h reset value: 00 h bit name description 7-5 unused must be zero for normal operation. 4eom (xfdl end of message) the eom bit indicates that the last byte of data written in the transmit data register is the end of the present data packet. i f the crc bit is set then the 16-bit fcs word is appended to the last data byte transmitted and a continuous stream of flags is gener - ated. the eom bit is automatically cleared before transmission of the next data packet begins. the eom register bit value can b e set to logic 1 by pulsing the tdlemoi input pin. 3inte (xfdl interrupt enable) the inte bit enables the generation of an interrupt via the tdlint output. setting the inte bit to logic 1 enables the generati on of an interrupt by asserting the tdlint output; setting inte to logic 0 disables the generation of an interrupt. 2 abt (xfdl abort code) the abort (abt) controls the sending of the 7 consecutive ones hdlc abort code. setting the abt bit to a logic 1 causes the 11111110 code to be transmitted after the last byte from the transmit data register. aborts are continuously sent until this bi t is reset to logic 0. 1crc (xfdl cyclical redundancy check) the crc enable bit controls the generation of the ccitt-crc frame check sequence (fcs). setting the crc bit to logic 1 enables the ccitt-crc generator and the appends the 16 bit fcs to the end of each message. when the crc bit is set to logic 0, the fcs is not appended to the end of the message. the crc type used is the ccitt-crc with generator polynomial = x 16 +x 12 +x 5 +1. the high order bit of the fcs word is transmitted first. 0en (xfdl enable) the enable bit (en) controls the overall operation of the xfdl tsb. when the en bit is set to a logic 1, the xdfl tsb is enable d and flag sequences are sent until data is written into the transmit data register. when the en bit is set to logic 0, the xfdl tbs is disabled. xfdl tsb interrupt status read/write addresses: 21 h reset value: 00 h bit name description 7-2 unused must be zero for normal operation. 1int (xfdl interrupt) the int bit indicates when the xfdl tsb is ready to accept a new data byte for transmission. the int bit is set to a logic 1 wh en the previous byte in the transmit data register has been loaded into the parallel to serial converter and a new byte can be wri tten into the transmit data register. the int bit is set to a logic 0 while new data is in the transmit data register. the int bit i s not dis- abled by the inte bit in the configuration register. 0udr (xfdl underrun) the udr bit indicates when the xfdl tsb has underrun the data in the transmit data register. the udr bit is set to a logic 1 if the parallel to serial conversion of the last byte in the transmit data register has completed before the new byte was written into the transmit data register. once an underrun has occurred, the xfdl transmits an abort, followed by a flag, and waits to trans- mit the next valid data byte. if the udr bit is still set after the transmission of the flag the xfdl will continuously transmi t the all- ones idle pattern. the udr bit can only be cleared by writing a logic 0 to the udr bit position in the register. 76543210 0 0 0 eom inte abt crc en 7 76543210 000000intudr 7 0
register description 34 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice xfdl tsb transmit data read/write addresses: 22 h reset value: 00 h bit name description 7-0 td 7-0 (xfdl transmit data byte) data written to this register is serialized and transmitted on the path maintenance data lint least significant bit first. the xfdl tsb signals when the next data byte is required by asserting the tdlint output (if enabled) and by setting the int bit in the status register high. when int and/or tdlint is set, the transmit data register must be written with the next message byte within 4 data bit periods to prevent the occurrence of an underrun. at a nominal 28.2 kbit/sec link data rate the required writ e interval is 110 sec. rfdl tsb configuration read/write addresses:24 h reset value: 00 h bit name description 7-2 unused must be zero for normal operation. 1tr (rdfl terminate reception) setting the terminate reception bit (tr) forces the rfdl tsb to immediately terminate the reception of the current lapd frame, empty the fifo, clear the interrupts, and begin searching for a new flag sequence. the rfdl handles the tr input in the same manner as if the en bit had been cleared and then set. the tr bit in the configuration register will reset itself afte r a rising and falling edge have occurred on the clk input to the rfdl tsb once the write to this register has completed and web goes inactive. if the configuration register is read after this time, the tr value returned will be zero. the rfdl tsb handles the tr input in the same manner as clearing and setting the en bit, therefore, the rfdl state machine will begin searching for flags and an interrupt will be generated when the first flag is detected. 0en (rfdl enable) the enable bit (en) controls the overall operation of the rfdl tsb. when set, the rdfl tsb is enabled; when reset, the rdfl tsb is disabled. when the tsb is disabled, the fifo and interrupts are all cleared, however, the programming of the interrupt control/status register is not affected. when the tsb is enabled, it will immediately begin looking for flags. 76543210 0 td6 td5 td4 td3 td2 td1 td0 7 td7 76543210 000000tren 7 0
register description 35 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice rfdl tsb interrupt control/status read/write addresses: 25 h reset value: 00 h bit name description 7-3 unused must be zero for normal operation. 2, 1 intc1, intc0 (rdfl interrupt control bits) the intc1 and intc0 bits control when an interrupt is asserted based on the number of received data bytes in the fifo as follow s: 0int (rdfl interrupt status) the int bit reflects the status of the external rdlint interrupt unless the intc1 and intc0 bits are set to disable interrupts, in that case, the rdlint output is forced to 0 and the int bit of the interrupt control/status register will reflect the state of the i nternal inter- rupt latch. 76543210 00000intc1intc0int 7 0 intc1 intc0 description 0 0 disable interrupts (all sources) 0 1 enable interrupt when fifo receives data 1 0 enable interrupt when fifo has 2 bytes of data 1 1 enable interrupt when fifo has 3 bytes of data
register description 36 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice rfdl tsb status read/write addresses:26 h reset value: 00 h bit name description 7fe (rdfl fifo empty) the fifo empty bit (fe) is high when the last fifo entry is read and goes low when the fifo is loaded with new data. 6ovr (rdfl overrun) the receiver overrun bit (ovr) is set when data is written over unread data in the fifo. this bit is not reset until after the status register is read. while ovr is high, the rfdl and fifo are held in the reset state, causing the flg and eom bits in the status reg- ister to be reset also. 5flg (rdfl flag) the flag bit (flg) is set if the rfdl tsb has detected the presence of the lapd flag sequence (01111110) in the data. flg is re set only when the lapd abort sequence (01111111) is detected in the data or when the rfdl tsb is disabled. this bit is passed through the fifo with the data so that the status will correspond to the data just read from the fifo. the reception of bit ori ented codes over the data link will also force an abort due to its eight ones pattern. 4eom (rfdl end of mes- sage) the end of message bit (eom) follows the rdleom output. it is set when: 1. the last byte in the lapd frame (eom) is being read from the receive data register. 2. an abort sequence is detected while not in the receiving all-ones state and the byte, written to the fifo due to the detection of the abort sequence, is being read from the fifo, 3. immediately on detection of fifo overrun. the eom bit is passed through the fifo with the data so that the status will correspond to the data just read from the fifo. 3 crc (rfdl cyclical redundancy check) the crc bit is set if a crc error was detected in the last received lapd frame. the crc bit is only valid when eom is logic 1 a nd flg is a logic 1 and ovr is a logic 0. 2-0 nvb 2-0 (rfdl number of valid bits) the nvb 2-0 bit positions indicate the number of valid bits in the receive data register byte. it is possible that not all of t he bits in the receive data register are valid when the last data byte is read since the data frame can be any number of bits in length and no t nec- essarily an integral number of bytes. the receive data register is filled from the msb to the lsb bit position, with one to eig ht data bits being valid. the number of valid bits is equal to 1 plus the value of nvb 2-0 value of 000 binary indicates that only the msb in the register is valid. nvb 2-0 is only valid when the eom bit is a logic 1 and the flg bit is a logic 1 and the ovr bit is a logic 0. rfdl tsb recive data read/write addresses: 27 h reset value: 00 h bit name description 7-0 rd 7-0 (rfdl receive byte) rd0 corresponds to the first bit of the serial byte received by the rfdl. 76543210 0 ovr flg eom crc nvb2 nvb1 nvb0 7 fe 76543210 0 rd6 rd5 rd4 rd3 rd2 rd1 rd0 7 rd7
register description 37 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx23 configuration read/write addresses: 28 h reset value: 00 h bit name description 7-4 unused must be zero for normal operation. 3-2 lbcode 1-0 (loopback code) the lbcode 1-0 bits select the valid state for a loopback request coded in the c-bits of the ds3 signals. transmit and receive are not independent; the same code is expected in the receive ds3 as is inserted in the transmitted ds3. the following table gives the corre- spondence between lbcode 1-0 bits and the valid codes: if ldcode 1-0 is ?b00 or ?b11, the loopback code is as per ansi t1.107a section 8.2.1 and tr-tdy-000009 section 3.7. because tr-tsy 000233 section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback command possibilities are also supported the lbcode 1-0 bits become logical 0 upon either a hardware or software reset. 1cbe (c-bit parity enable) when set high, the cbe bit enables c-bit parity operation. when cbe is low, m23 operation is enabled. while in c-bit parity mod e, loopback request insertion are disabled. the generated ds2 clock, gd2clk, is nominally 6.3062723 mhz while in c-bit parity mode , received c bits are ignored, and transmitted c bits are set to 1. while in m23 mode, the generated ds2 clock, gd2clk, is nomina lly 6.311993 mhz and c bit decoding and encoding is fully operational. 0inte (m23 interrupt enable) when set high, the inte bit enables the mx23 to activate the interrupt output, intb, whenever any of the lbri 7-1 bits are set high in the mx23 loopback request interrupt register. mx23 interrupts are masked when inte is cleared low. 76543210 0 0 0 0 lbcode1 lbcode0 cbe inte 7 0 lbcode1:0] loopback code 00 c1 = c2 and c1 = c3 01 c1 = c3 and c1 = c2 10 c2 = c3 and c1 = c2 11 c1 = c2 and c1 = c3
register description 38 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice demux ais insert register mx23 mux ais insert register read/write addresses: 2a h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 dais 7-1 (demux alarm indication signal) setting any of the dais7-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding ds2 stream demul- tiplexed from the ds3 signal input on rdat. demux ais insertion takes place after the point where per ds2 loopback may be invoked using the loopback activate register thus allowing demux ais to be inserted into the through path while a ds2 loopback is activated, if desired. read/write addresses: 2a h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 mais 7-1 (multiplexed alarm indication signal) setting any of the mais 7-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding ds2 strea m multiplexed into the ds3 signal output on tdat. mux ais insertion takes place before the point where per ds2 loopback may be invoked using the loopback activate register and thus mux ais cannot be inserted while a ds2 loopback is activated. 76543210 0 dais7 dais6 dais5 dais4 dais3 dais2 dais1 7 0 76543210 0 mais7 mais6 mais5 mais4 mais3 mais2 mais1 7 0
register description 39 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx23 loopback request insert register mx23 loopback activate register read/write addresses: 2b h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 lba 7-1 (ds2 loopback) setting any of the lba 7-1 bits activates loopback of the corresponding ds2 stream from the input ds3 signal to the output ds3 signal. the demultiplexed ds2 signals continue to present valid payloads while loopbacks are activated. the mx23 demux ais insert register allows insertion of ds2 ais if required. read/write addresses: 2c h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 ilbr 7-1 (mx23 insertion loopback request) setting any of the ilbr 7-1 bits enables the insertion of a loopback request in corresponding ds2 stream in the output ds3 sign al. the format of the loopback request is determined by the lbcode 1-0 bits in the mx23 configuration register. 76543210 0 lba7 lba6 lba5 lba4 lba3 lba2 lba1 7 0 76543210 0 ilbr7 ilbr6 ilbr5 ilbr4 ilbr3 ilbr2 ilbr1 7 0
register description 40 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx23 loopback request detect register read/write addresses: 2d h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 lbrd 7-1 (mx23 loopback request detector) the lbrd 7-1 bits are set high while a loopback request is detected for the corresponding ds2 stream in the input ds3 signal. t he lbrd 7-1 bits are set low otherwise. the format of the loopback request expected is determined by the lbcode 1-0 bits in the mx23 configuration register. as per tr-tsy-000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has be absent for five successive m-frames. mx23 loopback request interrupt register read/write addresses: 2e h reset value: 00 h bit name description 7 unused must be zero for normal operation. 6-0 lbri 7-1 (mx23 loopback request interrupt) the lbri 7-1 bits are set high while a loopback request is asserted or deasserted for the corresponding ds2 stream in the input ds3 signal. the lbri 7-1 bits are set high whenever the corresponding lbri 7-1 bits change state. if interrupts are enabled usi ng the inte bit in the configuration register then the interrupt output, intb is activated. the lbri 7-1 bits are to logic 0 immed iately following a read of the register, acknowledging the interrupt and deactivating the intb output. 76543210 0 lbrd7 lbrd6 lbrd5 lbrd4 lbrd3 lbrd2 lbrd1 7 0 76543210 0 lbri7 lbri6 lbri5 lbri4 lbri3 lbri2 lbri1 7 0
register description 41 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice feac xboc tsb code read/write addresses: 31 h reset value: 3f h bit name description 7-6 unused must be zero for normal operation. 5-0 bc 5-0 this register enables the xboc tsb to generate a bit oriented code and selects the 6-bit code to be transmitted. when this register is written with any 6-bit code other than 111111, that code will be transmitted repeatedly in the far-end al arm and control (feac) channel with the format 111111110[bc0][bc1][bc2][bc3][bc4][bc5]0. when the register is written with 111111, the xboc tsb is disabled. rboc configuration/interrupt enable read/write addresses: 32 h reset value: 00 h bit name description 7-3 unused must be zero for normal operation. 2idle (idle) the idle bit position enables or disables the generation of an interrupt when there is a transition from a validated boc to idl e code. a logic 1 in this bit position enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation . 1 avc (alternative validation criterion) the avc bit position selects the validation criterion used in determining a valid boc. a logic 0 selects the 8 out of 10 matchi ng boc criterion; a logic 1 in the avc bit position selects the ?alternative? validation criterion of 4 out of 5 matching bocs. 0boce (bit oriented code enable) the boce bit position enables or disables the generation of an interrupt when a valid boc is detected. a logic 1 in this bit po sition enables generation of an interrupt; a logic 0 in this bit position disables interrupt generation. when the d3mx is reset, boce is reset to logic 0; therefore, interrupt generation is disabled. 76543210 0 0 bc5 bc4 bc3 bc2 bc1 bc0 7 0 76543210 00000idleavcboce 7 0
register description 42 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice rboc interrupt status read/write addresses: 33 h reset value: 00 h bit name description 7idlei (idle interrupt) the idlei bit indicates whether an interrupt was generated by the detection of the transition from a valid boc to idle code. a logic 1 in the idlei bit position indicates that a transition from a valid boc to idle code has generated an interrupt; a logic 0 in the i dlei bit position indicates that no transition from a valid boc to idle code has been detected. idlei is cleared to logic 0 when the reg ister is read. 6boci (bit oriented code interrupt) indicates a logic 1 in the boci bit position indicates that a validated boc code has generated an interrupt; a logic 0 in the boci bit position indicates that no boc has been detected. since the bit-oriented code ?111111? is not recognized by the rboc, the boc 5 -0 bits are set to all ones (?111111?) if no valid code has been detected. the boci bit position is cleared to logic 0 and the int errupt is deasserted when this register is read. 5-0 boc 5-0 (bit oriented code) the bit positions boc 5-0 contain the received bit-oriented codes. a logic 1 in the boci bit position indicates that a validate d boc code has generated an interrupt; a logic 0 in the boci bit position indicates that no boc has been detected. since the bit-orie nted code ?111111? is not recognized by the rboc, the boc 5-0 bits are set to all ones (?111111?) if no valid code has been detected . the boci bit position is cleared to logic 0 and the interrupt is deasserted when this register is read. 76543210 0 boci boc5 boc4 boc3 boc2 boc1 boc0 7 idlei
register description 43 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 frmr configuration read/write addresses: 34 h reset value: 80 h bit name description 7 aispat (ds3 alarm indication pattern) the aispat bit controls the pattern used to detect the alarm indi cation signal (ais). when a logic 1 is written to aispat, the ais detection algorithm checks that a framed ds3 signal containing the repeating pattern 1010...is present. the c-bits are checked for the value specified by the aisc bit setting. when a logi c 0 is written to aispat, the ais det ection algorithm is determined sol ely by the settings of aisc and aisones register bits (see bit mapping table in the additional configuration register description). 6fdet (ds3 fast detection) the fdet bit selects the fast detection timing for ais, idle and red. when fdet is set to logic 1, the ais, idle, and red detec - tion time is 2.23 ms; when fdet is set to logic 0, the detection time is 13.5 ms. 5mbdis (ds3 m-bit error dis- able) the mbdis bit disables the use of m-bit errors as a criteria for losing frame alignment. when mbdis is set to logic 1, m-bit er rors are disabled from causing an oof; the loss of frame criteria is based solely on the number of f-bit errors selected by the m3o8 bit . when mbdis is logic 0, an oof can occur when one or more m-bit errors occur in 3 out of 4 consecutive m-frames, or when the f- bit error ratio selected by the m3o8 bit is exceeded. 4m3o8 (ds3 m-bit 3 out of 8 framing error) the m3o8 bit configures the out of frame decision criteria. if m3o8 is a logic 1, out of frame is declared if at least 3 of 8 f raming bits are in error. if m3o8 is a logic 0, the standard 3 of 16 bits in error criteria is used. 3 uni (ds3 unipolar select) the uni bit is used to configure the frmr to accept either unipolar or bipolar data streams. when a logic 1 is written to uni, the frmr accepts unipolar data and line code violation indication on its inputs. when a logic 0 is written to uni, the frmr accepts bipo- lar data on its inputs and performs b3zs decoding and line code violation reporting. 2refr (ds3 re-framing) the refr bit is used to trigger reframing. if a logic 1 is written to refr when it was previously logic 0, the frmr is forced o ut-of- frame, and a new search for frame alignment is initiated. note that only a low to high transition of the refr bit triggers refr aming; multiple write operations are required to ensure such a transitions 1aisc (ds3 alarm indicationsignal configuration) the aisc bit controls the algorithm used to detect the alarm indication signal (ais). when a logic 1 is written to aisc, the al gorithm checks that a framed ds3 signal with all c-bits set to logic 0 is observed for a period of time before declaring ais. the paylo ad con- tents are checked to the pattern selected by the aispat bit. when a logic 0 is written to aisc, the ais detection algorithm is deter- mined solely by the settings of aispat and aisones register bi ts (see bit mapping table in the additional configuration registe r description). 0cbe (ds3 c-bit parity enable) the cbe bit selects whether the c-bit parity application is enabled. when a logic 1 is written to cbe, c-bit parity mode is ena bled. when a logic 0 is written, c-bit parity mode is disabled. 76543210 0 fdet mbdis m3o8 uni refr aisc cbe 7 aispat
register description 44 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 frmr interrupt enable (ace=0) read/write addresses: 35 h reset value: 00 h bit name description 7cofae (ds3 change of frame alignment enable) the cofae bit enables an interrupt to be generated when a change of frame alignment (i.e. a cofa event) occurs. when cofae is set to logic 1, the interrupt output, intb, is set low when the cofa event occurs. 6rede (ds3 red alarm enable) the rede bit enables an interrupt to be generated when a change of state of the ds3 red indication occurs. the ds3 red indication is visible in the redv bit location in the ds3 frmr status register and on the roof/rred pin when the redo bit in th e master alarm enable register (register 06hex) is set to logic 1. when rede is set to logic 1, the interrupt output, intb, is se t low when the state of the red indication changes. 5cbite (ds3 c-bit identification enable) the cbite bit enables an interrupt to be generated when a change of state in the c-bit identification indication internal to th e ds3 frmr occurs. when cbite is set to logic 1, the interrupt output, intb, is set low when the state of the c-bit identification in dication changes. 4ferfe (ds3 far end receive failure enable) the ferfe bit enables an interrupt to be generated when a change of state of the ferf indication occurs. the ferf indication is visible in the ferfv bit location in the ds3 frmr status register and on the rferf pin. when ferfe is set to logic 1, the inter rupt output, intb, is set low when the state of the ferf output changes. 3idle (ds3 idle enable) the idle bit enables an interrupt to be generated when a change of state of the ds3 ais signal detector occurs. when idle is se t to logic 1, the interrupt output, intb, is set low when the state of the idle detector changes. 2aise (ds3 alarm indication signal enable) the aise bit enables an interrupt to be generated when a change of state of the ds3 ais signal detector occurs. the state of th e ais detector is visible in the aisv bit location in the ds3 frmr status register and on the rais pin. when aise is set to logic 1, the interrupt output, intb, is set low when the state of the ais detector changes. 1oofe (ds3 out of frame enable) the oofe bit enables an interrupt to be generated when a change of state of the ds3 frmr frame alignment acquisition circuitry occurs. the state of the frame alignment acquisition circuitry occurs. the state of the frame alignment acquisition circuitry i s visible in the oofv bit location in the ds3 frmr status register and on the roof/rred pin when the redo bit in the master alarm enable register is logic 0. when the circuitry has lost frame aliment and is searching for the new alignment, and out frame is indicat ed and the oofv bit and roof pin are set to logic 1. when the circuitry has found frame alignment, the oofv bit and roof pin are set t o logic 0. when oofe is set to logic 1, the interrupt output, intb, is set low when the state of the oof indication changes. 0lose (ds3 loss of signal enable) the lose bit enables an interrupt to be generated when a change of state of the loss of signal detector occurs. the state of th e detector is visible in the losv bit position in the ds3 frmr status register and on the rlos pin. when lose is set to logic 1, the interrupt output, intb, is set low when the state of the los indication changes. 76543210 0 rede cbite ferfe idle aise oofe lose 7 cofae
register description 45 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 frmr additional configuration register (ace=1) read/write addresses: 35 h reset value: 00 h bit name description 7-6 unused must be zero for normal operation. 5 aisones (ds3 alarm indication signal) the aisones bit controls the pattern used to detect the alarm i ndication signal (ais) when both aispat and aisc bits in ds3 frmr configuration register (34h) are logic 0; if either aispat or aisc are logic 1, the aisones bit is ignored. when a logic 0 is written to aisones, the algorithm checks that a framed all-ones payload pattern (1111...) signal is observed for a period of ti me before declaring ais. only the payload bits are observed to follow an all-ones pattern, the overhead bits (x, p, m, f, c) are i gnored. when a logic 1 is written to aisones, the algorithm checks that an unframed all-ones pattern (1111...) signal is observed for a period of time before declaring ais. in this case all the bits, including the overhead, are observed to follow an all-ones pattern. th e valid combinations of aispat, aisc, and aisones bits are summarized below: 4 bpvo (ds3 bipolar violations) the bpvo bit enables only bipolar violations to indicate line code violates and be accumulated in the pmon lcv count registers. when bpvo is set to logic 1, only bpvs not part of a valid b3zs signature generate an lcv indication and increment the pmon lcv counter. when bpvo is set to logic 0, both bpvs not part of a va lid b3zs signature, and either 3 consecutive zeros or excessive zeros generate an lcv indication and increment the pmon lcv counter. 3 exzso (ds3 excessive zero occurrences) the exzso bit enables only summed zero occurrences to be accumula ted in the pmon exzs count registers. when exzso is set to logic 1, any excessive zero occurrences over an 85 bit period increments the pmon exzs counter by one. when exzso is set to logic 0, summed lcvs are accumulated in the pmon exzs count registers. a summed lcv is defined as the occurrence of either bpvs not part of a valid b3zs signature or 3 consecutive zeros (o r excessive zeros if exzdet=1) occurring over an 85 bit period ; each summed lcv occurrence increment the pmon exzs counter by one. 2 extype (ds3 excessive zero type) the extype bit determines the type of zero occurrences to be included in th e lcv indication. when extype is set to logic 1, the occurrence of an excessive zero generates a single pulse indication that is used to indicate an lcv.when extype is set to logic 0, every occurrence of 3 consecutive zeros generates a pulse indication that is used to indicate an lcv. for example, if a sequenc e of 15 consecutive zeros were received, with extype=1 only a single lcv would be indicated for this string of excessive zeros; with extype=0, five lcvs would be indicated for this string (i.e. one lcv for every 3 consecutive zeros). 1 salgo (ds3 signature algorithm) the salgo bit determines the criteria used to establish a vali d b3zs signature used to map bpvs to line code violation indicati ons. any bpv that is not part of a valid b3zs signature is indicated as an lcv. when the salgo bit is set to logic 1, a valid b3zs s igna- ture is declared whenever a zero followed by a bipolar violation is observed. when salgo is set to logic 0, a valid b3zs signat ure is declared whenever a zero followed by a bipolar violation of the opposite polarity to the last observed bpv is seen. 0 algotype (ds3 algorithm type) the algotype bit determines the criteria used to decode a valid b3zs signature. when the algotype is set to logic 1, a valid b3zs signature is declared and 3 zeros substituted whenever a zero followed by a bipolar violation of the opposite polarity to the last observed bpv is seen. when the algotype bit is set to logic 0, a valid b3zs signature is declared and the 3 zeros are substitut ed whenever a zero followed by a bipolar violation is observed. 76543210 0 0 aisones bpvo exzso extype salgo algotype 7 0 aispat aisc aisones ais detected 1 0 x framed ds3 stream containing repeating 1010... pattern; overhead bits ignored. 0 1 x framed ds3 stream containing c-bits all logic 0; payload bits ignored. 1 1 x framed ds3 stream containing repeating 1010... pattern and c-bits all logic 0. 0 0 0 framed ds3 stream containing all-ones payload pattern; overhead bits ignored. 0 0 1 unframed all-ones ds3 stream.
register description 46 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 frmr interrupt status read/write addresses: 36 h reset value: 00 h bit name description 7cofai (ds3 change of frame alignment indication) the cofai bit indicates that a change of frame alignment (i.e. a cofa event) signal detector has occurred. when the cofai bit is a logic 1, the frame alignment acquisition circuitry has detected that the new alignment differs from the previ- ous frame alignment. when the cofai bit is logic 0, there was no difference from the current frame alignment and the previous f rame alignment. 6redi (ds3 red indication) the redi bit indicates that a change of state of the ds3 red indication has occurred. the ds3 red indication is visible in the redv bit location of the ds3 frmr status register and on the roof/rred pin when the redo bit in the master alarm enable register (register 06hex) is set to logic 1. when the redi bit is a logic 1, a change in the red state has occurred. when the redi bit is logic 0, no change in the red stat e has occurred. 5cbiti (ds3 c-bit identification) the cbiti bit indicates that a change of state in the c-bit identification indication internal to the ds3 frmr has occurred. when the cbiti bit is a logic 1, a change in the internal cbit state has occurred. when the cbiti bit is logic 0, no change in the cbit state has occurred. 4ferfi (ds3 ferf indication) the ferfi bit indicates that a change of state of the ferf indication has occurred. the ferf indication is visible in the ferfv bit location of the ds3 frmr status register and on the rferf pin. when the ferfi bit is a logic 1, a change in the ferf state has occurred. when the ferfi bit is logic 0, no change in the ferf state has occurred. 3idli (ds3 idle signal detector) the idli bit indicates that a change of state of the ds3 idle signal detector has occurred. when the idli bit is a logic 1, a c hange in the idle detector state has occurred. when the idli bit is logic 0, no change in the idle signal detector state has occurred. 2aisi (ds3 ais signal detector) the aisi bit indicates that a change of state of the ds3 ais signal detector has occurred. the state of the ais detector is vis ible in the aisv bit location in the ds3 frmr status register and on the rais pin. when the aisi bit is a logic 1, a change in the ais dete ctor state has occurred. when the aisi bit is logic 0, no change in the ais detector state has occurred. 1oofi (ds3 frmr status) the oofi bit indicates that a change of state of the ds3 frmr status frame alignment acquisition circuitry has occurred. the st ate of the frame alignment acquisition circuitry is visible in the oofv bit location in the ds3 frmr status register and on the roo f/ rred pin when the redo bit in the master alarm enable register is logic 0. when the circuitry has lost frame alignment and is searching for the new alignment, an out frame is indicated and the oofv bit and roof pin are set to logic 1. when the circuitry has found frame alignment, the oofi bit and roof pin are set to logic 0. when the oofv bit is a logic 1, a change in the oof state has occurred. when the oofv bit is logic 0, no change in the oof stat e has occurred. 0losi (ds3 loss of signal) the losi bit indicates that a change of state of loss of signal detector has occurred. the state of the detector is visible in the losv bit position in the ds3 frmr status register and on the rlos pin. when the losi bit is a logic 1, a change in the los state has occurred. when the losi bit is logic 0, no change in the los state has occurred. 76543210 0 redi cbiti ferfi idli aisi oofi losi 7 cofai
register description 47 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 frmr status read/write addresses: 37 h reset value: 00 h bit name description 7ace (ds3 additional configuration enable) the ace bit selects the additional configuration register. this register is located at address 35h, and is only accessible when the ace bit is to logic 1. when ace is set to logic 0, the interrupt enable register is accessible at address 35h. 6redv (ds3 red alarm violation) the redv bit indicates the current state of the ds3 red indication. when the redv bit is a logic 1, the ds3 frmr alignment acqu i- sition circuitry has been out of frame for 2.23ms (or for 13.5ms when fdet is logic 0). when the redv bit is logic 0, the frame align- ment circuitry has found frame (i.e. oodfv=0) for 2.23ms (or 13.4ms if fdet=0) 5cbitv (ds3 c-bit violation) the cbitv bit indicates the current state in the c-bit identification indication. when the cbitv bit is a logic 1, the first c- bit or m sub- frame 1 has been observed to be logic 1 for 63 consecutive occasions. when the cbitv bit is logic, the first c-bit of sub-frame 1 has either not been logic 1 for 63 consecutive occasions or, if cbitv was previously logic 1, the first c-bit of sub-frame 1 has be en observed to be logic 0 for 2 or more times within 15 consecutive occasions. 4ferfv (ds3 far end enable error violation) the ferfv bit indicates the current state of the ferf indication. when the ferfv bit is a logic 1, the frmr detects that the se cond to last m-frame?s x2=x1=0. when the ferfv bit is logic 0, the second to last m-frame?s x2=x1=1. 3idlv (ds3 idle violation) the idlv bit indicates the current state of the ds3 idle signal detector. when the idlv bit is a logic 1, the ds3 idle pattern has been received for 2.23ms (or for 13.5ms when fdet is logic 0). when the idlv bit is logic 0, the ds3 idle pattern has not been received for either 2.23ms or 13.5ms. 2aisv (ds3 alarm indication violation) the aisv bit indicates the current state of the ds3 ais signal detector. when the aisv bit is a logic 1, the ds3 ais pattern ha s been received for 2.23ms (or for 13.5ms when fdet is logic 0). when the aisv bit is logic 0, the ds3 ais pattern has not been receiv ed for either 2.23ms or 13.5ms. 1oofv (ds3 out of frame violation) the oofv bit indicates the current state of the ds23 frmr frame alignment acquisition circuitry. when the circuitry has lost fr ame alignment and is searching for the new alignment, an out of frame is indicated and the oofv bit is set to logic 1. when the cir cuitry has found frame alignment, the oofv bit is set to logic 0. 0losv (ds3 los of signal violation) the losv bit indicates the current state of the loss of signal detector. when the losv bit is a logic 1, a sequence of 175 cons ecutive zeros was detected on the dual-rail rpos and rneg ds3 inputs. when the losv bit is logic 0, a valid ds3 signal with a ones? den - sity greater than 33% for 175 1 bit periods was detected on the dual-rail inputs. 76543210 0 redv cbitv ferfv idlv aisv oofv losv 7 ace
register description 48 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 frmr configuration read/write addresses: 40 h , 50 h , 60 h , 70 h , 80 h , 90 h , a0 h reset value: 00 h bit name description 7g747 (ds2 g.747 enable) the g747 bit configures the frmr for g.747 operation. if the g747 bit is a logic 1, the frmr will process a g.747 signal. if th e g747 bit is a logic 0, the frmr will process a ds2 signal as defined in ansti t1.107 section 7. 6 unused must be zero for normal operation. 5word (ds2 frame alignment signal errors method) the word bit determines the method of accumulating g.747 framing errors. if the word bit is a logic 0, each frame alignment sig nal (fas) bit error results in a single ferr count. if the word bit is a logic 1, one or more bit errors in a fas word result in a single ferr count. 4m2o5 (ds2 m-bit 2 out of 5) the m2o5 bit selects the error ratio for declaring out-of-frame (oof) when in ds2 mode only. when a 1 is written to m2o5, the f ramer declares oof when 2 f-bit errors out of 5 consecutive f-bits are observed. when a 0 is written, the framer declares oof when 2 f-bit errors out of 4 consecutive f-bits are observed. (these two ratios are recommended in t-tsy000009 section 4.1.2). when the frmr is con fig- ured for g.747 operation (the g747 bit is set to logic 1), the oof status is declared when 4 consecutive framing word errors oc cur (as per ccitt rec. g747 section 4), regardless of the m2o5 bit setting. 3mbdis (ds2 m-bit error disable) the mbdis bit disables the declaration of out-of-frame upon excessive m-bit errors. if mbdis is a logic 0, out-of-frame is decl ared when one or more m-bit errors are detected in 3 out of 4 consecutive m-frames. if mbdis is a logic 1, the state of the m-bits is ignored once in frame. regardless of the state of the mbdis bit, the f-bits are always monitored for invalid framing. 2ref (ds2 reframing mode) the ref bit is used to trigger reframing. if a logic 1 is written to ref when it was previously logic 0, the frmr is forced out -of-frame, and a new search for frame alignment is initiated. note that only a low-to-high transition of the ref bit triggers reframing; multipl e write opera- tions are required to ensure such a transition. 1-0 unused must be zero for normal operation. 76543210 0 0 word m2o5 mdbis ref 0 0 7 g747
register description 49 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 frmr interrupt enable read/write addresses: 41 h , 51 h , 61 h , 71 h , 81 h , 91 h , a1 h reset value: 00 h bit name description 7cofae (ds2 change of frame alignment enable) the cofae bit is an interrupt enable. a change of frame alignment (cofa) event causes the interrupt output to be set high when the cofae bit is written with a logic 1. 6 unused must be zero for normal operation. 5rede (ds2 red alarm enable) the rede bit is a interrupt enable. a change of state on a corresponding ds2 frmr status causes the interrupt output intb, to b e asserted low when the corresponding interrupt enable bit is written with a logic 1. 4ferfe (ds2 far end receive error enable) the ferfe bit is a interrupt enable. a change of state on a corresponding ds2 frmr status causes the interrupt output intb, to be asserted low when the corresponding interrupt enable bit is written with a logic 1. 3rese (reserved bit enable) the rese bit is an interrupt enable. a change in the debounced value of the reserved bit in set ii when in g.747 mode causes th e interrupt output to be set high when the rese bit is written wi th a logic 1. the debounced value of the reserved bit only chang es when the reserved bit is the same for two consecutive frames. the rese bit has no effect in ds2 mode the interrupt output, intb m is deasserted when the interrupt status register is read if its assertion was a result an oof, ais, ferf, red, res, or cofa eve nt. 2aise (ds2 alarm indication signal interrupt enable) the aise bit is a interrupt enable. a change of state on a corresponding ds2 frmr status causes the interrupt output intb, to b e asserted low when the corresponding interrupt enable bit is written with a logic 1. 1 oofe (ds2 out of frame interrupt enable) the oofe bit is a interrupt enable. a change of state on a corresponding ds2 frmr status causes the interrupt output intb, to b e asserted low when the corresponding interrupt enable bit is written with a logic 1. 0 unused must be zero for normal operation. 76543210 0 0 rede ferfe rese aise oofe 0 7 cofae
register description 50 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 framer interrupt status read/write addresses: 42 h , 52 h , 62 h , 72 h , 82 h , 92 h , a2 h reset value: 00 h bit name description 7cofai (ds2 change of frame alignment indication) the cofai bit is an interrupt status indicator. as per tr-tsy-000820, the change of frame alignment (cofa) interrupt is only asserted if a frame search results in a frame alignment which is different from the prior frame alignment. 6 unused must be zero for normal operation. 5redi (ds2 red alarm interrupt indication) the redi bit is a interrupt status indicator. a change of state on the corresponding ds2 frmr status causes the corresponding interrupt status bit to be set to logic 1. 4ferfi (ds2 far end receive frame interrupt indication) the ferfi bit is a interrupt status indicator. a change of state on the corresponding ds2 frmr status causes the corresponding interrupt status bit to be set to logic 1. 3 resi (ds2 reserved bit indication) the resi bit is an interrupt status indicator. a change in the debounced value of the reserved bit in set ii when in g.747 mode causes this bit to be set to logic 1. the debounced value of the reserved bit only changes when the reserved bit is the same fo r two consecutive frames, this bit has no effect in ds2 mode. 2aisi (ds2 alarm indication signal interrupt indication) the aisi bit is a interrupt status indicator. a change of state on the corresponding ds2 frmr status causes the corresponding i nter- rupt status bit to be set to logic 1. 1oofi (ds2 out of frame violation interrupt indication. the oofi bit is a interrupt status indicator. a change of state on the corresponding ds2 frmr status causes the corresponding interrupt status bit to be set to logic 1. 0 unused must be zero for normal operation. 76543210 cofai 0 redi ferfi resi aisi oofi 0 7
register description 51 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 framer status read/write addresses: 43 h , 53 h , 63 h , 73 h , 83 h , 93 h , a3 h reset value: 00 h bit name description 7-6 unused must be zero for normal operation. 5redv (ds2 red alarm violation) the redv bit is a logic 1 if an out-of-frame condition has persisted for 9.9ms (6.9ms in g.747 mode). this is less than 1.5 tim es the maximum average reframe time allowed. the redv status will remain asserted for 9.9ms (6.6ms in g.747 mode) after frame align- ment has been declare and then become logic 0. 4 ferfv (ds2 far end receive frame violation) the ferfv bit in this register reflects the status of the corresponding ds2 frmr value. in ds2 mode, the ferfv bit reflects the debounced state of the x bit (first bit of the m4-subframe). if the x-bit has been a zero for two consecutive m-frames, the fer fv bit becomes a logic 1. if the x-bit has been a one for two consecutive m-frames, the ferfv bit becomes a logic 0. in g.747 mode, ferfv bit reflects the debounced state of the remote alarm indication (rai, bit 1 of set ii) bit. if the rai bit has been a one for two consecutive frames, the ferfv bit becomes logic 1. if the rai bit has been a zero for two consecutive frames , the ferfv bit becomes a logic 0. a six frame latency of the ferfv status ensures a virtually 100% probability of freezing correctly in ds2 mode upon an out-of-f rame condition and a better than 99.9% probability of freezing correctly in g.747 mode. 3 resv (ds2 reserved bit violation) the resv bit reflects the debounced state of the reserved bit in set ii when in g.747 mode. the debounced value of the reserved bit only changes when the reserved bit is the same for two consecutive frames. 2aisv (ds2 alarm indication signal violation) the aisv bit in this register reflects the status of the corresponding ds2 frmr value. the aisv bit is a logic 1 if ais has bee n declared. 1oofv (ds2 out of frame violation) the oofv bit in this register reflects the status of the corresponding ds2 frmr value. the oofv bit is a logic 1 if the ds2 fra mer is presently out-of-frame. 0 unused must be zero for normal operation. 76543210 0 0 redv ferfv resv aisv oofv 0 7 0
register description 52 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 framer monitor interrrup enable/status read/write addresses: 44 h , 54 h , 64 h , 74 h , 84 h , 94 h , a4 h reset value 00 h bit name description 7-3 unused must be zero for normal operation. 2inte (ds2 interrupt enable) the interrupt enable (inte) bit allows the ds2 frmr to assert the intb output upon register transfers. a logic 1 in the inte bi t posi- tion enables the ds2 to generate a microprocessor interrupt when the counter values are transferred to a holding registers. a l ogic 0 in the inte bit position disables the ds2 frmr from generating an interrupt. when the tsb is reset, the inte bit is set to lo gic 0, disabling the interrupt. the interrupt is cleared when this regist er is read if its assertion was a result a transfer operation . 1intr (ds2 interrupt) the interrupt (intr) bit indicated the current status of the internal interrupt signal. a logic 1 in this bit position indicate s that a transfer of counter values to the holding registers has occurred; a logic 0 indicates that no transfer has occurred. this bit is set to logic 0 when this register is read. the value of the intr bit is not affected by the value of the inte bit. 0ovr (ds2 overrun) the overrun (ovr) bit indicates the overrun status of the holding registers. a logic 1 in this bit position indicates that a pr evious interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have been overwritten. a logic 0 indicates that no overrun has occurred. this bit is reset to logic 0 when this register is read. to generate a transfer of the counters to the holding registers, a microprocessor write to the global pmon update register is required. ds2 frmr ferr count read/write addresses: 45 h , 55 h , 65 h , 75 h , 85 h , 95 h , a5 h reset value: 00 h bit name description 7-0 ferr7-0 (ds2 framing bit error) this register indicates the number of ds2 framing bit error events or g.747 framing word errors that occurred during the previo us accumulation interval. a ds2 framing bit error event is either an m-bit or and f-bit error. one or more bit errors in a g.747 f rame alignment signal results in a single framing word error. a transfer operation can be triggered by writing to the global pmon up date register. 76543210 00000inteintrovr 7 0 76543210 0 ferr6 ferr5 ferr4 ferr3 ferr2 ferr1 ferr0 7 ferr7
register description 53 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2 frmr perr count (lsb) read/write addresses: 46 h , 56 h , 66 h , 76 h , 86 h , 96 h , a6 h reset value: 00 h bit name description 7-0 perr 7-0 (ds2 parity bit error) these registers indicate the number of g.747 parity events that occurred during the pervious accumulation interval. a transfer operation can be triggered by writing to the global pmon update register ds2 frmr perr count (msb) read/write addresses: 47 h , 57 h , 67 h , 77 h , 87 h , 97 h , a7 h reset value: 00 h bit name description 7-5 unused must be zero for normal operation. 4-0 perr 12-8 (ds2 parity bit error) these registers indicate the number of g.747 parity events that occurred during the pervious accumulation interval. a transfer operation can be triggered by writing to the global pmon update register 76543210 perr7 perr6 perr5 perr4 perr3 perr2 perr1 perr0 7 76543210 0 0 0 perr12 perr11 perr10 perr9 perr8 7
register description 54 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx12 configuration and control read/write addresses: 48 h , 58 h , 68 h , 78 h , 88 h , 98 h , a8 h reset value: 00 h bit name description 7g747 (g747 configuration) when g747 is high, the mx12 supports ccitt recommendation g.747. in this mode, three 2048b/bits tributaries are multiplexed into and demultiplex out of a 840 bit frame. if g747 is low, the frame is compatible with ds2 as specified in the ansi t1.107 s tan- dard. 6pinv (g747 parity inversion) when pinv is set high, the transmitted parity bit in the g.747 formatted output stream is inverted for diagnostic purposes. thi s only has effect when the g747 bit is high. 5minv (g747 m-bit inversion) when minv is set high, the transmitted m bits in the ds2 output stream are inverted for diagnostic purposes. this only has effe ct when the g747 bit is low. 4finv (g747 f-bit inversion) when finv is set high and g747 is low, all the transmitted f bits in the ds2 output stream are logically inverted for diagnosti c purposes. if g.747 is high when finv is set high, the nine bit frame alignment signal (111010000) is logically inverted (i.e. 000101111). 3 xais (transmit ais) when set high, the xais bit enables the transmission of the alarm indication signal (ais) in the 6312kbit/s output stream. when xais is set high, the transmitted data is set to all ones; otherwise the transmitted data is not affected. 2xferf (transmit far end receive failure) when set high, the xferf bit enables the transmission of the far end receive failure (ferf0 signal in the ds2 output stream when in ds2 mode (i.e.g747 bit low). when xferf is set high, the transmitted x bit is set to 0, provided that ais is not being transmitted; otherwise the transmitted x bit is set to 1. when in g.747 mode (i.e. g747 bit high), the remote alarm indication (rai) is set to 1 when xferf is set high; otherwise, the transmitted rai bit is set to 0 unless ais is being transmitted. 1xres (transmit reserved bit) the xres bit only has effect in g.747 mode. when xres is set high and ais is not being transmitted, the reserved bit (set ii, b it 3) is set to 0; otherwise, the transmitted reserved bit is set to 1. 0inte (loopback requirement interrupt enable) when set high, the inte bit enables the activation of the interrupt output, intb, whenever any of the lbri 4-1 bits are set hig h in the loopback request interrupt register. interrupts are masked when inte is cleared low. 76543210 0 pinv minv finv xais xferf xres inte 7 g747
register description 55 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx12 loopback code select register read/write addresses: 49 h , 59 h , 69 h , 79 h , 89 h , 99 h , a9 h reset value: 00 h bit name description 7-2 unused must be zero for normal operation. 1-0 lbcode1-0 (loopback code) the lbcode 1-0 bits select the valid state for a loopback request coded in the c-bits of the ds2 signals. transmit and receive are not independent; the same code is expected in the demultiplexed ds2 as is inserted in the ds2 to be multiplexed. the following table gives the correspondence between lbcode 1-0 bits and the valid codes: if lbcode 1-0 is ?b00 or ?b11, the loopback code is as per ansi t1.107 section 7.2.1.1 and tr-tsy-000009 section 3.7. because tr-tsy-000233 section 5.3.14.1 recommends compatibility with non-compliant existing equipment, the two other loopback com- mand possibilities are also supported. the lbcode 1-0 bits will also select the valid state for a loopback request coded in the c-bits of the g.747 formatted signal. again, the transmit and receive are not independents; the same code is expected in the demultipl exed g.747 stream as is inserted in the g.747 stream to be multiplexed. the valid codes are the same as those for the ds2 formatted stream given in the table above. the lbcode 1-0 bits become logical 0 upon either a hardware or software reset. 76543210 000000lbcode1lbcode0 7 0 lbcode 1-0 loopback code 00 c1 = c2 and c1 = c3 01 c1 = c3 and c1 = c2 10 c1 = c3 and c1 = c2 11 c1 = c2 and c1 = c3
register description 56 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx12 ais insert register read/write addresses: 4a h , 5a h , 6a h , 7a h , 8a h , 9a h , aa h reset value: 00 h bit name description 7-4 mais4-1 (m12 mux alarm indication signal) setting any of the mais [4:1] bits activate insertion of the alarm indication signal (all ones) into the corresponding low spee d stream multiplexed into the 6312kbits high speed output signal. mux ais insertions takes place before the point where remote loopback may be invoked using the loopback activate register and thus mux ais cannot be inserted while a loopback is activated. 3-0 dais4-1 (m12 demux alarm indication signal) setting any of the dais 4-1 bits activates insertion of the alarm indication signal (all ones) into the corresponding low speed stream demultiplexed from the 6312kbits high speed input signal. demux ais insertion takes place after the point where remote loopback may be invoked using the loopback activate register thus demux ais to be inserted into the through path while a loopback is act i- vated, if desired. mx12 loopback activate register read/write addresses: 4b h , 5b h , 6b h , 7b h , 8b h , 9b h , ab h reset value: 00 h bit name description 7-4 ilbr 4-1 (insertion loopback request) in ds2 mode, setting any of the ilbr 4-1 bits enable the insertion of a loopback request in the corresponding ds1 stream in the ds2 output signal. the format of the loopback request is determined by the lbcode 1-0 bits in the loopback code select mx12 regis- ter. in g.747 mode, ilbr[j] inverts bit cj1, cj2, or cj3 in the g.747 frame in an analogous fashion. 3-0 lba 4-1 (loopback activation) setting any of the lba 4-1 bits activates loopback of the corresponding low speed stream from the high speed input signal to th e high speed output signal. lba4 has no effect in g.747 mode, but lba 3-1 activates the loopback of the corresponding 2048kbits signals. the demultiplexed ds1 signals continue to present valid payloads while loopbacks are activated. the mx12 ais insert re g- ister allows insertion of ds1 ais if required. 76543210 0 mais3 mais2 mais1 dais4 dais3 dais2 dais1 7 mais4 76543210 0 ilbr3 ilbr2 ilbr1 lba4 lba3 lba2 lba1 7 ilbr4
register description 57 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice mx12 loopback interrupt register read/write addresses: 4c h , 5c h , 6c h , 7c h , 8c h , 9c h , ac h reset value: 00 h bit name description 7-4 lbri4-1 (loopback request interrupt) the lbr 4-1 bits are set high when a loopback request is asserted or deasserted for the corresponding low speed stream in the high speed input signal. the lbr 4-1 bits are set high whenever the corresponding lbrd 4-1 bits change state. if interrupts are enabled using the inte bit in the configuration register then the interrupt output, intb is activated. the lbri 4-1 bits are cl eared low immediately following a read of the register, acknowledging the interrupt and deactivating the intb output. 3-0 lbrd4-1 (loopback request detached) the lbrd 4-1 bits are set high while a loopback request is detected for the corresponding low speed stream in the high speed input signal. the lbrd 4-1 bits are set low otherwise. the fo rmat of the loopback request expected is determined by the lbcode 1-0 bits in the mx12 loopback code select register. as per tr-tsy000009 section 3.7, the loopback request must be present for five successive m-frames before declaration of detection. removal of the loopback request is declared when it has been absent f or five successive m-frames. ds1 transmit and receive edge select read/write addresses: 4d h , 5d h , 6d h , 7d h , 8d h , 9d h , ad h reset value: 00 h bit name description 7-4 txesel4-0 (ds1 transmit edge select) transmit edge select when 0 the ds1 data will be transmitted on the rising edge of td1clk. when 1 the ds1 data will be transmit - ted on the falling edge of td1clk. 3-0 rxesel4-0 (ds1 receive edge select) receive edge select when 1 the ds1 data will be sampled on the rising edge of rd1clk. when 0 the ds1 data will be sampled on the falling edge of rd1clk. 76543210 0 lbri3 lbri2 lbri1 lbrd4 lbdr3 lbdr2 lbdr1 7 lbri4 76543210 0 txesel3 txesel2 txesel1 rxesel4 rxesel3 rxesel2 rxesel1 7 txesel4
register description 58 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
functional description 59 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.1 ds3 framer figure 1 ds3 framer block figure 2 ds3 frame fifo tdat b3zs encoder ds3 framer 1:7 fifo ds2 ds2 external oh m23 / c-bit mode oh stuffing rdat b3zs decoder ds3 framer 1:7 6143 drw 31a external oh status ds2 ds2 x1 x2 p1 p2 m1 m2 m3 f1 f1 f1 f1 f1 f1 f1 c1 c1 c1 c1 c1 c1 c1 f2 f2 f2 f2 f2 f2 f2 c2 c2 c2 c2 c2 c2 c2 f3 f3 f3 f3 f3 f3 f3 c3 c3 c3 c3 c3 c3 c3 f4 f4 f4 f4 f4 f4 f4 84-bits m sub-frame m frame 680 bits 6143 drw19 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits 84-bits nominal ds2 rate 6,312kbits/sec and multiplexing four tributaries @1,544kbit/s (6,176kbit/s) nominal ds3 rate 44.736mb/s and multiplexing seven tributaries @ 6,312kbits/sec stuff block the nominal ds3 interface is 44.736 mb/s 20ppm ( 895 b/s). a ds3 m-frame (multiframe) is composed of seven ds3 m-subframes. each m-subframe contains eight blocks of 84 payload bits (bit-interleaved from the seven ds2 or 28 ds1 streams) plus one overhead bit (the seven subframes do not represent each separate ds2 signals). the ds3 frame contains a total of 4,760 bits of which there are 4,704 payload bits and 56 overhead bits. the total period of a ds3 frame is 106.4 s (44.736e-6 x 4,760).
functional description 60 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 3 b3zs coding 10 1 0 0 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 e o e ov o e bv ov bv 6143 drw53 1.1.1 framing modes 1.1.1.1 m23 mode in m23 mode the three c-bits per ds3 m-subframe indicate the nature of stuff opportunity bit in the last block of the m-subframe. stuffing is further explained in the m23 section. 1.1.1.2 c-bit parity mode in c-bit parity mode the ds2s operate at the nominal ds2 rate and thus no stuffing is required. as such all the stuff opportunity bits contain stuffing (null bit) and the c-bits are used to carry performance monitoring, alarm, control and data link channel. 1.1.1.3 transparent mode 1.1.2 reframing 1.1.2.1 procedure the search of frame alignment (based on f-bits and m-bits) will happen in two cases: ? after a reset. ? after an internal out of frame (oof) declaration. ? when the microprocessor forces the reframing process. the algorithm of reframing is based on the following steps: ? the ds3 framer will search for the f-bits in order to find one potential m-subframe alignment. ? then the ds3 framer will process the m-bits to detect the m-frame structure (x-bits and p-bits are ignored during the reframing operation). ? framing is declared if the m-bits are correct for three consecutive m-frames (and no f-bits error is detected). ? x-bits and p-bits are ignored 1.1.2.2 max time the mart, maximum average reframing time (the average time necessary when processing all the bits in the m-frame), is 1.5ms. framing goes from ds3 framing to ds2 framing. 1.1.3 errors and alarms 1.1.3.1 line management all the alarms and errors associated with line management must be processed if the coding/decoding f unction is implemented. the 82v8313 will manage the ds3 liu (counting and reporting errors). but the ds3 liu has to control the ds3 line (encoding / decoding and errors detec- tion). 1.1.3.1.1 bnzs coding overview bnzs corresponds to an ami line code with the substitution of a unique code to replace occurrences of n consecutive zero signal elements. for ds3 lines, a b3zs code (three-zero substitution) is used. in the b3zs format, each block of three consecutive zeros is removed and replaced by a b0v or 00v code: ? b represents a pulse conforming to the bipolar rule. ? 0 is a zero (no pulse). ? v represents a pulse violating the bipolar rule. the choice of b0v or 00v is made so that the number of b pulses between consecutive v pulses is odd. for ds1 lines, a b8zs code is used (no more than seven consecutive zeros on a ds1 line).
functional description 61 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.1.3.1.2 bipolar violation description bipolar violation error (bpv) is declared when a pulse presents the same polarity as the previous ?1? while also not following the b3zs coding. this is the mechanism used to determine if there is a true line code violation or if there is a subs titution. for each ds3 line code viola- tion the 82v8313 will increment the ds3lcv count register (0x14 and 0x15). 1.1.3.1.3 excessive zeros error description exz is declared on occurrence of more than n consecutive zeros for bnzs coded signal. for each exz violation the 82v8313 will increment the ds3 exzs count register (0x18 and 0x19). 1.1.3.1.4 los description a los defect occurs when there are 175 75 contiguous pulse posi- tions shifted in the device with no pulses of either positive or negative polarity at the line interface. a los defect is ended when there is a detection of an average pulse density of at least 33% (for t3 line) over a same period (12.5% for t1 line). los failure is declared when los defect persists for 2.5 0.5s. los failure is cleared when los defect is absent for 10 0.5 seconds for t3 line (20 seconds or less for t1 line). a los is indicated in the ds3 framer interrupt status register (0x36) and the ds3 framer status (0x37). 1.1.3.2 oof (out of frame) oof shall be declared when there is a significant ratio of frame align- ment, f-bit, errors. the typical ratio is three (or more) errors out of 16 (or fewer) consecutive framing f-bits?a sliding window methodology is implemented in the 82v8313. the algorithm used is a logical oring of 1 (or more) m-bit errors in 2 (or more) out of 4 (or fewer) consecutive m-frames with the f-bit error criteria. the oof defect is ended when the signal does not contain any more fram ing bits (f-bits and m-bits) error in several consecutive frames (1 m-frame or more). the defect detection and termination must be done in less than 2.3ms (1.5 times the maximum average reframe time (mart). the 82v8313 can be config- ured for either 3 out of 16 consecutive f-bit errors or 3 out of 8 consecu- tive f-bit errors (ds3 framer configuration register 0x34). oof violations are monitored in the ds3 framer status register (0x37). 1.1.3.3 red alarm red defect is defined by the occurrence of oof or los in one m-frame. 1.1.3.4 lof (loss of frame) loss of frame: ? lof is declared when the oof persists for 2.5 0.5 s. ? lof is cleared when the oof defect is absent for 10.0 0.5 s. fcp (failure count path) is incremented each time lof failure appears. 1.1.3.5 ais ais signal is transmitted downstream (instead of the normal signal to): ? maintain transmission continuity ? indicate to the receiving equipment that there is a transmission interruption located either at the equipment originating the ais signal or upstream of that equipment (ais is sent downstream until the incoming signal becomes correct again). different events can be declared as ais: ? incoming signal with valid framing (m and f-bits), valid parity, all ds3 stuff indicators c-bits set to 0, x-bits set to 1 and repeated information pattern 1010... (a 1 immediately following any of the control bit position) shall be identified as being ds3 ais. ? unframed all-ones signal = blue code. ? framed ds3 signal with the repeated payload pattern 1010. ? framed ds3 arbitrary pattern with all ds3 stuff indicators c-bits set to 0. ? framed ds3 1010 pattern with all ds3 stuff indicators c-bits set to 0. ? framed all-ones signal (the overhead bits are ignored). oof detection implies to insert ais downstream in 2.25 to 3ms. los or incoming ais implies to send ais downstream in maximum 0.15ms (0.1 mart). ais defect occurs upon detection of ais in contiguous m-frames for a time t, 0.2ms t 100ms. this defect must be detected and cleared properly in the presence of a random ber 10 -3 . in gr-499-core, it is specified that ais defect detection and termi- nation must be done in 2.3ms (1.5 x mart) and maximum removal time is 0.15ms (0.1 x mart). the 82v8313 has an integration counter which decrements for each invalid m-frame and increments the integration counter. in slow detection mode the count saturates 127 which results in a detection time of 13.5ms. in fast detection mode the saturation point is 21 and results in a detection time of 2.23ms. ds3 ais failure is declared if an ais defect persists for 2.5 0.5 s. ais failure is cleared if ais defect is absent for 10.0 0.5 s. typically an alarm indication signal counter on the system is incremented each time an ais failure appears. on the downstream data flow, two strategies must be activated during ais defect: ? continue data processing with the last correct frame alignment (off-line framer). note: due to the amount of errors (ais, lof or los failure activated), incoming data can have a m23 and m12 stuffing ratio between 0 and 100%. in the worst case, some applica- tions can have problems due to ds1 clock deviation: ds1 clock can vary between 1.544 mhz 1745 ppm and 1.544 mhz ? 3218 ppm. ? send a full 1?s signal to the hdlc controller: send downstream full 1?s (stopping ds2 and ds1 framers allowed: in that case, a full 1?s signal must be sent downstream the ds1 signals).
functional description 62 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.1.3.6 rai (remote alarm indication) 1.1.3.6.1 rai for c-bit parity mode the rai signal has to be imm ediately transmitted upon declaring los failure, lof or ais failure. an rai failure is declared as soon as any of the four following alarm si gnals are detected on the far-end alarm channel (feac, explained the following section): ? equipment failure (service affecting) ? los failure, lof or ais failure. rai failure is cleared as soon as the absence of all of the above alarm signals is detected. a system counter must be incremented by one each time the rai failure begins. 1.1.3.6.2 rai for m23 mode rai failure is declared when the far-end sef/ais defect (if implemented, x-bits) persists for 2.5 0.5s. the rai failure is cleared when sef/ais disappears for 10.0 0.5s. a counter must be incre- mented by one each time the rai failure begins. 1.1.3.7 parity error the 82v8313 uses even parity, which is defined as: if the digital sum of all information bits (4704 bits in the m-frame) is equal to 1 in the previous m-frame, the two p bits are set to 1 (similar for 0). error is indicated if the received p-bits do not match the locally calculated parity, or when the two p- bits do not agree. p-bit errors are counted in the p-bit error register (0xa and 0xb). parity error ratio, per, is typically defined as the number of parity errors detected divided by the number of m-frames examined. 1.1.3.8 x-bit: ferf ( far-end sef/ais = rdi) the two x-bits must be equal in an m-frame. if x1 = x2 = 0, the far end receive failure (ferf) is declared as soon as a valid framing is not identified or ais is received. ferf status remains in the previous state in the following cases: ? if x1 x2 ? if oof is detected: ferf status can be updated only after having completely processed the current incoming m-frame. if the current m-frame is numbered n, the last valid ferf information comes from m-frame numbered n-2 (error can start in end of m-frame n-1 and can be declared at the beginning of m-frame n). the x-bits must not change more than once per second. 1.1.3.9 idle signal if implemented, the idle signal must have correct m-bits, f-bits and p-bits. the 3 c-bits in subframe 3 of the m-frame must be set to 0 and all other c-bits can take any values (and may vary with time). the x-bits shall be set to 1 and the repeated information pattern 1100 must be sent (started with 11 after each m-frame alignment, m-subframe alignment, x- bit, p-bit and c-bit). such a signal is used before the customer initializes the channel to avoid declaration of alarm. the identification of the idle sig- nal should not exceed 10 seconds in duration. 1.1.3.10 c-bits signification if c-bit parity mode activated the c-bit parity mode (see m23 chapter) affected c-bits for special purposes (no more stuffing bit indicators): table 3 ?ferf status (x1 & x2 state) x1 x2 ferf status 00 1 0 1 previous state 1 0 previous state 11 0
functional description 63 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice table 4 ?c-bit parity mo de ds3 c-bit assignments m-subframe number c-bit number function 11 2 3 application identifications reserved for future network use far-end alarm and control (feac) 21 2 3 unused unused unused 31 2 3 cp (parity) cp (parity) cp (parity) 41 2 3 far-end block error (febe) far-end block error (febe) far-end block error (febe) 51 2 3 data link (dl) data link (dl) data link (dl) 61 2 3 unused unused unused 71 2 3 unused unused unused
functional description 64 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.1.3.10.1 aic the application identification channel is used to identify the specific ds3 m-frame application: ? in m23 mode: aic shall be random 1s and 0s. ? in c-bit parity mode: aic shall be set to 1 (in this mode, aic is not sufficient for determining identification of c-bit parity application. the process needs the confirmation by secondary methods such as the presence of 0s in the febe bit positions) ? unchannelized applications may have either any aic value (if developed before ansi t1.107 ? 1995 standards) or all 1s (as c-bit parity mode). the process to identify the ds3 application should typically not exceed 10 seconds in duration. 1.1.3.10.2 feac far end alarm and control signals are encoded into repeating 16-bit 0xxxxxx0 11111111 c odewords (right-most bit tr ansmitted first): the 6?bits x allowed 64 distinct signals; assigned codewords gr-499-core code words areincluded for reference: ? listing order is in decreasing priority order. codewords shall be transmitted continuously for the duration of the condition being reported, or 10 repetiions whichever is longer. ? control messages are higher in prio rity then any of the far end alarm signals. the idle state of the feac channel (no codeword is transmitted) is a full ones signal. a code is correct (no error during transmission) after being received 10 times. some implementations also use algorithms that take care of ber: a valid boc message is declared if a code is received 4 out of 5 times, or 8 out of 10 times as determined by the avc bit in the feac configuration register (0x32).
functional description 65 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice notes sa: service affecting. nsa: non-service affecting single ds1 los (2 and 3) 0 011110 0 11111111 1. applicable to b2zs-coded signal. ds1 equipment failure (nsa) (3) 0 000011 0 11111111 2. network equipment must not respond to or generate these codewords. 3. applicable to all type of loopbacks. 4. code must be transmitted 10 times, followed immediatel y by 10 repetitions of the ds3 or ds1 line codeword. 5. for unchannelized ds3 applications, ds1s are unassigned. *listing order is in decreasing priority order. codewords shall be transmitted continuously for the duration of the condition being reported, or 10 repetitions whichever is longer. **control messages are higher in priority than any of the far end alarm signals. table 5 ?ds3 feac loopback control messages condition codeword line loopback activate (4) 0 000111 0 11111111 line loopback deactivate (4) 0 011100 0 11111111 ds3 line 0 011011 0 11111111 ds1 line number n 0 1---n--- 0 11111111 (1 n 28) (5) ds1 line - all 0 010011 0 11111111 table 6 ?ds3 feac alarm and status messages function codeword ds3 equipment failure (sa) 0 011001 0 11111111 ds3 los (1) 0 001110 0 11111111 ds3 oof 0 000000 0 11111111 ds3 ais received 0 010110 0 11111111 ds3 idle signal received 0 011010 0 11111111 ds3 equipment failure (nsa) 0 001111 0 11111111 common equipment failure (nsa) 0 011101 0 11111111 multiple ds1 los (2 and 3) 0 010101 0 11111111 ds1 equipment failure (sa) (3) 0 000101 0 11111111
functional description 66 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 4 transmit boc figure 5 receive boc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 15 11111 654321 boc_reg [6:1] xboc ds3 c-bit parity feac 6143 drw 35 xxxxxx bit data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 15 11111 654321 boc_reg [6:1] rboc ds3 c-bit parity feac 6143 drw 36 xxxxxx bit data 1.1.3.10.3 bit oriented code detector (boc) the receive bit oriented code detector (rboc) is designed to detect the presence of bocs in the ds3 c-bit parity far end alarm and control (feac) channel. the rboc recognizes 63 of the 64 possible bocs, and purposefully ignores the ? 111111? c ode which is similar to the hdlc flag sequence. bocs are received in a feac channel as 16?bit sequences composed of an 8?ones header, a zero, six boc bits, and a trailing 0 (?111111110 xxxxxx0?). in order to validate a boc, the same code must be repeated at least ten times with at least 8 of 10 or 4 out 5 times (as specified by the avc bit) being the same. the rboc block will trigger an interrupt, unless masked, to indicate the receipt of a boc or when the boc disappears. if the boc receives an invalid code the boc bits will be set to ? 111111? the transmit bit oriented code (xboc) is designed to transmit bocs in the ds3 c-bit parity far end alarm and control (feac) channel. the xboc can transmit 63 of the 64 possible bocs, and purposefully ignores the ?111111? c ode which is similar to the idle hdlc flag sequence. bocs are transmitted in a feac channel as 16?bit sequences composed of an 8? ones header, a zero six boc bits, and a trailing 0 (? 11111111xxx xxx0?). the 16?sequence is repeated until disabled by forcing the six code bits to ?111111? some of the common bocs are listed here for reference.
functional description 67 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice notes: 1. sa-service affecting 2. nsa-non service affecting 3. applicable to b3zs - coded signal 4. newtork equipment must not respond to or generate these code words. 5. applicable to all types of loopbacks 6. code must be transmitted 10 times, followed immediately by 10 repetition of the ds3 or ds1 line code word. 7. for unchannelized ds3 applications, ds1 are unassigned. 1.1.3.10.4 terminal-to-terminal application specific data link the nine c-bits in m-subframes 2, 6 and 7 are reserved for application specific uses in ds3 terminal equipment. if they are not used, they will be set to one. 1.1.3.10.5 ds3 path parity bits the three cp-bits (parity bits instead of stuffing indication in c-bit parity mode) must be set to the same value as the two p-bits in the m-frame structure. some transport equipment in the network may alter p-bits, but any intermediate equipment on the ds3 path typically does not modify cp?bits. parity error detection (also called path error) is done by computing the parity of the information bits in the nth m-frame and is compared to the result with the majority value of the cpbits received in m-frame n + 1. 1.1.3.10.6 febe (far end block error) the three febe bits shall be set to any pattern other than 111 to indicate a far-end cp-bits error or framing (m or f-bits) error. the febe-bits are equal to 111 if no error is detected. 1.1.3.10.7 ds3pmon counters the ds3 performance monitor is a collection of counter registers for tracking c-bit parity errors (cperr), excessive zeros occurrences (exzs), far end block errors (febe), framing bit error (ferr), line code violations (lcv), and p-bit parity errors (perr). each counter can be individually cleared and accessed via microprocessor. if the counter is not cleared in an appropriate interval defined by the specific counter register, the counter will stay at the maximum value and not roll over. table 7 ?ds1 bit oriented codes command and response message function codeword line loopback activate 0 000111 0 11111111 line loopback deactivate 0 011100 0 11111111 payload loopback activate 0 001010 0 11111111 payload loopback deactivate 0 011001 0 11111111 for network use (loopback activate) 0 001001 0 11111111 universal loopback deactivate 0 010010 0 11111111 isdn line loopback (nt2) 0 010111 0 11111111 c1/csu line loopback 0 010000 0 11111111 for network use (nt1 power off) 0 001110 0 11111111 protection switch line n (1 n 27) 0 1---n--- 0 111111111 protection switch acknowledge 0 001100 0 11111111 protection switch release 0 010011 0 11111111 do not use for synchronization 0 011000 0 11111111 status 2 traceable 0 000110 0 11111111 sonet minimum clock traceable 0 010001 0 11111111 stratum 4 traceable 0 010100 0 11111111 stratum 1 tracable 0 000010 0 11111111 synchronization traceability unknown 0 000100 0 11111111 stratum 3 traceable 0 001000 0 11111111 reserved for networksynchronization 0 1000000 0 11111111 transmit node clock (tnc) 0 111100 0 11111111 stratum 3e traceable 0 111110 0 11111111 table 8 ?ds1 bit oriented priority messages rai/yellow alarm 0 000000 0 11111111 loopback retention 0 010101 0 11111111 rai-ci 0 011111 0 11111111 table 9 ?ds1 bit oriented codes reserved messages under study for maintenance 0 010110 0 11111111 0 011010 0 11111111 reserved for network use 0 001011 0 11111111 0 001101 0 11111111 0 001111 0 11111111 0 011101 0 11111111 reserved for customer 0 000011 0 11111111 0 000101 0 11111111 0 000010 0 11111111 0 011011 0 11111111 rai-ci 0 011111 0 11111111
functional description 68 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice notes: 1. c/r = 0 if dte (from user side) 2. c/r = 1 if carrier (from network side) 3. fcs: is the frame check sequence crc16 (can be disabled) polynomial = x 16 + x 12 + x 5 + 1 4. type: identify type of message (1 byte) with the following value - for pid message: 00111000 (76 byte info field) - for isid message: 00110100 (76 byte info field) - for tsid message: 00110010 (76 byte info field) - for itu-t path id: 00110010 (82 byte info field) 5. eic: identify the specific piece of equipment (10 bytes). 6. lic: identify a particular location (11 bytes). 7. fic: identify where the equipment is located with in a building (10 bytes). 8. unit: identify the equipment location with in a bay (6 bytes). 9. final field (38 bytes): - for pid message: fi to identify a specific ds3 path - for isid message: port number to identify the port number of the equipment that initiated the idle signal. -for tsid message: gen nnumber to identify the signal generator that initiated the test signal. table 10 ?data link format bit bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 flag0111 1110 sapi 0 0 1 1 1 1 c/r 0 ea tei 0 0 0 0 0 0 0 1 ea control 0 0 0 0 0 0 1 1 76 or 82 bytes information field type (1 byte) eic (10 bytes lic (11 bytes) fic (10 bytes) unit (6 bytes) final field (38 bytes) fcs-16 2 -8 2 -15 2 -0 2 -7 during a microprocessor access to a pmon register, an internal clock transfer signal is generated to transfer the internal count value to the holding registers. once this transfer is made the internal counter is reset until the next interval. in this way, error events occurring during the reset period are not missed. to preempt an overrun condition, whenever a counter-to-holding-register transfer occurs, an interrupt is generated (unless masked). however, if the holding register is not read since the last interrupt, an overrun will occur and the overrun status bit in the corresponding register will be set. 1.1.3.10.8 terminal-to-terminal path maintenance data link the three c-bits in m-subframe 5 may be used as a 28.2 kbit/s terminal-to-terminal data link for path maintenance data. data link protocol follows a subset of the lapd specification (recommendation q.921) with three messages defined (others are ignored): messages shall be transmitted cont inuously at a minimum rate of once per second (when no message is transmitted, the data link contains the repeated idle pattern (?0 1111110?). the transmitting terminal must perform zero stuffing to avoid flag pattern occurrence between opening and closing flags (equipment in receives path must suppress extra 0s). if the full length of an information field is not needed (or if the field is not used), the ascii null character shall be used to indicate the end of the string. the rema ining bit positions of the data field can contain any combination of 1s and 0s. at any time, the abort code can be also sent. a carrier may use this data link for the provisioning or maintenance of the ds3 facility or network. that may cause interrup- tions, delays or reduction of throughput on the data link. however, that should not affect the timely transmission of the messages. if not used, the three bits shall be set to 1.
functional description 69 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.1.3.10.7 data link receiver the rdl block first searches for the flag characters before identifying the first byte of data where the rdl block then removes the stuff bits, calculates the crc-ccitt frame check sequence (fcs), and then stores the framed data into a 4-level fifo buffer. the rdl buffer has an associated control buffer, which will indicate data ready, flag detected, end of message (eom) and overrun (ovr) status to maintain the rdl. in an eom condition, the status register also indicates the fcs status and the number of valid bits in the last data byte of the message. an interrupt will be generated not only when the fifo reaches a programmable threshold, but also when an abort sequence, fifo overrun, or terminating flag sequence are detected. 1.1.3.10.8 data link transmitter the xdl transmitter is designed to provide a serial path for hdlc data in c-bit parity applications. the xdl transmitter, will automatically perform data serialization, crc generation, bit-stuffing, flag generation, idle sequence, and abort sequence. the xdl transmitter performs all of the necessary signaling to maintain the channel. an interrupt is provided so that a double buffered transmit data register remains full for the duration of the message. the xdl at the end of the frame will automatically calculate the crc-ccitt fcs if enabled. once the frame is complete the xdl will transmit idle codes until the following frame begins. should an underrun condition occur, the xdl transmitter will automatically transmit an abort sequence and notify the controlling processor via the xdl status register udr status bit. an underrun occurs when, the controller does not write a word to the transmit data register before the previous byte has been transmitted. also, at any time, an abort sequence can be conti nuously transmitted by setting the abt control bit in the xfdl tsb configuration register (0x20). the xdl can also be enabled to continuously transmit a flag character ?01111110.? the data flow s equence for the xdl works as such: 1. step 1 continues until the all bytes for the frame are written. 2. transmit data bytes are written to the transmit data register. 3. the xdl prepares the byte by performing a serial-to-parallel conversion of the byte. 4. an interrupt is generated to signal the controller to write the next byte. 5. after the last byte is written to the transmit data register, the eom bit in the xdl configuration register should be set or the tdleomi pin should be set to indicate the end of message. 6. the xdl sends the last data byte and then the crc word is sent (if enabled) or a flag (if crc is not enabled). 7. once complete, the flag character is sent. to prevent unintentional transmission of abort or flag characters, if more than five consecutive ones exist in the raw transmit data of in the crc data, a zero is stuffed into the serial data output. the data link section provides additional information about the data link function. 1.1.3.11 ds3 loopback the ds3 can be looped back on the line level (asked by remote equipment via feac message or local host decision). however, no remote ds3 payload loopback is defined. in both these cases, transmit and receive clocks can be of a different frequency (independent clocks). in that case, a slip buffer must be provided in order to manage the discrepancy between the incoming and outgoing data streams. when the slip buffer underrun (transmit clock faster than receive clock) or overflow (transmit clock slower than receive clock) an alarm is gener- ated (these events must also be counted). for more information on the loopback capability see the loopback section. 1.1.3.12 jitter jitter is the short-term variations of digital edges from their ideal positions in time. short-term variations are phase oscillations of frequency greater than 10hz (variations at frequency under 10 hz are defined as wander). jitter amplitude is measured in unit intervals (ui) where one ui is the phase deviation of one clock period. figure 6 jitter definition t 0 1 ui 0.5 ui t j 6143 drw55
functional description 70 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 7 maximum jitter tolerance on dsn interface inputs table 11 ?max jitter tolerance on ds if cat ii data rate (mbit/s ui (ns) jitter amplitude a0 (ms)* a1 (ui) a2 (ui) filter frequencies f 0 (hz) f 1 (hz) f 2 (hz) f 3 (hz) f 5 (hz) 1.544 648 18 10 0.3 1.2 x 10 -5 10 192.9 6.43 40 78.9 2.63 20 669 22.3 300 f 0 f 1 f 2 f 3 f 4 a 2 a 1 a 0 frequency amplitude peak-to-peak (ui) slope = -20db / decade shorter the interval measurement, the higher the ?real time jitter? wander jitter 6143 drw54 there are several kinds of jitter measurement: ? jitter tolerance (gr-499-core 7.3.1): minimum jitter at the input of equipment that results in more than two errored seconds in a 30-second interval. ? jitter transfer (gr-499-core 7.3.2): ratio of (amplitude of equipment output jitter) / (applied input jitter). ? jitter generation (gr-499-core 7.3.3): added jitter by the equipment or chip. there also exists two categories of jitter: ? category i: when the correspondent line does not physically exists. ? category ii: when the line physically exists. 1.1.4 ds3 framer ? to liu interface 1.1.4.1 if ds3 framer ? ds3 liu the interface between a ds3 liu and a ds3 framer depends on which device is performing the line coding / decoding function: ? if the line encoder / decoder is in the liu: signals follow single rail configuration. ? if the line encoder / decoder is in the framer: signals follow dual rail configuration. 1.1.4.1.1 dual rail configuration (bipolar mode) ? rx3clk (input): 44.736 mhz clock with duty cycle between 40 and 60 %; clock used to sample (on positive or negative edge: user- selected edge) rx signals. ? rx3pos (input): positive pulse received on the b3zs-encoded line. ? rx3neg (input): negative pulse received on the b3zs-encoded line. ? tx3clk (output): 44.736 mhz clock with duty cycle between 40 and 60%. this clock is used to sample (user-selected edge) all the tx signals. ? tx3pos (output): positive pulses that must be sent on b3zs encoded line. ? tx3neg (output): negative pulses that must be sent on b3zs encoded line. 1.1.4.1.2 single rail configuration (unipolar mode) ? rx3clk (input): 44.736 mhz clock with duty cycle between 40 and 60%. this clock is used to sample (user-selected edge) all the rx signals. ? rx3d (input): logical incoming data stream received on b3zs-encoded line. ? rxlcv (input): line code violation detected on b3zs-encoded line. ? tx3clk (output): 44.736mhz clock with duty cycle between 40 and 60%. this clock is used to sample (user-selected edge) all the tx signals. ? tx3d (output): logical data that must be encoded and sent by the ds3 liu. txmfp (output): m-frame pulse sync hronization signal that must be high during one bit time (the first of the m-frame (x1).
functional description 71 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.2 m23 multiplexer figure 8 m23 mulitplexer block fifo tdat b3zs encoder ds3 framer 1:7 fifo ds2 ds2 external oh m23 / c-bit mode oh stuffing rdat b3zs decoder ds3 framer 1:7 6143 drw 31a external oh status ds2 ds2 to multiplex 7 ds2 signals into a formatted ds3 signal (respectively, to terminate a framed ds3 and to generate 7 independent ds2 signals). the m23 function is not activated when the m13 is used in an unchan- nelized mode. when the m23 function is used, the ds3 formatted data stream (but not framed) is made by taken one bit from each ds2 data streams in a round robin fashion.
functional description 72 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 9 ds3 stuff block 6143 drw19a f4 f4 f4 f4 f4 f4 info bit 84 info bit 84 info bit 84 info bit 84 info bit 84 info bit 84 info bit 84 ??? ??? ??? ??? ??? ??? ??? m1 sub-frame m2 sub-frame m3 sub-frame m4 sub-frame m5 sub-frame m6 sub-frame m7 sub-frame info bit 1 info bit 1 info bit 1 info bit 1 info bit 1 info bit 1 info bit 2 info bit 2 info bit 2 info bit 2 info bit 2 info bit 2 info bit 3 info bit 3 info bit 3 info bit 3 info bit 3 info bit 3 info bit 4 info bit 4 info bit 4 info bit 4 info bit 4 info bit 4 info bit 5 info bit 5 info bit 5 info bit 5 info bit 5 info bit 5 info bit 6 info bit 6 info bit 6 info bit 6 info bit 6 info bit 6 info bit 7 info bit 7 info bit 7 info bit 7 info bit 7 info bit 7 info bit 8 info bit 8 info bit 8 info bit 8 info bit 8 info bit 8 info bit 8 stuff bit 2 stuff bit 3 stuff bit 4 stuff bit 5 stuff bit 6 stuff bit 7 stuff bit 3 f4 1.2.1 stuffing 1.2.1.1 description the seven ds2 are asynchronous relative to each other and there- fore may be operating at different rate. bit stuffing adjusts the different incoming rates. the stuff opportunity bit position exits in the last block of each ds3 m-subframe to adjust the transmission rate of each ds2 stream independently (just one bit stuffing opportunity per ds2 and per ds3 m-subframe). the signal data rate limits are: ? maximum data rat: 6.3157mbit/s (more than 6.312 m/bits 20 ppm) ? minimum data rate: 6.3063mbit/s (less than 6.312 m/bits 20 ppm) stuffing indication bits are the c overhead bits, 3 c bits for each ds2 (ci1, ci2, and ci3 for ds2-i) if 2 or 3 c-bits are ?1?s, the bit in the correspondent stuffing position is a stuff bit (either 0 or 1): if zero or one c-bit equals, ?1?, the bit in the stuffing position is a data. 1.2.1.2 stuffing strategies 1.2.1.2.1 on receive line adaptation the number of real stuffing bits inserted in transmission is equal to the number of real stuffing observed in reception. it is called loop-timing mode. 1.2.1.2.2 m23 mechanism as each ds2 signals can be considered asynchronous, the host must be able to give each ds2s the stuffing speed for transmission. the range of each ds2 data rates is: ? if zero stuff: 6.31567 mhz (6.312 mhz 581 ppm). ? if full stuff: 6.306272 mhz (6.312 mhz 907 ppm). a particular case is the nominal stuff (ds2 signal frequency equal to 6.312 mbit/s). to multiplex such a ds2 in one ds3 signal, the host must program the stuffing speed at a special value that corresponds to a 39.06 % stuffed m-frames (for the particular ds2). as the ds2 level is most often a transition between ds1 and ds3 signals, it is possible to use always the m23 mode with a fixed stuff: zero stuff, full stuff or nominal stuff. 1.2.1.2.3 c-bit parity mechanism in this mode, the decision is a full stuff: each stuffing bit opportunity (for all the ds2) in all ds3 m-frames contains a stuff except when the ds3 signal is unchannelized. in this case, it is possible to have a c-bit parity mode with a null stuff strategy. c-bits are not used for stuffing indi- cation (always full or zero stuff): they can be used for others purposes presented in ds3 framer chapter.
functional description 73 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.3 ds2 framer figure 10 ds2 framer block figure 11 ds2 frame fifo ds2 ds2 framer 1:4 fifo tx1 tx4 g.747 or ds2 mode oh stuffing ds2 ds2 framer 1:4 6143 drw 32a oh rx1 rx4 stuffing m1 m2 m2 x c1 c1 c1 c1 f1 f1 f1 f1 c2 c2 c2 c2 c3 c3 c3 c3 f2 f2 f2 f2 48-bits m sub-frame m frame 294 bits 6143 drw20 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits 48-bits stuff block the nominal ds2 interface rate is 6.312 mbit/s 33 ppm ( 208 bit/s). then ds2 framer function is not activated when unchannelized ds3 is initalized. ds2 signal is a combination of four ds1 signals. a ds2 m-frame is composed of four ds2 m-subframes. moreover, each m-subframe contains six blocks of 48 payload bits (bit-interleaved from the four ds1 streams; made by m12 function) plus 1 overhead bit (the four subframes do not represent each separate ds1 signals). the ds2 frame contains 1176 bits (1152 pay load bits 24 overhead bits) and the period is 186.31ms. the ds2 framer can also be used to frame g.747 bit streams. in this case the nominal ds2 rate is 6.312 mb/s multiplexed from three tributaries of 2.048 mbit/s.
functional description 74 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 12 g.747 frame format 1 set 1 set 2 set 3 set 4 g.747 nominal ds2 rate 6312kbit/s multiplexing three tributaries of 2048 kbit/s nominal ds3 rate 44.736mb/s multiplexting seven tributaries of 6,312kbits/sec 6143 drw21 set 5 110100000 ais c11 c12 c13 par c21 c22 c23 rev c31 c32 c33 stuff 1 stuff 2 stuff 3 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 parity = 1 odd parity = 0 even rev reserved, should be set to 1 cji (j = 1,2,3 i = 1,2,3) indicates the ith justification control bit of the jth tributary stuff (j) : stuff bit for the jth tributary positive justification = 111 (majority decision) no justification = 000 (majority decision) bit 167 1.3.1 reframing 1.3.1.1 procedure the search of frame alignment must be activated in three cases: ? after a reset. ? when the microprocessor forced the reframing process. ? after an internal out of frame (oof) declaration (but reframing asked by microprocessor). when a ds2 reframing is in process, all- ones ais signal is sent downstream for the duration of the reframing. 1.3.1.2 max time the standard indicates a maximum average framing time of 7ms to resynchronize the incoming data flow (time necessary to check every bits of a structure before declaring frame synchronization). this time is significant only if neither mimic patte rn (data payload that simulate? a frame alignment pattern) nor other tr ouble (like errors) is present inside the incoming data flow. 1.3.2 alarms and errors 1.3.2.1 oof out of frame is declared when n out of m consecutive framing bits are in error (n = 2 and m = 4 or 5). optionally, the oof detection can take into accounts one or more m-bits in error in 3 or 4 consecutive m-frames. if configured, during ds2 oof, an all-ones ais signal is sent downstream to all concerned ds1s. otherwise the payload extracted with the previous frame alignment is transmitted downstream because it is an off-line framer. oof defect is terminated when the signal does not contain any more framing bits (f-bits and m-bits) error in several consecutive frames (1 m-frame or more). defect detection / termination must be done in less than 10.5 ms (1.5 x mart). 1.3.2.2 lof lof failure is declared if oof defect is present for 2.5 0.5 seconds except when a ds2 ais defect is present or ds2 ais failure has been declared. lof is cleared if no error has been detected in 10 0.5 seconds.
functional description 75 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.3.2.3 ais ais defect is declared when at least one of the three following condi- tions (it should be detected in less than 10.5 ms = 1.5 x mart.) is true: ? incoming signal with more than 99.9% of ones density (unframed all-ones signal = ais from upper level). (incoming signal with unfram ed condition (ds2 los or oof). ? host command. the insertion of ais (same for the ais removal) in the downstream signal has to be made in less than 0.7 ms (0.1 x mart) ais failure is declared if an ais defect is present for 2.5 0.5 seconds and is cleared if ais a defect is absent for 10 0.5 seconds. the activation of an ais failure must not exceed 0.7 ms and a host can configure one of the two downstream transmission strategies: ? payload transmission taking with the last correct frame alignment (off-line framer). ? transmission of ais (unframed all-ones signal). 1.3.2.4 rai the rai signal (last m-bit mx) is transmitted upon declaration of lof or ais failure for the duration of the failure (downstream failure). rai is declared when this bit presents for an in terval of 0.5 to 1.5 seconds with no more than 10 -3 ?1?s (active state is zero). similarly, the inactive state of rai signal must be sampled between 0.5 and 1.5 seconds with no more than 10 -3 ?0?s.
functional description 76 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice 1.4 g.747 applications 1.4.1 reframing 1.4.1.1 procedure the search of frame alignment must be activated in three cases: ? after a reset. ? when the microprocessor forced the reframing process. ? after an internal out of frame (oof) declaration (but reframing asked by microprocessor). when a ds2 reframing is in process, all- ones ais signal is sent downstream for the duration of the reframing. 1.4.1.2 max time for g.747 applications the ds2 framer has a maximum reframe rime of less than 1ms. in order for the fr amer to declare framing however, the candidate frame alignment signal mu st be present for 3 consecutive frames in accordance with ccitt rec. g.747 section 4. once in frame the ds2 framer will provide frame boundary indications as well as overhead bit positions. 1.4.2 alarms and errors 1.4.2.1 oof for alarm indications the ds2 fr amer is designed to indicate oof conditions when 4 consecutive frame alignment signals are incorrect in accordance with ccitt rec. g.747 section 4. much like the ds3 framer, the ds2 framer is an "off-line" framer and will continue to indicate errors when oof based on the previous frame alignment. 1.4.2.2 ais in g.747 applications the ds2 framer also uses an integration algorithm with a 1:1 slope to detect red alarm and ais. instead of using ds2 frames however the ds2 framer uses g.747 frames with the integrator counter. ais is defined as the occurrence of less than 9 zeros while the framer is oof during that g.747-frame. red alarm is defined as the detection of a red defect, or oof in an m-frame. for each interval, a g.747 frame, if the framer detects a red defect or ais event, the integrator counter is incremented. accordingly, if a valid g.747 frame is received then integrator counter is decremented. as a result the ds2 framer can detect red alarm and ais in 6.9ms. 1.4.2.3 rai the ds2 framer also extracts the ds2 x-bit and g.747 remote alarm indication bit, rai, to indicate a far end receive failure, ferf. the ds2 framer uses an internal status fifo to insure that for an oof condition, nearly 100% of the time for ds2 applications and 99.9% of the time for g.747 applications, that the ds2 framer will freeze in a valid state. if two successive x-bits or rai bits are the same, then a ferf status is indicated and entered into the internal status fifo. each m-frame or g.747 frame the status fifo will be updated and shifted. after a total of six m-frames or g.747 frames, the error condition will reach the sixth (last) position of the fifo. when the error condition reaches the last position in the fifo, the ds2 status register will be updated to indicate to the controller that a ferf has occurred. the error indication/value will be held in that sixth(last) position while the fifth through second positions will freeze the ferf state of the four m-frames following the ferf condition. the first position of the status fifo will contain the present ferf state and will be continually updated with the present ferf status. once correct frame alignment has been reestab- lished and the oof condition is gone, then the first fifo status location will have a valid indication. at this point the fifo will continue to operate normally, by shifting the ferf status through the fifo.
functional description 77 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 13 m12 block fifo ds2 ds2 framer 1:4 fifo tx1 tx4 g.747 or ds2 mode oh stuffing ds2 ds2 framer 1:4 6143 drw 32a oh rx1 rx4 stuffing 1.5 m12 to multiplex 4 ds1 signals into a formatted ds2 signal (respectively, to terminate a framed ds2 and to generate 4 independent ds1 signals). the m12 can also multiplex/demultiplex three e1 (2.048 mbit/s) streams into a g.747 formatted 6.312 mbit/s serial stream. the m12 function is not activated when unchannelized ds3 initialized. 1.5.1 actions on the four multiplexed ds1 bit-streams the ds2 data stream is built by taking one bit from each of the four ds1 data streams in a round robin fashion. however, the second and fourth ds1 signals must have their all bits inverted. 1.5.2 stuffing 1.5.2.1 mechanism the four ds1 are asynchronous relative to each other and may be operating at different rates. bit stuffing is used to adjust the different incoming rates. stuff opportunity bit position exists in the last block of each ds2 m-subframe to adjust the transmission rate of each ds1 streams independently (just one bit stuffing opportunity per ds1 and per ds2 m-subframe). stuffing indicator bits are the c overhead bits, 3 c?bits for each ds1 (ci1, ci2 and ci3 for ds1-i). if in these three bits there are 2 or 3 ?1?s, the bit in the stuffing position is stuff (value not specified: either 0 or 1); if there are 0 or 1 ?1?, the bit in the stuffing position is a data.
functional description 78 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 14 ds2 stuff block 6143 drw20a f2 f2 f2 f2 info bit 1 info bit 1 info bit 1 info bit 2 info bit 2 info bit 2 info bit 3 info bit 3 info bit 3 info bit 4 info bit 4 info bit 4 info bit 5 info bit 5 info bit 5 info bit 5 info bit 48 info bit 48 info bit 48 info bit 48 ??? ??? ??? ??? m1 sub-frame m2 sub-frame m3 sub-frame m4 sub-frame stuff bit 3 stuff bit 2 stuff bit 1 stuff bit 4 1.5.2.2 stuffing strategies 1.5.2.2.1 on receive line adaptation the number of real stuffing bits inserted in transmission is equal to the number of real stuffing observed in reception. this mode is also called per?t1 loop timing. in this mode, the system must free run under trouble condition at 1.544 mbit/s 200 bit/s (1.544 mbit/s 130 ppm). such a mode seems to be used only if remote loopback (line or payload) is activated. 1.5.2.2.2 adaptive frequency as each ds1 signal comes from its own source (asynchronous), the host processor must be able to give for each ds1 the stuffing speed for transmission in order to adapt the ds1 data rates independently. an external reference has to be used to synchronize the ds1 signals (this reference is also called building integrated timing source, bits). such a reference can come from one ds1 received data stream (line-timing mode) or from an external reference such as gps for example (external reference mode). in reception, each ds1stuffing ratio must be esti- mated. however, the real time stuffing value depends on the mode used to multiplex ds2s into a ds3 signal: ? if m23 mode, every ds1 signal works at its own speed. (near the nominal stuffing value if m23 st uffing programmed near the nominal value for example). ? if c-bit parity mode, ds1 stuffing value must be under the nominal value (less stuff) due to the full stuff processing when ds2 signals are multiplexed into the ds3 formatted signal. 1.5.2.2.2.1 ds1 nominal stuffing value if m23 mode used between ds2 and ds3 level the per-ds1 in a ds2 signal (6.312 mbit/s) data rate limits are: ? maximum data rate: 1.5458 mbit/s (more than 1.544 mbit/s 20 ppm). ? minimum data rate: 1.5404 mbit/s (less than 1.544 mbit/s-20 ppm). the nominal stuffing ratio is 33.46 % of stuffed frames (if ds2 at nominal data rate). 1.5.2.2.2.2 ds1 nominal stuffing value if c-bit parity mode used between ds2 and ds3 level the per-ds1 in a ds2 signal (6.306 mbit/s) data rate limits are: ? maximum data rate: 1.5444 mbit/s (more than 1.544 mbit/s 20 ppm). ? minimum data rate: 1.5390mbit/s(less than 1.544 mbit/s-20 ppm). the nominal stuffing ratio is 7.41% of stuffed frames. 1.5.3 oh insertion during the muxing process the m12 mux also inserts x, f, m and c bits. 1.5.4 per ds1 payload loopback the m12 multiplex should loopback the ds1 signal if it detects that ci3 bit is the inverse of ci1 and ci2 bits (i defines the concerned ds1). it is necessary to repeat this information at least 10 times. more information on the loopback modes are provided in the loopback section of the data sheet.
data link 79 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 15. xfdl reg 20 reg 21 xfdl control tdl int tdr udr tdl eom reg 22 data parallel-to-serial crc - gen zero stuff mux pmdl_out 6143 drw37 parallel-to-serial parallel-to-serial parallel-to-serial parallel-to-serial zero stuff internal data link transmitter: the transmitter data link confi guration register and the transmit data link control register are the two main registers used for control- ling the transmit data link function in the m13. after reser, xfdl is disabled because the en bit in the tsb configuration register will be 0. the inte bit, also in the xfdl tsb configuration register, should be set so that the tdlint output is masked. when a frame is ready to be transmitted, the xfdl tsb should be configured accordingly. if the ccitt-crc frame check sequence is de- sired this should be enabled. then the inte bit should be enabled (if in the interrupt driver mode), and then finally the en bit is set to 1 enable the overall operation of the xfdl. the xfdl can be run in three different modes: polled, interrupt driven, and dma-controlled. in the polled mode, the tdlint and tdludr out- put of the xfdl are unused and the microprocessor must periodically poll (read) the xfdl status register to determine when to write the next byte to the transmit data fifo. in the interrupt driven mode, the micropro- cessor will use the tdlint pin as an interrupt pin to determine when the transmit data fifo is ready for the next data byte. in the dma controlled mode the tdlint output acts as a dma request to the dma controller while dma end signal feeds the tdleomi of the m13. in an under run condition the tdludr drives an interr upt on the controlling microproces- sor.
data link 80 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice polled mode: in the polled mode the controlling microprocessor will periodica lly initiate a service routine to complete the following. 1) read the xfdl status reg. 2) if udr = 1 clear the status register by setting udr = 0, de-asserting tdleomi input pin and clearing eom. restart the curr ent frame. 3) if intr = 1 then a) write next data byte to xfdl tsb data reg. b) set eom = 1 and inte = 0 or assert tdleomi input pin. 4) repeat steps 1 an 2 to confirm no underrun occurred during step 3. figure 16. xfdl polled mode x tdlint tdleomi 0x21 0x22 xfdl tsb int status xfdl tsb tx data x tdludr 6143 drw42 82v8313
data link 81 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice interrupt driven mode: in the interrupt driven mode the microprocessor will service the m 13 when the xfdl is ready to accept another byte or when an u nderrun condition occurs. the isr will be the same as described above. figure 17. xfdl interrupt mode figure 18. xfdl interrupt service routine 6143 drw42a xfdl tsb tx data reg ready for new byte new byte written to xfdl tsb tx data register 0x25 0x26 xfdl tsb int status xfdl tsb tx data x tdlint tdleomi x tdludr 82v8313 6143 drw42b read xfdl tsb int status udr status clear status reg udr = 0 deassert tdleomi clear eom = 0 write data to xfdl tsb data reg or set eomi in xfdl config reg. if int = 0 or assert tdleomi pin & inte = 0 int = 0 udr = 1 int = 1
data link 82 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice dma mode: when a dma controller is used with the xfdl, the tdlint will initiate a dma request and consequently the dma controller will se nd a byte to the m13. for each assertion of the tdlint the dma controller should s end a byte. once the last byte is sent from the dma controll er to the m13, to finish the request, the dma controller should assert the tdleomi when the dma controller sets tdleomi high, the eom bit in the xfdl configura- tion register will be set to complete the transaction. if an un derrun condition occurs the tdludr will interrupt the microproc essor and will stop dma controller, clear the condition, reset any necessary dat a pointers, and restart the dma to resend the data frame. figure 19. xfdl dma mode 6143 drw41 tdludr tdlint tdleomi dma reg int microprocessor end 82v8313
data link 83 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 20. xfdl normal data sequence flag byte 1 byte 2 byte n c1 c2 flag byte 1 inte byte 1 byte 2 byte 3 byte 4 eom inte inte byte 1 byte 2 byte 3 serial rfdl data tdlint d7-0 6143 drw48 xfdl normal data sequence: this example shows a normal xfdl interrupt driven sequence with the crc enabled. in order to begin the sequence the microprocessor must first set the inte bit in the xfdl c onfiguration/control register to enable the tdlint interrupt. once the interrupt is enabled the m13 will assert the tdlint to interrupt the microprocessor. the interrupt routine de- scribed above will cause the microprocessor to write the first data byte of the frame to the transmit fifo. once the byte is written to the fifo, the tdlint will de-assert. when the xfdl begins to transmit the first byte, tdlint will assert again to signal that it is ready for the next byte in the frame. again the microprocessor will enter the xfdl isr and load the data byte in to the fifo. again the tdlint will de-assert when it begins to transmit that data byte. this process continues until the last byte of the frame. once the last data byte begins to transmit, the tdlint will be as- serted, as normal. since all of the data has been written to the fifo the isr should set the eom bit (or assert the tdlemi pin) to end the frame. also, the inte bit should be set to 0 so that the tdlint interrupt is dis- abled and the crc bytes and the closing flag are transmitted. when new data for the next frame is ready, the tdlint can be re-enabled by setting the inte bit to 1, and thus beginning the sequence over again.
data link 84 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 21. xfdl underrun sequence flag byte 1 byte 2 abort flag byte 1 byte 2 byte 3 inte byte 1 byte 2 byte 3 udr byte 1 byte 2 serial xfdl data tdlint tdludr byte 3 byte 3 byte 4 inte inte d7-0 6143 drw 49 xfdl underrun sequence: this example is also an interrupt driven example, but shows the xfdl inputs and outputs during and underrun error. similar to the last example, the microprocessor begins by setting the inte bit in the configuration/control register to 1 thus enabling tdlint interrupts. the tdlint is asserted and the microprocessor enters the interrupt routine to write the first data byte to the transmit fifo. once the byte is written to the fifo, the tdlint is de-asserted. as with the previous example, once the xfdl begins to transmit the data, the tdlint will be asserted to start the next isr transmit data write sequence. when d3 begins to transmit the tdlint is asserted and the interrupt routine should be started. for some reason, the routine was not able to write to the transmit fifo within five rising clock edges, so the transmit data link underrun pin, tdludr, is asserted. once the tdludr is asserted, an abort followed by a flag is automatically sent out on the data link. the xfdl is stopped, the udr bit is set, and the m13 must be serviced by the microprocessor. the udr bit should be cleared and the inte bit should be set to 0. once this is done, the frame can be restarted again by setting the inte bit to 1.
data link 85 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 22. tdlint timing normal data tx 6143 drw52 tdlint wrb (byte write to xfdl fifo) tdludr missed write byte write to xfdl fifo min 216 s max 311 s min 216 s max 311 s min 216 s max 311 s <110 s sec <110 s sec tdlint timing normal data transmission: this figure shows the timing requi rements for the microprocessor to adequately service the transmit data link fifo. each byte of the packet must be written within 110 sec of the rising edge of the tdlint without causing an underrun. the time from rising edge to rising edge of tdlint is a result of the variation in time to transmit the data link byte over the 3 c-bits of the 5th m-subframe over multiple m-frames, and for the m13 to latch in the next byte. as shown above, the third byte write to the xfdl fifo is missed and thus the tdludr goes high when it was supposed to transmit that third byte.
data link 86 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 23. tdleomi timing eomi after crc 6143 drw50 first byte of next frame latest deassertion tdlint wrb byte write & xfdl fifo tdleomi min 216 s max 311 s <210 s last byte & crc 850 s flag ?01111110" <110 s tdleomi timing: the transmit data link end of message indicator, tdlemoi, is used to indicate to the xfdl block that the last byte of the frame has been writ- ten to the xfdl transmit data register. when tdleomi has been as- serted, the xfdl will insert the fcs, if enabled, and flags (?0 1111110?) after the last byte has been transmitted. to aid designers, the m13 can accept a wide range of timing for the tdleomi. the above diagram will help illustrate this broad range. at the earliest, the tdleomi can be as- serted synchronously with the falling edge of the write strobe that is used to write the last data byte to the xfdl transmit fifo. at the latest, td- leomi must be asserted before the next rising edge of tdlint, when the xfdl would expect the next data byte to be written to the xfdl transmit fifo (210 sec). for de-assertion a similar logic applies and the earliest tdleomi can be de-asserted would be just after the rising edge of the tdlint that registered the tdleomi. at the latest, tdle- omi must be de-asserted before the write of the first byte of the nest frame. if tdleomi is still high when tdlint goes high, that byte will be considered that last byte and thus the crc bytes and flag bytes will au- tomatically be transmitted on the data link in the above diagram, tdlemoi is shown going high synchro- nously with the write strobe but can be asserted any time up to 210 sec after the rising edge of tdlint. tdlemoi is de-asserted before the end of the second crc byte (or before the flag transmis- sion). in this example tdlint is still active and remains high while waiting for the first byte of the next frame to be written to the xfdl transmit fifo. in this example, it is important to note that the tdludr is not asserted. in this situations, no underrun can occur since it is the first byte of the frame. however, once the first byte is written, the xfdl fifo must be serviced regularly to prevent an underrun condition. as noted previously, tdleomi must be glitch free. if tdlemoi is not used, it can be tied to ground or held low. in this case, the eom bit can be used and the same restrictions that apply to the tdleomi apply to the eom bit. it is strongly recommended that the interrupt routine described in this data sheet be used.
data link 87 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 24. rfdl reg 24 reg 25 reg 26 fifo zero destuff serial to parallel data out 6143 drw38 rfdl control rdl int rdl eom internal data link receiver: like the data link transmitter, the data link receiver should be disabled at start up by setting the en bit in the rfdl configuration register. before initiating the rfdl, the fifo depth for generating an interrupt should be set by writing to the rfdl interrupt control/status register. by setting the en bit in the configuration register to 1, the rfdl will be enabled and assumes the link will be idle (all ones). immediately after enabling the rfdl however, the rdfl will begin searching for flags. when the first flag is found, an interrupt will be generated and the data byte found before the flag will be written to the fifo. when an interrupt is generated the rfdl control block guarantees that the flg and eom bits will also be written to the status register reflect the current state. after the interrupt is generated the data should be read out and eom should be logic 1 and the flg bit logic 1. it is important to note that after the rfdl is enabled (en = 1 or tr = 1) the rfdl will generate an interrupt to indicate the status of the link. as a result, the first data byte read should be discarded. the m13 is designed as a passive rfdl, any link state in the form of boc, idl, active flags, or other indi- cations should be handled by t he controlling microprocessor. much like the xfdl, the rfdl can be run in a polled, interrupt driven, or dma controlled mode. in the polled mode the rdlint and rdleom outputs are not used and the microprocessor must periodically read (poll) the status register to determine when to read the data. in the interrupt driven mode the m13 will generate an interrupt via rdlint pin to indicate to the microprocessor that data is ready to be read. in the dma controlled mode the rdlint and rdleom are used as a hard- ware handshake to initiate, indicate and terminate the dma.
data link 88 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 25. rfdl polled mode x rdlint 0x25 0x26 rfdl tsb int. cnt/status 0x27 6143 drw 39a rfdl tsb status rfdl tsb receive data x rdleom 82v8313 polled mode: in the polled mode the controlling microprocessor will periodically initiate a service routine and complete the following: 1) read the rfdl data register 2) read the rfdl status register 3) if the fifo has underrun (0x00) then discard byte and wait for the next period/interrupt. 4) if the fifo has overflowed (ovr = 1) then discard the last frame and wait for the next period/interrupt. 5) if flg = 0 (i.e. abort) and the link was active discard the byte and wait for the next period/interrupt. 6) if flg = 1 and the link was inactive, then set the link to active, discard the byte and wait for the next period/interrupt. 7) save the byte. 8) if eomr = 1, then check the crc, nvb and process the frame 9) if fe = 0, then go to step 1, else wait for next period/interrupt. steps 1 and 2 may be reserved to avoid reading the data register unneccessarily.
data link 89 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 26. rfdl interrupt driven mode figure 27. rfdl interrupt service routine 6143 drw 39b 0x25 0x26 rfdl tsb int. cut/status 0x27 rfdl tsb status rfdl tsb receive data rdlint rdleom 82v8313 discard last frame = 1 = 1 = 0 = 1 = 0x00 ! = 0x00 = 0 = 1 wait for interrupt read rfdl data reg read status reg check ovr check flg save byte check eomr check fe check crc, nvb process the frame set link to inactive discard data set link to active = 0 6143 drw40 interrupt driven mode: in the interrupt driven mode the microprocessor will service the m13 when the rfdl indicates when a data byte is ready or when an error condition occurs. the isr will be the same as with the polled condition described above. the above flow (steps 5 and 6) assumes that the link state is stored as a local variable. this is done to determine if the link state inactive, receiving all ones or boc which contains all ones sequences, or active and thus receiving data and flags.
data link 90 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 28. rfdl dma mode dma request int microprocessor rdleom rdlint 6143 drw 39 82v8313 dma mode: the rfdl can also be used with a dma controller. in this case the rdleom of the m13 is connected to the interrupt pin of the micro- controller. the rdleom is also routed to a gate, with the rdlint, which will inhibit a dma request if the rdleom output is high. in this way, if the rdleom is low, the rdlint will control dma requests. when the dma controller reads the last byte (eom or abort) or an overrun condition occurs the rdleom output goes high the dma controller will be inhibited from reading more bytes and the processor is interrupted. when the processor takes over, the dma can be halted and readied for the subsequent frame, and the frame processing initiated.
data link 91 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice figure 29. rfdl normal data and abort sequence (1) eom abort eom rdlint rdleom d7-0 byte 1 data reg read 6143 drw46 byte 2 data reg read byte n-3 data reg read byte n-2 data reg read byte n-1 data reg read byte n data reg read byte b1 read from data reg byte b2 read from data reg byte b3 read from data reg byte 1 data reg read flag byte 1 byte 2 byte 3 byte n-1 byte n r c1 c2 flag byte 1 r abort serial rfdl data b1 b2 b3 b1' rfdl normal data and abort sequence: the above diagram shows the relationship between the incoming and extracted data link data and the rdlint, rdleom, and micropro- cessor bus. to simplify the examples each microprocessor access is a composition of multiple accesses following the recommended handling sequence, where each incoming data byte of the farme is ?handled? (read) in turn. as can be seen there is a short delay from the incoming data to rdlint going high. it can also be seen that rdlint will both be de-asserted until the microprocessor reads the data byte from the rfdl data register. the assert/de-assert sequence is followed through the entire farme until byte (n-2) when multiple bytes exist in the buffer. in this case it can be seen that the rdlint is not de-asserted. at the end of an interrupt sequence the controlling microprocessor should realize that the interrupt has not been completely cleared and thus re-enter the isr. at byte (n-1) the interrupt is cleared and the rdlint is de- asserted. in a data link frame, it is not necessary to have an integral number bytes. in the above example, this is one of those cases. the ?r? represents the non-integral bits that remain at the end of the frame. the internal rfdl block will take in the remainder and the crc and also register those into the rfdl data register. in this example b1 will contain the remainder of the farme dat a and the first part of the first byte of crc data. b2 will contain the second part of the first byte of the crc data plus the first part of the second byte of the crc data. and finally, b3 will contain only the second part of the second byte of the crc data. when the status register is read for b3, the eom bit in the rfdl status register will also be set to indicate the end of the current frame (end of message --eom). the rfdl block parses data on byte boundaries until the rfdl receives the end flag. the rfdl block will indicate the size of the remainder by setting the nvb (number of vaild bits) in the rfdl tsb status register (0x26). the nvb information can be used by controlling microprocessor to properly parse, check, and handle the data. in the above example, after b3 is read a new frame is started. shortly after it starts, it is aborted. the microprocessor first reads byte 1 and then reads the b1 byte. when b1 is read the status register will indicate flg bit and eom bit meaning all bytes up to the abort should be read.
data link 92 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
functional timing 93 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice functional timing: figure 30. receive ds3 oh serial stream figure 31. transmit ds3 oh serial stream figure 32. functional receive oh timing low speed rohclk roh rohfp 6143 drw43 x1 f1 c11 f0 c12 f0 c13 s1 x2 f1 c21 f0 c22 f0 c23 s2 p1 f1 c31 f0 c32 f0 c33 s3 p2 f1 c41 f0 c42 f0 c43 s4 m1 f1 c5 1 f0 c52 f0 c53 s5 m2 f1 c61 f0 c62 f0 c63 s1 m3 f1 c71 f0 c72 f0 c73 s7 x1 6143 drw43a tohclk (526 khz) toh tohfp tohen x1 f1 c11 f0 c12 f0 c13 s1 x2 f1 c21 f0 c22 f0 c23 s2 p1 f1 c31 f0 c32 f0 c33 s3 p2 f1 c41 f0 c42 f0 c43 s4 m1 f1 c51 f0 c52 f0 c53 s5 m2 f1 c61 f0 c62 f0 c63 s1 m3 f1 c71 f0 c72 f0 c73 s7 x1 rohclk (526khz) rmsfp (x,p,m) rohp (x,p,m,c,f) rohfo (x1) roh x1 f1 c11 f0 c12 f0 c13 s1 x2 f1 c21 f0 c22 f0 c23 s2 p1 f1 c31 f0 c32 f0 c33 s3 p2 f1 c41 f0 c42 f0 c43 s4 m1 f1 c51 f0 c52 f0 c53 s5 m2 f1 c61 f0 c62 f0 c63 s1 m3 f1 c71 f0 c72 f0 c73 s7 x1 6143 drw44
idt82v8313 3.3 volt m13 multiplexer functional timing 94 june 3, 2004 *notice: the information in this document is subject to change without notice figure 33. functional receive timing pmon figure 34. functional receive oh timing high-speed rohclk rais rlos roof (3 out of 16 f-bits) roof (3 out of 8 f-bits) rferf rdlsig rdlclk x1 f1 c11 f0 c12 f0 c13 s1 x2 f1 c21 f0 c22 f0 c23 s2 p1 f1 c31 f0 c32 f0 c33 s3 p2 f1 c41 f0 c42 f0 c43 s4 m1 f1 c51 f0 c52 f0 c53 s5 m2 f1 c61 f0 c62 f0 c63 s1 m3 f1 c71 f0 c72 f0 c73 s7 x1 x1 f1 c11 f0 c12 f0 c13 s1 x2 f1 c21 f0 c22 f0 c23 s2 p1 f1 c31 f0 c32 f0 c33 s3 p2 f1 c41 f0 c42 f0 c43 s4 m1 f1 c51 f0 c52 f0 c53 s5 m2 f1 c61 f0 c62 f0 c63 s1 m3 f1 c71 f0 c72 f0 c73 s7 x1 6143 drw44a x-2bit or p-bit or m-bit info x-bit c-bit or f-bit roclk (44.736 mhz) rodat rmfp rmsfp rohp 6143 drw45 info info info info info info
loopback modes 95 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice loopback modes:
loopback modes 96 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 diagnostic loopback for a ds3 diagnostic loopback, the transmitted ds3 stream will be looped back into the ds3 receive path and as a result the inc oming ds3 will be ignored. as a result of the incoming ds3 being ignored, the receive path will use the transmit clock instead of the rpos./r dat and rneg/rlcv. figure 35. ds3 diagnostic loopback f r m r f f f f f f mx12 #1 mx12 #2 mx12 #3 mx12 #4 mx12 #5 mx12 #6 mx12 #7 ds3 frmr ds3 tran uni mx23 ? ? ? ? ? ? rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp optional ais insertion 6143 drw60
loopback modes 97 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds3 line loopback for a ds3 line loopback, the received ds3 stream will be looped back into the ds3 transmit path and as a result the internally generated ds3 will be ignored. similar to the ds3 diagnostic loopback the transmit clock will be substituted with the receive clock. figure 36. ds3 line loopback f r m r f f f f f f mx12 #1 mx12 #2 mx12 #3 mx12 #4 mx12 #5 mx12 #6 mx12 #7 ds3 frmr ds3 tran mx23 ? ? ? ? ? ? rclk rpos/ rdat rneg/ rlcv tclk tpos/ tdat tneg/ tmfp 6143 drw61
loopback modes 98 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds2/g.747 demultiplex loopback for a ds2/g.747 demultiples loopback individual ds2 or g.747 str eams can be looped from the receive ds3 stream and be placed ba ck on the transmit ds3 stream. as might be expected, the internally generated ds2 or g.747 ds2 will be ignored. figure 37. ds2 / g.747 demultiplex loopback f r m r f f f f f f mx12 #1 mx12 #2 mx12 #3 mx12 #4 mx12 #5 mx12 #6 mx12 #7 ds3 frmr tclk tpos/ tdat tneg/ tmfp ds3 tran mx23 ? ? ? ? ? ? rclk rpos/ rdat rneg/ rlcv 6143 drw62 optional demux ais insertion ds2/g.747 tributary loopback path
loopback modes 99 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice ds1/e1 demultiplex loopback for a ds1/ei demultiplex loopback individual ds1 or e1 streams can be looped from the received ds3 stream and be placed back on the transmit ds3 stream. as with the ds2/g.747 demultiplex loopback the corresponding incoming ds1 or e1 stream will be ignored. figure 38. ds1/e1 demultiplex loopback6+ f r m r f f f f f f mx12 #1 mx12 #2 mx12 #3 mx12 #4 mx12 #5 mx12 #6 mx12 #7 ds3 frmr tclk tpos/ tdat tneg/ tmfp ds3 tran mx23 ? ? ? ? ? ? rclk rpos/ rdat rneg/ rlcv 6143 drw63 optional demux ais insertion ds1/e1 tributary loopback path rd1datn rd1clkn td1datn td1clkn
loopback modes 100 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
dc electrical characteristics 101 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice notes: 1. inputs/outputs are 5v tolerant. 2. voltages are with respect to ground (gnd) unless otherwise stated. dc electrical characteristics absolute maximum ratings symbol parameter min. max. unit vcc supply voltage -0.5 +4.0 v v i voltage on digital inputs gnd -0.3 vcc +0.3 v io current at digital outputs -50 50 ma ts storage temperature -55 +125 c p d package power dissipation ? 2 w recommended operating conditions (1) symbol parameter min. typ. max. unit vcc positive supply 3.0 3.3 3.6 v v ih (1) input high voltage 2.0 ? vcc v v il input low voltage -0.3 ? 0.8 v t op operating temperature industrial -40 25 +85 c
dc electrical characteristics 102 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice note: 1. voltages are with respect to ground (gnd) unless otherwise stated. 2. outputs unloaded. 3. 0 v vcc 4. maximum leakage on pins (output or i/o in high-impedance state) is over an applied voltage (v). 5. ioh = 10 ma 6. iol = 10 ma dc electrical characteristics symbol parameter min. typ. max. units icc (1) supply current ? ? 185 ma i il (3.4) input leakage (input pins) -10 ? 60 a i bl (3.4) input leakage (i/o pins) -10 60 a i oz (3,4) high-impedance leakage ? ? 60 a v oh (5) output high voltage 2.4 ? ? v v ol (6) output low voltage ? ? 0.4 v
ac electrical characteristics 103 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer ac electrical characteristics microprocessor interface timing charactericstics figure 39 microprocessor read access timing notes on microprocessor read timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt poi nt of the output. 2. maximum output propagation delays are measured with a 100 pf load on the microprocessor data bus, (d 7-0). 3. a valid read cycle is defined as a logical or of the csb and the rdb signals. 4. microprocessor timing applies to normal mode register accesses only. 5. when a set-up time is specified between an input and a clock, t he set-up time is the time in nanoseconds from the 1.4 volt p oint of the input to the 1.4 volt point of the clock. 6. when a hold time is specified between an input and a clock, t he hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 7. in non-multiplexed address/data bus architectures, ale should be held high, parameters t salr , t halr , t vl , t hlr and t slr are not applicable. 8. parameters t har and t sar are not applicable of address latching is used. microprocessor read access symbol parameter min. typ. max. unit t sar address to valid read set-up time 20 ? ns t har address to valid read hold time 20 ? ns t salr address to latch set-up time 20 ? ns t halr address to latch hold time 20 ? ns t vl valid latch pulse width 20 ? ns t hlr latch to read hold 20 ? ns t prd valid read to valid data propagation delay ? 100 ns t zrd valid read deserted to output tristate ? 20 ns t pinth valid read deasserted to intb tristate ? 50 ns ale (csb + rdb) intb d7-0 a8-0 6143 drw04 t sar t salr t vl t har t hlr t pinth t prd t hal vaild address vaild data t zrd
ac electrical characteristics 104 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 40 microprocessor write access timing notes on microprocessor write timing: 1. a valid write cycle is defined as a logical or of the csb and the wdb signals. 2. microprocessor timing applies to normal mode register accesses only. 3. in non-multiplexed address/data bus architectures, ale should be held high, parameters t salw , t halw , t vl , t hlw and t slw are not applicable. 4. parameters t haw and t saw are not applicable of address latching is used. 5. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt poi nt of the output. 6. when a set-up time is specified between an input and a clock, t he set-up time is the time in nanoseconds from the 1.4 volt p oint of the input to the 1.4 volt point of the clock. 7. when a hold time is specified between an input and a clock, t he hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. microprocessor write access symbol parameter min. max. unit t saw address to valid write set-up time 25 ? ns t sdw data to valid write set-up time 20 ? ns t salw address to latch set-up time 20 ? ns t halw address to latch hold time 20 ? ns t vl valid latch pulse width 20 ? ns t slw latch to write set-up 0 ? ns t hlw latch to write hold 20 ? ns t hdw data to valid write hold time 20 ? ns t haw address valid write hold time 20 ? ns t vwr valid write pulse width 40 ? ns ale (csb + rdb) d7-0 a8-0 6143 drw05 t vl t sdw vaild address vaild data t slw t hlw t hdw t salw t vwr t haw t hlw
ac electrical characteristics 105 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer timing characteristics figure 41 receive ds3 input timing receive ds3 input symbol parameter min. max. unit rclk frequency (nominally 44.736 mhz) -20 +20 ppm rclk duty cycle 40 60 % t srpos rpos/rdat set-up time 4 ? ns t hrpos rpos/rdat hold time 6 ? ns t srneg rneg/rlcv set-up time 4 ? ns t hrneg rneg/rlcv hold time 6 ? ns rclk rpos/rdat 6143 drw06 t srpos t hrpos t srneg t hrneg rneg/rdat
ac electrical characteristics 106 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 42 transmit ds3 input timing figure 43 transmit overhead input timing transmit ds3 input symbol parameter min. max. unit ticlk frequency (nominally 44.736 mhz) 20 ? ppm ticlk duty cycle 20 ? % t stimfp timfp set-up time 20 ? ns t htimfp timfp hold time 20 ? ns transmit overhead input symbol parameter min. max. unit t stoh toh set-up time 20 ? ns t htoh toh hold time 20 ? ns t stohen tohen set-up time 20 ? ns t htohen tohen hold time 20 ? ns ticlk 6143 drw07 t stimfp t htimfp timfp tohclk toh 6143 drw08 t stoh t htoh t stohen t htohen tohen
ac electrical characteristics 107 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 44 transmit tributary input timing figure 45 transmit data link input timing transmit tributary input symbol parameter min. max. unit td1clkn frequency (nominally 1.544 mhz, when configured for ds1 rate operation) -130 +130 ppm td1clkn frequency (nominally 2.048 mhz, when configured for e1 rate operation; not applicable for n = 4, 8, 12, 16, 20, 24, 28) -50 +50 ppm td1clkn frequency (nominally 6.312 mhz, when configured for ds2 rate operation; only applicable for n = 4, 8, 12, 16, 20, 24, 28) -33 +33 ppm td1clk duty cycle (all configurations) 33 67 % td2clk frequency (nominally 6.312 mhz) -33 +33 ppm td2clk duty cycle 33 67 % t std 1 dat td1dat set-up time 20 ? ns t htd 1 dat td1dat hold time 20 ? ns transmit data link input symbol parameter min. max. unit t stdlsig tdlsig to tdlclk set-up time 20 ? ns t htdlsig tdlsig to tdlclk hold time 20 ? ns td1clk td1dat 6143 drw09 t std1dat t htd1dat tdlclk tdlsig 6143 drw10 t stdlsig t htdlsig
ac electrical characteristics 108 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 46 transmit data link eom input timing notes on input timing: 1. when a set-up time is specified between an input and a clock, t he set-up time is the time in nanoseconds from the 1.4 volt p oint of the input to the 1.4 volt point of the clock. 2. when a hold time is specified between an input and a clock, t he hold time is the time in nanoseconds from the 1.4 volt point of the clock to the 1.4 volt point of the input. 3. td1clk frequency, td2clk frequency, t s 1 teomi , t s 2 teomi , t s 3 teomi and t vteomi values are guaranteed by design - not measured. transmit data link eom input symbol parameter min. max. unit t vteomi tdlemoi pulse width 3 5?ns t s 1 teomi tdlemoi pulse to falling edge of wfdl 3 transmit data register write set-up time 0?ns t s 2 teomi tdlemoi pulse to next falling edge of xfdl 3 transmit data register write set-up time 0?ns t s 3 teomi tdlemoi pulse after tdlint assertion 3 ? 210 s t hrpos t s2teomi t s3teomi t vteomi 6143 drw11 ?write of last byte? [i.e. wrb & (a[8:] = 22h]) tdleomi tdlint
ac electrical characteristics 109 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 47 transmit ds3 output timing transmit ds3 output symbol parameter min. max. unit tclk duty cycle ticlk -5 ticlk +5 % t ptpos tclk low to tpos/tdat valid prop. delay -2 5 ns t ptneg tclk low to tneg/tmfp valid prop. delay -2 5 ns tpos/tdat 6143 drw12 tneg/tmfp t ptpos t ptneg tclk
ac electrical characteristics 110 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 48 receive ds3 output timing receive ds3 output symbol parameter min. max. unit t prodat roclk low to rodat valid prop. delay -3 3 ns t prmfp roclk low to rmfp valid propagation delay -3 3 ns t prmsfp roclk low to rmsfp valid prop. delay -3 3 ns t prohp roclk low to rohp valid propagation delay -3 3 ns t prlos roclk low to rlos valid propagation delay -3 3 ns rodat 6143 drw13 rmfp t prodat t ptmfp roclk t prmsfp t rohp t prlos rmsfp rohp rlos
ac electrical characteristics 111 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 49 receive overhead output timing receive overhead output symbol parameter min. max. unit t proh rohclk low to roh valid propagation delay -5 20 ns t prohfp rohclk low to rohfp valid prop. delay -5 20 ns t prais rohclk low to rais valid propagation delay -5 20 ns t proof rohclk low to roof valid prop. delay -5 20 ns t prferf rohclk low to rferf valid prop. delay -5 20 ns roh 6143 drw14 rohfp t proh t prohfp rohclk t prais t proof t prferf rais roof/rred rferf
ac electrical characteristics 112 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 50 transmit overhead output timing figure 51 receive tributary output timing transmit overhead output symbol parameter min. max. unit t ptohfp tohclk low to tohfp valid prop. delay -10 20 ns receive tributary output symbol parameter min. max. unit t prd 1 dat rd1clk low to rd1dat valid prop. delay -10 20 ns tohfp t ptohfp tohclk 6143 drw15 rd1dat t prd1dat rd1clk 6143 drw16
ac electrical characteristics 113 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer figure 52 receive data link output timing notes on output timing: 1. output propagation delay time is the time in nanoseconds from the 1.4 volt point of the reference signal to the 1.4 volt poi nt of the output. 2. maximum output propagation delays are measured with a 20 pf l oad on the high-speed ds3 outputs (tclk, tpos/tdat, tneg/tmfp, roclk, rodat, rmfp, rmsfp, and rohp) and a 50 pf load on the remaining outputs. receive data link output symbol parameter min. max. unit t prd 1 dat rd1clk low to rd1dat valid prop. delay -10 20 ns rdlsig t prdlsig rdlclk 6143 drw17
ac electrical characteristics 114 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer
jtag 115 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer jtag timing specifications figure 53 standard jtag timing notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo device inputs (1) / tdi/tms tck 6143 drw17a t jrst t jrsr t jcd t jdc t jcyc t jr t jcl t jch t js t jh device outputs (2) / tdo trst
jtag 116 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. note: 1. device id foridt82v8313 is 0x0313. jtag ac electrical characteristics (1,2,3,4) symbol parameter min. max. units t jcyc jtag clock input period 100 - ns t jch jtag clcok high 40 - ns t jcl jtag clock low 40 - ns t jr jtag clock rise time - 3 (1) ns t jf jtag clock fall time - 3 (1) ns t jrst jtag reset 50 - ns t jrsr jtag reset recovery 50 - ns t jcd jtag data output - 25 ns t jdc jtag data output hold 0 - ns t js jtag setup 15 - ns t jh jtag hold 15 - ns identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x0312 (1) defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register scan register sizes register name bit size instruction (ir) 4 bypass (byr) 1 identification (idr) 32 boundary scan (bsr) note (3)
jtag 117 june 3, 2004 *notice: the information in this document is subject to change without notice idt82v8313 3.3 volt m13 multiplexer notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst 3. the boundary scan description language (bsdl) file for this device is available on the idt website (www.idt.com), or b y con tacting you local idt sales representative. system interface parameters instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. high-z 0011 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device input (2) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserv ed. do not use codes ot her than those indentified above. jtag information all fourteen even t1 data inputs (td1dat2, 4, 6...28) are inverted before jtag scan registers. so during jt ag preload/sample operation, the in- verted values will be shifted out in tdo output. in other words if 0 is ap- plied to the pin a 1 will be read out on tdo for that corresponding pin. all fourteen even t1 data outputs (d1dat2,4,6...28) are inverted after jtag scan registers. so during jtag extest operation, their iverted values will be output on the output pads. in other words if a 0 is loaded into the pad, a 1 will be seen on the pin when looked at externally.
idt82v8313 3.3 volt m13 multiplexer jtag 118 june 3, 2004 *notice: the information in this document is subject to change without notice jtag scan order name in out high-z td1clk27 0 rd1dat27 1 2 td1dat27 3 rd1clk26 4 5 td1clk26 6 rd1dat26 7 8 td1dat26 9 rd1clk25 10 11 td1clk25 12 rd1dat25 13 14 td1dat25 15 rd1clk24 16 17 td1clk24 18 rd1dat24 19 20 td1dat24 21 rd1clk23 22 23 td1clk23 24 rd1dat23 25 26 td1dat23 27 rd1clk22 28 29 td1clk22 30 rd1dat22 31 32 td1dat22 33 rd1clk21 34 35 td1clk21 36 rd1dat21 37 38 td1dat21 39 rd1clk20 40 41 td1clk20 42 rd1dat20 43 44 td1dat20 45 rd1clk19 46 47 td1clk19 48 rd1dat19 49 50 td1dat19 51 rd1clk18 52 53 td1clk18 54 rd1dat18 55 56 td1dat18 57 rd1clk17 58 59 td1clk17 60 rd1dat17 61 62 td1dat17 63 rd1clk16 64 65 td1clk16 66 rd1dat16 67 68 td1dat16 69 rd1clk15 70 71 td1clk15 72 rd1dat15 73 74 td1dat15 75 rd1clk14 76 77 td1clk14 78 rd1dat14 79 80 td1dat14 81 rd1clk13 82 83 td1clk13 84 rd1dat13 85 86 td1dat13 87 rd1clk12 88 89 td1clk12 90 rd1dat12 91 92 td1dat12 93 rd1clk11 94 95 td1clk11 96 rd1dat11 97 98 td1dat11 99 rd1clk10 100 101 td1clk10 102 rd1dat10 103 104 td1dat10 105 rd1clk9 106 107 td1clk9 108 jtag scan order name in out high-z
idt82v8313 3.3 volt m13 multiplexer jtag 119 june 3, 2004 *notice: the information in this document is subject to change without notice name in out high-z rd1dat9 109 110 td1dat9 111 rd1clk8 112 113 td1clk8 114 rd1dat8 115 116 td1dat8 117 rd1clk7 118 119 td1clk7 120 rd1dat7 121 122 td1dat7 123 rd1clk6 124 125 td1clk6 126 rd1dat6 127 128 td1dat6 129 rd1clk5 130 131 td1clk5 132 rd1dat5 133 134 td1dat5 135 rd1clk4 136 137 td1clk4 138 rd1dat4 139 140 td1dat4 141 rd1clk3 142 143 td1clk3 144 rd1dat3 145 146 td1dat3 147 rd1clk2 148 149 td1clk2 150 rd1dat2 151 152 td1dat2 153 rd1clk1 154 155 td1clk1 156 rd1dat1 157 158 td1dat1 159 tdlemoi 160 tdlsig 161 162 163 td2clk 164 tdlclk_int 165 166 timfp 167 ticlk 168 tclk 169 170 tpos_dat 171 172 rais 173 174 tneg_mfp 175 176 gd2clk 177 178 rodat 179 180 roclk 181 182 rmfp 183 184 rohp 185 186 tohclk 187 188 tohfp 189 190 rmsfp 191 192 toh 193 tohen 194 rohfp 195 196 roh 197 198 rohclk 199 200 rlos 201 202 rferf 203 204 roof_red 205 206 rexz 207 208 rclk 209 rpos_dat 210 rneg_lcv 211 rdclk_int 212 213 rdlsig_eom 214 215 int 216 217 d0 218 219 220 d1 221 222 223 d2 224 225 226 d3 227 228 229 name in out high-z
idt82v8313 3.3 volt m13 multiplexer jtag 120 june 3, 2004 *notice: the information in this document is subject to change without notice note: all fourteen even t1 data inputs (ts1dat2,4,6...28) are inverted before jtag scan registers. so during jtag preload/sample ope ration, the inverted values will be shifted out in tdo output. in other words if a 0 is applied to the pin 1 will be read out on tdo for that corresponding pin. all fourteen even t1 data outputs (rd1dat2,4,6...28) are inverted after jtag scan registers. so during jtag extest operation, t heir inverted values will be output on the output pads. in other words if a 0 is loades into the pad, a 1 will be seen on the pin when looked at externally. name in out high-z d4 230 231 232 d5 233 234 235 d6 236 237 238 d7 239 240 241 cs 242 ale 243 a0 244 a1 245 a2 246 a3 247 a4 248 a5 249 a6 250 name in out high-z a7 251 a8 252 wr 253 rd 254 rst 255 rd1clk28 256 257 td1clk28 258 rd1dat28 259 260 td1dat28 261 rd1cl27 262 263
idt82v8313 3.3 volt m13 multiplexer corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-5116 fax: 408-492-8674 www.idt.com for tech support: 408-330-1552 email:telecomhelp@idt.com the idt logo is a registered trademark of integrated device technology, inc. ordering information 121 june 3, 2004 *notice: the information in this document is subject to change without notice ordering information datasheet document history 12/15/2003 pgs. 1 thru 130 03/15/2004 pgs. 3 and 121. 06/03/2004 pgs. 101, 102 and 121. 6143 drw18 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 82v8313 3.3v m13 multiplexer ds plastic ball grid array (pbga, bb208-1) bb plastic quad flatpack (pqfp, ds208-1)
ordering information 122 june 3, 2004 idt82v8313 3.3 volt m13 multiplexer *notice: the information in this document is subject to change without notice
standards 123 june 3, 2004 *notice: the information in this document is subject to change without notice standards american national standards institute (ansi) ansi t1.101 1994: synchronization interface standard. ansi t1.102 1993: digital hierarchy: electrical interfaces. ansi t1.107 1995: digital hierarchy: formats specifications. ansi t1.231 1997: digital hierarchy: layer1 in-ser vice digital transmission performance monitoring. ansi t1.403 1995: network-to-customer installation ds1 metallic interface. ansi t1.404 1994: network-to-customer installation ds3 metallic interface specification bell communications research (bellcore) tr-tsy-000009 issue 1, 05/1986: asynchronous digital multiplexes - requirements and objectives. tr-nwt-000170 issue 2, 01/1993: digital cross-connec t system generic requirements and objectives. tr-nwt-000233 issue 3, 11/1993: wideband and broadband digital cross-connect systems generic criteria. tr-nwt-001112 issue 1, 06/1993: broadband-isdn user to network in terface and network node interface physical layer generic crit eria. gr-499-core issue 2, 12/1998: transport systems generic requirements (tsgr) common requirements. gr-820-core issue 2, 12/1997: generic digital trans mission surveillance (a module of otgr, fr-439). gr-1244-core - issue 1, 06/1995: clocks for the synchronized network: common generic criteria international telecommunication union (itu-t) recommendation g.703 04/91: physical/electrical char acteristics oh hierarchical digitalinterfaces recommendation g.704 07/95: synchronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels recommendation g.706 04/91: frame alignment and cyclic redundancy check (cgc) procedures relating to basic frame structures def ined in recommendation g.704 recommendation g.747 1988: second order digital multiplex equipment operating at 6312 kbit/s and multiplexing three tributaries at 2048 kbit/s recommendation g.752 1988: characteristics of digital multiplex equipment based on a second order bit rate of 6312 kbit/s and u sing positive justification recommendation g.824 03/93: the control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarc hy recommendation m.20 10/92: maintenance and philosophy for telecommunication networks recommendation o.150 05/96: general requirements for instrumentat ion for performance measurement s on digital transmission equip ment recommendation o.151 10/92: error performance measuri ng equipment operating at the primary rate and above recommendation o.152 10/92: error performance measuring equipment for bit rates of 64 kbit/s and n x 64 kbit/s signals recommendation o.153 10/92: basic parameters for the measurement of error performance at bit rates below the primary rate recommendation q.921 03/93: isdn user-network interface data link layer specification
idt82v8313 3.3 volt m13 multiplexer standards 124 june 3, 2004 *notice: the information in this document is subject to change without notice network working group rfc 2495 01/99: definitions of managed objects for the ds1, e1, ds2 and e2 interface types. other documents t1 basics (telecommunications techniques corporation - ttc) the fundamentals of ds3 1992 (telecommuni cations techniques corporation - ttc)
glossary 125 june 3, 2004 *notice: the information in this document is subject to change without notice glossary adm add / drop multiplexer aic application identification ais alarm indication singnal ais-ci alarm indication signal - customer installation aiss ais second ami alternate mark inversion ansi american national standards institute b-dcs broadband dcs ber bit error rate bert bit error rate testing bits building integrated timing source (or supply) bnzs bipolar with n zero substitution (n = 3 for ds3 and 8 for ds1 level) boc bit oriented code bpv bipolar violation c/r command / response cas-br channel associated signaling - bit robbing (signaling distributed in each ds0) cas-cc channel associated signaling - common channel (in timeslot 24 in t1 channel) cc composite clock ccs common channel signaling cfa carrier failure alarm cga carrier group alarm ci customer installation cofa change of frame alignment cp parity bit instead of stuffing indicator in ds3 c-bit parity mode crc cyclical redundancy check cs controlled slip css controlled slip second csu customer service unit cv code violation
idt82v8313 3.3 volt m13 multiplexer glossary 126 june 3, 2004 *notice: the information in this document is subject to change without notice cvcp "code violation, cp-bit" cvp "code violation, p-bit" dcs digital cross-connect system dsx "digital signal hierarchy, level x" ea extension address (field) edf extended superframe format eic equipment identification channel eom end of message err error es errored second esa "errored second, type a" esacp "errored second, type a, cp-bit" esap "errored second, type a, p-bit" esb "errored second, type b" esbcp "errored second, type b, cp-bit" esbp "errored second, type b, p-bit" escp "errored second, cp-bit" esp "errored second, p-bit" exz excessive zeros exzs excessive zero suppression fas frame alignment signal fc failure count fcs frame check sequence fdl facility data link feac far end alarm and control channel febe far end block error fepr far end performance report ferf far end receive failure fic fast information channel gps general positioning system hdb3 high density bipolar three hdlc high level data link control hssl high speed serial link idl idle pattern
idt82v8313 3.3 volt m13 multiplexer glossary 127 june 3, 2004 *notice: the information in this document is subject to change without notice isdn integrated services digital network isid idle signal identification itu international telecommunication union lline lapd link access protocol on the d channel lcv line code violation lfe line far end lic location identification channel liu line interface unit lod loss of data lof loss of frame los loss of signal mart maximum average reframe time mdl maintenance data link mop message oriented protocol ne network element np network path npfe network path nprm network performance report message oc-n optical carrier level n oof out of frame ppath per parity error ratio pfe path far end pid path identification pm performance monitoring pol polarity prm performance report message prs primary reference source ps protection switching psc protection switching count psd protection switching duration pte path terminating equipment rai remote alarm indication
idt82v8313 3.3 volt m13 multiplexer glossary 128 june 3, 2004 *notice: the information in this document is subject to change without notice rai-ci remote alarm indication - customer installation rdi remote defect indication red red alarm sapi service access point identifier sas severely errored frame / alarm indication signal (sef/ais) second sef severely errored frame ses severely errored second sescp "severely errored second, cp-bit" sesp "severely errored second, p-bit" sf superframe format signal slc96 subscriber loop carrier (96 subscriber access line) sonet synchronous optical network sprm supplement performance report message sts-n synchronous transport signal level n (sts-1: transmission rate of 51.84 mbit/s) tca threshold crossing alert tei terminal endpoint identifier tsid test signal identification uas unavailable second uascp "unavailable second, cp-bit" uasp "unavailable second, p-bit" udr underrun ui unit interval vt virtual tributary (vt1.5: 1.544 mbit/s signal encapsulated in a higher rate) w-dcs wideband dcs zbtsi zero-byte time slot interchange
index 129 june 3, 2004 *notice: the information in this document is subject to change without notice a ais - alarm indication signal 1, 6, 12, 17, 19, 22, 23, 32, 33, 36, 37, 38, 39, ......................................................................... 40, 42, 43, 46, 47, 71 aisc ...................................................................................... 36, 38 aise....................................................................................... 37, 42 aisi ........................................................................................ 39, 43 aisones............................................................................... 36, 38 aispat................................................................................... 36, 38 aisv........................................................................... 37, 39, 40, 43 dais ...................................................................................... 32, 47 lineais ....................................................................................... 17 mais ...................................................................................... 33, 47 rais ........................................................................ 5, 6, 37, 39, 67 xais............................................................................................. 46 b boc - bit oriented code ............................................................... 35, 71 boce........................................................................................... 35 boci ............................................................................................ 35 rboc .................................................................... 9, 12, 20, 35, 71 xboc............................................................................... 12, 34, 35 c crc - cyclical redundancy check ......................................... 28, 31, 71 ccitt-crc ................................................................................. 28 e eom - end of message........................................... 8, 28, 30, 31, 65, 71 rdleom ............................................................... 6, 16, 17, 20, 31 rfdleom ................................................................................... 20 err - error.......................................................................................... 71 cperr ............................................................................ 11, 26, 27 dcperr...................................................................................... 23 dferr ........................................................................................ 23 dmerr........................................................................................ 23 dperr ........................................................................................ 23 ferr ............................................................. 11, 12, 24, 25, 41, 44 perr......................................................................... 11, 12, 26, 45 rferr .......................................................................................... 5 exzs - excessive zero suppression................................. 11, 25, 38, 71 exzso......................................................................................... 38 f fdl - facility data link ....................................................................... 71 rfdl ............................................................... 6, 12, 20, 29, 30, 31 rfdleom ................................................................................... 20 rfdlint...................................................................................... 20 wfdl........................................................................................... 65 xfdl.......................................................... 8, 11, 20, 21, 28, 29, 65 xfdlint...................................................................................... 20 xfdludr.................................................................................... 21 feac - far end alarm control .................................... 12, 20, 34, 35, 71 febe - far end block error ...............................................11, 19, 27, 71 altfebe..................................................................................... 19 dfebe ........................................................................................ 23 febe ........................................................................................... 27 ferf - far end receive failure................... 1, 6, 22, 37, 39, 40, 42, 71 ferf0 ......................................................................................... 46 ferfe................................................................................... 37, 42 ferfi .................................................................................... 39, 42 ferfv....................................................................... 37, 39, 40, 43 rferf .................................................................... 5, 6, 37, 39, 67 xferf......................................................................................... 46 h hdlc - high level data link control...................6, 8, 11, 16, 20, 28, 71 rexhdlc ................................................................... 6, 16, 17, 20 texhdlc.............................................................. 8, 16, 17, 20, 21 i idl - idle pattern ........................................................................... 22, 71 idle .................................................................... 35, 36, 37, 39, 40 idlei ........................................................................................... 35 idli.............................................................................................. 39 idlv............................................................................................. 40 ridl ........................................................................................ 5, 22 l lapd - see previous page for description....................... 29, 30, 31, 71 lcv - line code violation..............................................1, 11, 24, 38, 71 dlcv........................................................................................... 23 rlcv....................................................................................... 5, 63 lof - los of frame ........................................................................ 1, 71 los - loss of signal .......................................................... 1, 19, 39, 71 dlos........................................................................................... 22 los ............................................................................................. 37 lose........................................................................................... 37 losi ............................................................................................ 39 losv............................................................................... 37, 39, 40 rlos........................................................................... 5, 37, 39, 66 o oof - out of frame ................................... 5, 19, 36, 37, 39, 41, 42, 71 oofe .................................................................................... 37, 42 oofi............................................................................................ 39 oofv ........................................................................ 37, 39, 40, 43 roof ................................................................ 5, 6, 19, 37, 39, 67 roov.......................................................................................... 37 p pol - polarity...................................................................................... 71 rempol ..................................................................................... 17 rintpol..................................................................................... 17 tintpol ..................................................................................... 17 tudrpol ................................................................................... 17 index
idt82v8313 3.3 volt m13 multiplexer index 130 june 3, 2004 *notice: the information in this document is subject to change without notice r rai - remote alarm indication .................................................. 1, 43, 46 red - red alarm............................................. 19, 36, 37, 39, 40, 42, 71 red2 ........................................................................................... 20 red2alme ................................................................................. 19 red3 ........................................................................................... 20 red3alme ................................................................................. 19 rede..................................................................................... 37, 42 redi ...................................................................................... 39, 42 redo .......................................................................... 6, 19, 37, 39 redv................................................................... 37, 39, 40, 42, 43 rred........................................................................... 6, 19, 37, 39 u udr - underrun............................................................................. 28, 71 tdludr ...................................................................... 8, 16, 17, 21 xfdludr.................................................................................... 21

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