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DS1302 trickle charge timekeeping chip DS1302 032598 1/12 features ? real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 ? 31 x 8 ram for scratchpad data storage ? serial i/o for minimum pin count ? 2.05.5 volt full operation ? uses less than 300 na at 2.0 volts ? singlebyte or multiplebyte (burst mode) data trans- fer for read or write of clock or ram data ? 8pin dip or optional 8pin soic's for surface mount ? simple 3wire interface ? ttlcompatible (v cc = 5v) ? optional industrial temperature range 40 c to +85 c ? ds1202 compatible ? added features over ds1202 optional trickle charge capability to v cc1 dual power supply pins for primary and backup power supplies backup power supply pin can be used for battery or super cap input additional scratchpad memory (7 bytes) pin assignment DS1302 v cc1 sclk i/o rst v cc2 x1 x2 gnd 1 2 3 4 8 7 6 5 v cc1 sclk i/o rst v cc2 x1 x2 gnd 1 2 3 4 8 7 6 5 DS1302s 8pin soic (200 mil) 8pin dip (300 mil) DS1302z 8pin soic (150 mil) pin description x1, x2 32.768 khz crystal pins gnd ground rst reset i/o data input/output sclk serial clock v cc1 , v cc2 power supply pins ordering information part # description DS1302 serial timekeeping chip; 8pin dip DS1302s serial timekeeping chip; 8pin soic (200 mil) DS1302z serial timekeeping chip; 8pin soic (150 mil) description the DS1302 trickle charge timekeeping chip contains a real time clock/calendar and 31 bytes of static ram. it communicates with a microprocessor via a simple serial interface. the real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. the clock operates in either the 24hour or 12hour format with an am/pm indicator. interfacing the DS1302 with a microprocessor is simpli- fied by using synchronous serial communication. only three wires are required to communicate with the clock/ ram: (1) rst (reset), (2) i/o (data line), and (3) sclk (serial clock). data can be transferred to and from the clock/ram one byte at a time or in a burst of up to 31 bytes. the DS1302 is designed to operate on very low power and retain data and clock information on less than 1 microwatt.
1 7 6 a4 5 a3 4 a2 3 a1 2 a0 1 rd 0 w ram ck DS1302 032598 2/12 the DS1302 is the successor to the ds1202. in addi- tion to the basic timekeeping functions of the ds1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, program- mable trickle charger for v cc1 , and seven additional bytes of scratchpad memory. operation the main elements of the serial timekeeper are shown in figure 1: shift register, control logic, oscillator, real time clock, and ram. to initiate any transfer of data, rst is taken high and eight bits are loaded into the shift register providing both address and command informa- tion. data is serially input on the rising edge of the sclk. the first eight bits specify which of 40 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. after the first eight clock cycles have loaded the com- mand word into the shift register, additional clocks will output data for a read or input data for a write. the num- ber of clock pulses equals eight plus eight for byte mode or eight plus up to 248 for burst mode. command byte the command byte is shown in figure 2. each data transfer is initiated by a command byte. the msb (bit 7) must be a logic a1o. if it is zero, writes to the DS1302 will be disabled. bit 6 specifies clock/calendar data if logic a0o or ram data if logic a1o. bits one through five specify the designated registers to be input or output, and the lsb (bit 0) specifies a write operation (input) if logic a0o or read operation (output) if logic a1o. the command byte is always input starting with the lsb (bit 0). DS1302 block diagram figure 1 32.768 khz x2 x1 oscillator and divider real time clock data bus input shift registers command and control logic address bus 31 x 8 ram i/o sclk rst power control v cc1 v cc2 gnd address/command byte figure 2
DS1302 032598 3/12 reset and clock control all data transfers are initiated by driving the rst input high. the rst input serves two functions. first, rst turns on the control logic which allows access to the shift register for the address/command sequence. second, the rst signal provides a method of terminating either single byte or multiple byte data transfer. a clock cycle is a sequence of a falling edge followed by a rising edge. for data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. if the rst input is low all data transfer terminates and the i/o pin goes to a high imped- ance state. data transfer is illustrated in figure 3. at powerup, rst must be a logic a0o until v cc 2.0 volts. also sclk must be at a logic a0o when rst is driven to a logic a1o state. data input following the eight sclk cycles that input a write com- mand byte, a data byte is input on the rising edge of the next eight sclk cycles. additional sclk cycles are ignored should they inadvertently occur. data is input starting with bit 0. data output following the eight sclk cycles that input a read com- mand byte, a data byte is output on the falling edge of the next eight sclk cycles. note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. additional sclk cycles retransmit the data bytes should they inadver- tently occur so long as rst remains high. this opera- tion permits continuous burst mode read capability. also, the i/o pin is tristated upon each rising edge of sclk. data is output starting with bit 0. burst mode burst mode may be specified for either the clock/calen- dar or the ram registers by addressing location 31 deci- mal (address/command bits one through five = logical one). as before, bit six specifies clock or ram and bit 0 specifies read or write. there is no data storage capac- ity at locations 9 through 31 in the clock/calendar reg- isters or location 31 in the ram registers. r eads or writes in burst mode start with bit 0 of address 0. as in the case with the ds1202, when writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. however, when writing to ram in burst mode it is not necessary to write all 31 bytes for the data to transfer. each byte that is written to will be transferred to ram regardless of whether all 31 bytes are written or not. clock/calendar the clock/calendar is contained in seven write/read reg- isters as shown in figure 4. data contained in the clock/ calendar registers is in binary coded decimal format (bcd). clock halt flag bit 7 of the seconds register is defined as the clock halt flag. when this bit is set to logic a1o, the clock oscillator is stopped and the DS1302 is placed into a lowpower standby mode with a current drain of less than 100 nanoamps. when this bit is written to logic a0o, the clock will start. the initial power on state is not defined. am-pm/12-24 mode bit 7 of the hours register is defined as the 12 or 24hour mode select bit. when high, the 12hour mode is selected. in the 12hour mode, bit 5 is the am/pm bit with logic high being pm. in the 24hour mode, bit 5 is the second 10 hour bit (20 23 hours). write protect bit bit 7 of the control register is the write protect bit. the first seven bits (bits 0 6) are forced to zero and will always read a zero when read. before any write opera- tion to the clock or ram, bit 7 must be zero. when high, the write protect bit prevents a write operation to any other register. the initial power on state is not defined. therefore the wp bit should be cleared before attempt- ing to write to the device. trickle charge register this register controls the trickle charge characteristics of the DS1302. the simplified schematic of figure 5 shows the basic components of the trickle charger. the trickle charge select (tcs) bits (bits 4 7) control the selection of the trickle charger. in order to prevent acci- dental enabling, only a pattern of 1010 will enable the trickle charger. all other patterns will disable the trickle charger. the DS1302 powers up with the trickle charger disabled. the diode select (ds) bits (bits 2 3) select whether one diode or two diodes are connected between v cc2 and v cc1 . if ds is 01, one diode is
DS1302 032598 4/12 selected or if ds is 10, two diodes are selected. if ds is 00 or 11, the trickle charger is disabled independent of tcs. the rs bits (bits 0 1) select the resistor that is connected between v cc2 and v cc1 . the resistor selected by the resistor select (rs) bits is as follows: rs bits resistor typical value 00 none none 01 r1 2k w 10 r2 4k w 11 r3 8k w if rs is 00, the trickle charger is disabled independent of tcs. diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a system power supply of 5v is applied to v cc2 and a super cap is connected to v cc1 . also assume that the trickle charger has been enabled with 1 diode and resistor r1 between v cc2 and v cc1 . the maximum current i max would therefore be calculated as follows: i max = (5.0v diode drop) / r1 ~ (5.0v 0.7v) / 2k w ~ 2.2 ma obviously, as the super cap charges, the voltage drop between v cc2 and v cc1 will decrease and therefore the charge current will decrease. clock/calendar burst mode the clock/calendar command byte specifies burst mode operation. in this mode the first eight clock/calen- dar registers can be consecutively read or written (see figure 4) starting with bit 0 of address 0. if the write protect bit is set high when a write clock/cal- endar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). the trickle charger is not accessi- ble in burst mode. ram the static ram is 31 x 8 bytes addressed consecutively in the ram address space. ram burst mode the ram command byte specifies burst mode opera- tion. in this mode, the 31 ram registers can be consec- utively read or written (see figure 4) starting with bit 0 of address 0. register summary a register data format summary is shown in figure 4. crystal selection a 32.768 khz crystal can be directly connected to the DS1302 via pins 2 and 3 (x1, x2). the crystal selected for use should have a specified load capacitance (cl) of 6 pf. for more information on crystal selection and crystal layout consideration, please consult application note 58, acrystal considerations with dallas real time clockso. power control v cc1 provides low power operation in single supply and battery operated systems as well as low power battery backup. v cc2 provides the primary power in dual supply sys- tems where v cc1 is connected to a backup source to maintain the time and data in the absence of primary power. the DS1302 will operate from the larger of v cc1 or v cc2 . when v cc2 is greater than v cc1 + 0.2v, v cc2 will power the DS1302. when v cc2 is less than v cc1 , v cc1 will power the DS1302.
DS1302 032598 5/12 data transfer summary figure 3 sclk i/o rst 01 23456 701 23456 7 r/w a0 a1 a2 a3 a4 1 address command data input/output single byte transfer sclk i/o 01 23456 701 2 456 7 1 1111 1 address command data i/o byte n burst mode transfer rst r/w data i/o byte 1 r/c r/c function byte n sclk n clock 8 72 ram 31 256
DS1302 032598 6/12 register address/definition figure 4 1 7 6 0 5 0 4 0 3 0 2 0 1 rd 0 w register address register definition 0 1 0 0 0 0 1 rd 0 w 1 0 0 0 1 0 rd 0 1 0 0 0 1 1 rd 0 w w 1 0 0 1 0 0 rd 0 1 0 0 1 0 1 rd 0 1 0 0 1 1 0 rd 0 1 0 0 1 1 1 rd 0 w w w w 1 0 1 0 0 0 rd 0 w 1 0 0 0 0 0 rd 1 1 1 1 1 1 0 rd 1 1 1 1 1 1 1 rd 1 w w w a. clock b. ram sec min hr date month day year control trickle ch sec 10 sec 0 12/ hr hr 0 0 10 date 0 0 0 10 0 0 0 0 0 10 year 0059 0059 0112 0128/29 0112 0107 0099 ram 0 ram 30 ram burst ram data 0 ram data 30 min 10 min 0023 24 10 a/p 0130 0131 date m month year day 0 wp 0 0 0 0 0 00 1 1 1 1 1 1 rd 0 w clock burst tcs tcs tcs ds ds rs tcs rs charger
DS1302 032598 7/12 DS1302 programmable trickle charger figure 5 1 of 3 select 1 of 2 select 1 of 16 select (note: only 1010 code enables charger v cc2 pin #1 v cc1 pin #8 trickle charger select diode select resistor select = = = tcs ds rs trickle tcs tcs tcs tcs ds ds rs rs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r1 r2 r3 2k w 4k w 8k w charge register
DS1302 032598 8/12 absolute maximum ratings* voltage on any pin relative to ground 0.5v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. the dallas semiconductor DS1302 is built to the highest quality standards and manufactured for long term reliability. all dallas semiconductor devices are made using the same quality materials and manufacturing methods. however, standard versions of the DS1302 are not exposed to environmental stresses, such as burnin, that some industrial applications require. products which have successfully passed through this series of environmental stresses are marked ind or n, denoting their extended operating temperature and reliability rating. for specific reliability informa- tion on this product, please contact the factory in dallas at (972) 3714448. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc1 , v cc2 v cc1 , v cc2 2.0 5.5 v 1, 11 logic 1 input v ih 2.0 v cc +0.3 v 1 logic 0 input v il v cc =2.0v 0.3 +0.3 v 1 l og i c 0 i npu t v il v cc =5v 0.3 +0.8 v 1 dc electrical characteristics (0 c to 70 c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes input leakage i li +500 m a 6 i/o leakage i lo +500 m a 6 logic 1 output v oh v cc =2.0v 1.6 v 2 l og i c 1 o u t pu t v oh v cc =5v 2.4 v 2 logic 0 output v ol v cc =2.0v 0.4 v 3 l og i c 0 o u t pu t v ol v cc =5v 0.4 v 3 active supply current i cc1a v cc1 =2.0v 0.4 ma 512 a c ti ve s upp l y c urren t i cc1a v cc1 =5v 1.2 m a 5 , 12 timekeeping current i cc1t v cc1 =2.0v 0.3 m a 412 ti me k eep i ng c urren t i cc1t v cc1 =5v 1 m a 4 , 12 standby current i cc1s v cc1 =2.0v 100 na 10, 12, st an db y c urren t i cc1s v cc1 =5v 100 n a 10 , 12 , 14 active supply current i cc2a v cc2 =2.0v 0.425 ma 513 a c ti ve s upp l y c urren t i cc2a v cc2 =5v 1.28 m a 5 , 13 *unless otherwise noted.
DS1302 032598 9/12 dc electrical characteristics (cont'd) (0 c to 70 c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes timekeeping current i cc2t v cc2 =2.0v 25.3 m a 413 ti me k eep i ng c urren t i cc2t v cc2 =5v 81 m a 4 , 13 standby current i cc2s v cc2 =2.0v 25 m a 10 13 st an db y c urren t i cc2s v cc2 =5v 80 m a 10 , 13 trickle charge resistors r1 r2 r3 2 4 8 k w k w k w trickle charger diode voltage drop v td 0.7 v *unless otherwise noted. capacitance (t a = 25 c) parameter symbol condition typ max units notes input capacitance c i 10 pf i/o capacitance c i/o 15 pf crystal capacitance c x 6 pf ac electrical characteristics (0 c to 70 c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes data to clk setup t dc v cc =2.0v 200 ns 7 d a t a t o clk s e t up t dc v cc =5v 50 ns 7 clk to data hold t cdh v cc =2.0v 280 ns 7 clk t o d a t a h o ld t cdh v cc =5v 70 ns 7 clk to data delay t cdd v cc =2.0v 800 ns 789 clk t o d a t a d e l ay t cdd v cc =5v 200 ns 7 , 8 , 9 clk low time t cl v cc =2.0v 1000 ns 7 clk l ow t i me t cl v cc =5v 250 ns 7 clk high time t ch v cc =2.0v 1000 ns 7 clk hi g h t i me t ch v cc =5v 250 ns 7 clk frequency t clk v cc =2.0v 0.5 mhz 7 clk f requency t clk v cc =5v dc 2.0 mh z 7 clk rise and fall t r t f v cc =2.0v 2000 ns clk ri se an d f a ll t r , t f v cc =5v 500 ns rst to clk setup t cc v cc =2.0v 4 m s 7 rst t o clk s e t up t cc v cc =5v 1 m s 7 *unless otherwise noted.
DS1302 032598 10/12 ac electrical characteristics (cont'd) (0 c to 70 c; v cc = 2.0 to 5.5v*) parameter symbol min typ max units notes clk to rst hold t cch v cc =2.0v 240 ns 7 clk t o rst h o ld t cch v cc =5v 60 ns 7 rst inactive time t cwh v cc =2.0v 4 m s 7 rst i nac ti ve t i me t cwh v cc =5v 1 m s 7 rst to i/o high z t cdz v cc =2.0v 280 ns 7 rst t o i/o hi g h z t cdz v cc =5v 70 ns 7 sclk to i/o high z t ccz v cc =2.0v 280 ns 7 sclk t o i/o hi g h z t ccz v cc =5v 70 ns 7 *unless otherwise noted. timing diagram: read data transfer figure 5 t cc t cdd t ccz t cdh t dc 017 rst sclk i/o write command byte read data bit 0 1 t cdd t cdz timing diagram: write data transfer figure 6 t cc 01 rst sclk i/o 7 t cwh t cch t cdh t dc t f t r t ch t cl write command byte write data 0
dim min max 8pin pkg a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 0.360 9.14 0.400 10.16 0.240 6.10 0.260 6.60 0.120 3.05 0.140 3.56 0.300 7.62 0.325 8.26 0.015 0.38 0.040 1.02 0.120 3.04 0.140 3.56 0.090 2.29 0.110 2.79 0.320 8.13 0.370 9.40 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 b c e f g h j k d 14 85 a DS1302 032598 11/12 notes: 1. all voltages are referenced to ground. 2. logic one voltages are specified at a source current of 1 ma at v cc =5v and 0.4 ma at v cc =2.0v, v oh =v cc for capacitive loads. 3. logic zero voltages are specified at a sink current of 4 ma at v cc =5v and 1.5 ma at v cc =2.0v, v ol =gnd for capacitive loads. 4. i cc1t and i cc2t are specified with i/o open, rst set to a logic a0o, and clock halt flag=0 (oscillator enabled). 5. i cc1a and i cc2a are specified with the i/o pin open, rst high, sclk=2 mhz at v cc =5v; sclk=500 khz, v cc =2.0v and clock halt flag=0 (oscillator enabled). 6. rst , sclk, and i/o all have 40k w pulldown resistors to ground. 7. measured at v ih =2.0v or v il =0.8v and 10 ms maximum rise and fall time. 8. measured at v oh =2.4v or v ol =0.4v. 9. load capacitance = 50 pf. 10. i cc1s and i cc2s are specified with rst , i/o, and sclk open. the clock halt flag must be set to logic one (oscillator disabled). 11. v cc =v cc2 , when v cc2 >v cc1 +0.2v; v cc =v cc1 , when v cc1 >v cc2 . 12. v cc2 =0 volts. 13. v cc1 =0 volts. 14. typical values are at 25 c. DS1302 serial timekeeper 8pin dip (300 mil)
DS1302 032598 12/12 DS1302s serial timekeeper 8pin soic (150 mil and 200 mil) dim min max 8pin (150 mil) pkg a in. mm b in. mm c in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 0.188 4.78 0.196 4.98 0.150 3.81 0.158 4.01 0.048 1.22 0.062 1.57 0.004 0.10 0.010 0.25 0.053 1.35 0.069 1.75 0.230 5.84 0.244 6.20 0.007 0.18 0.011 0.28 0.012 0.30 0.020 0.51 0.016 0.41 0.050 1.27 l in. mm phi 0 8 min max 0.203 5.16 0.213 5.41 0.203 5.16 0.213 5.41 0.070 1.78 0.074 1.88 0.004 0.10 0.010 0.25 0.074 1.88 0.084 2.13 0.302 7.67 0.318 8.08 0.006 0.15 0.010 0.25 0.013 0.33 0.020 0.51 0.019 0.48 0.030 0.76 0 8 0.050 bsc 1.27 bsc 8pin (200 mil) 56g2008001 56g4010001

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