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| d a t a sh eet preliminary speci?cation 1999 jan 12 integrated circuits tda8764 10-bit high-speed low-power adc with internal reference regulator
1999 jan 12 2 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 features 10-bit resolution (binary or gray code) sampling rate up to 40 mhz (/4 version) sampling rate up to 80 mhz (/8 version) dc sampling allowed one clock cycle conversion only high signal-to-noise ratio over a large analog input frequency range (9.5 effective bits at 5 mhz; full-scale input at f clk = 40 mhz) no missing codes guaranteed in-range (ir) cmos output ttl and cmos levels compatible digital inputs 2.7 to 3.6 v cmos digital outputs low-level ac clock input signal allowed internal reference voltage regulator power dissipation only 250 mw (typical for /4 version) power dissipation only 375 mw (typical for /8 version) low analog input capacitance, no buffer amplifier required no sample-and-hold circuit required. applications high-speed analog-to-digital conversion for: video data digitizing radar pulse analysis transient signal analysis high energy physics research sd modulators medical imaging. general description the tda8764 is a 10-bit high-speed low-power analog-to-digital converter (adc) for professional video and other applications. it converts the analog input signal into 10-bit binary or gray coded digital words at a maximum sampling rate of 40 mhz (/4 version) and 80 mhz (/8 version). all digital inputs and outputs are ttl compatible, although a low-level sine wave clock input signal is allowed. the device includes an internal voltage reference regulator. ordering information type number package sampling frequency (mhz) name description version tda8764ts/4 ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 40 tda8764ts/8 80 tda8764hl/4 lqfp32 plastic low pro?le quad ?at package; 32 leads; body 5 5 1.4 mm sot401-1 40 tda8764hl/8 80 1999 jan 12 3 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 quick reference data symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 2.7 3.3 3.6 v i cca analog supply current tda8764ts/4; tda8764hl/4 - 25 tbf ma tda8764ts/8; tda8764hl/8 - 45 tbf ma i ccd digital supply current tda8764ts/4; tda8764hl/4 - 25 tbf ma tda8764ts/8; tda8764hl/8 - 30 tbf ma i cco output stages supply current tda8764ts/4; tda8764hl/4 f clk = 40 mhz; ramp input - 0 tbf ma tda8764ts/8; tda8764hl/8 f clk = 80 mhz; ramp input - 0 tbf ma inl integral non-linearity tda8764ts/4; tda8764hl/4 f clk = 40 mhz; ramp input - 0.8 tbf lsb tda8764ts/8; tda8764hl/8 f clk = 80 mhz; ramp input - 0.8 tbf lsb dnl differential non-linearity tda8764ts/4; tda8764hl/4 f clk = 40 mhz; ramp input - 0.25 tbf lsb tda8764ts/8; tda8764hl/8 f clk = 80 mhz; ramp input - 0.25 tbf lsb f clk(max) maximum clock frequency tda8764ts/4; tda8764hl/4 40 -- mhz tda8764ts/8; tda8764hl/8 80 -- mhz p tot total power dissipation tda8764ts/4; tda8764hl/4 f clk = 40 mhz; ramp input - 250 tbf mw tda8764ts/8; tda8764hl/8 f clk = 80 mhz; ramp input - 375 tbf mw 1999 jan 12 4 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 block diagram fig.1 block diagram. handbook, full pagewidth dgnd2 r lad v rb v rm v rt v i v ccd2 v cca d4 d5 d6 d7 d8 d3 d2 d1 d0 d9 in-range latch cmos outputs latches analog-to-digital converter clock driver reference voltage regulator fce099 cmos output clk dec gray tc oe tda8764 v cco agnd 9 (15) 3 (7) 5 (10) 1 (5) 10 (16) 15 (21) 11 (17) analog ground digital ground digital ground dgnd1 ognd output ground analog voltage input data outputs lsb msb v ccd1 ir output 7 (13) 6 (12) 4 (8) 12 (18) 14 (20) 27 (3) 28 (4) 26 (2) 13 (19) 16 (22) 17 (23) 18 (24) 19 (25) 20 (26) 21 (27) 22 (28) 23 (29) 24 (30) 25 (31) 2 (6) 8 (14) the pin numbers given in parenthesis refer to the lqfp32 package. 1999 jan 12 5 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 pinning symbol pins description ssop28 lqfp32 clk 1 5 clock input tc 2 6 twos complement input (input active low) v cca 3 7 analog supply voltage (+5 v) agnd 4 8 analog ground dec 5 10 decoupling input v rb 6 12 reference voltage bottom input v rm 7 13 reference voltage middle input v i 8 14 analog input voltage v rt 9 15 reference voltage top input oe 10 16 output enable input (input active low) v ccd2 11 17 digital supply voltage 2 (+5 v) dgnd2 12 18 digital ground 2 v cco 13 19 supply voltage for output stages (2.7 to 3.6 v) ognd 14 20 output ground gray 15 21 gray code input (input active high) d0 16 22 data output; bit 0 (lsb) d1 17 23 data output; bit 1 d2 18 24 data output; bit 2 d3 19 25 data output; bit 3 d4 20 26 data output; bit 4 d5 21 27 data output; bit 5 d6 22 28 data output; bit 6 d7 23 29 data output; bit 7 d8 24 30 data output; bit 8 d9 25 31 data output; bit 9 (msb) ir 26 2 in-range data output dgnd1 27 3 digital ground 1 v ccd1 28 4 digital supply voltage 1 (+5 v) n.c. - 1, 9, 11 and 32 not connected 1999 jan 12 6 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 fig.2 pin configuration (ssop28). handbook, halfpage clk d9 d7 d6 d8 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 tda8764ts fce100 ir dgnd1 v ccd1 v cca agnd v ccd2 dgnd2 ognd gray v cco dec v rb v i v rt v rm tc oe fig.3 pin configuration (lqfp32). handbook, full pagewidth tda8764hl fce125 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 n.c. ir dgnd1 v ccd1 clk tc v cca agnd d3 d4 d5 d6 d7 d8 d9 n.c. v ccd2 dgnd2 ognd d2 d0 gray d1 v cco n.c. dec n.c. v rb v i v rt oe v rm 1999 jan 12 7 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v cc are respected. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output stages supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage difference v cca - v ccd - 1.0 +1.0 v v cca - v cco - 1.0 +4.0 v v ccd - v cco - 1.0 +4.0 v v i input voltage referenced to agnd - 0.3 +7.0 v v i(sw)(p-p) ac input voltage for switching (peak-to-peak value) referenced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature - 40 +85 c t j junction temperature - 150 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air ssop28 110 k/w lqfp32 90 k/w 1999 jan 12 8 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 characteristics the characteristics given refer to the ssop28 package. v cca =v 3 to v 4 = 4.75 to 5.25 v; v ccd =v 11 to v 12 and v 28 to v 27 = 4.75 to 5.25 v; v cco =v 13 to v 14 = 2.7 to 3.6 v; agnd and dgnd shorted together; t amb = 0 to 70 c; typical values measured at v cca =v ccd = 5 v and v cco = 3.3 v; c l = 10 pf and t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd1 digital supply voltage 1 4.75 5.0 5.25 v v ccd2 digital supply voltage 2 4.75 5.0 5.25 v v cco output stages supply voltage 2.7 3.3 3.6 v d v cc supply voltage difference v cca - v ccd - 0.20 - +0.20 v v cca - v cco - 0.20 - +2.55 v v ccd - v cco - 0.20 - +2.55 v i cca analog supply current tda8764ts/4; tda8764hl/4 - 25 tbf ma tda8764ts/8; tda8764hl/8 - 45 tbf ma i ccd digital supply current tda8764ts/4; tda8764hl/4 - 25 tbf ma tda8764ts/8; tda8764hl/8 - 30 tbf ma i cco output stages supply current tda8764ts/4; tda8764hl/4 f clk = 40 mhz; ramp input - 0 tbf ma tda8764ts/8; tda8764hl/8 f clk = 80 mhz; ramp input - 0 tbf ma inputs c lock input ; clk ( referenced to dgnd); note 1 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v clk = 0.8 v - 10+1 m a i ih high-level input current v clk =2v - 210 m a c i input capacitance - 2 - pf i nputs oe, tc and gray ( referenced to dgnd); see tables 3 and 4 v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2 - v ccd v i il low-level input current v il = 0.8 v - 1 --m a i ih high-level input current v ih =2v -- 1 m a 1999 jan 12 9 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 v i ( analog input voltage referenced to agnd) i il low-level input current tda8764ts/4; tda8764hl/4 v i =v rb - 0 -m a tda8764ts/8; tda8764hl/8 v i =v rb - 0 -m a i ih high-level input current tda8764ts/4; tda8764hl/4 v i =v rt - 45 -m a tda8764ts/8; tda8764hl/8 v i =v rt - 85 -m a y i input admittance tda8764ts/4; tda8764hl/4 f i = 5 mhz; note 2 input resistance - 70 - k w input capacitance 3 5 7 pf input admittance tda8764ts/8; tda8764hl/8 f i = 5 mhz; note 2 input resistance - 45 - k w input capacitance 3 5 7 pf reference voltages for the resistor ladder using the internal voltage regulator; see table 1 v rb reference voltage bottom tbf 1.3 tbf v v rt reference voltage top tbf 3.7 tbf v v diff(ref) differential reference voltage v rt - v rb tbf 2.4 tbf v tc vdiff temperature coef?cient of differential reference voltage - tbf - mv/k v offset(b) offset voltage bottom note 3 - 161 - mv v offset(t) offset voltage top note 3 - 161 - mv v i(p-p) analog input voltage (peak-to-peak value) note 4 tbf 2.08 tbf v outputs d igital outputs d9 to d0 and ir ( referenced to ognd) v ol low-level output voltage tda8764ts/4; tda8764hl/4 i ol = 1 ma 0 - 0.5 v tda8764ts/8; tda8764hl/8 i ol = 2 ma 0 - 0.5 v v oh high-level output voltage tda8764ts/4; tda8764hl/4 i oh = - 1ma v cco - 0.5 - v cco v tda8764ts/8; tda8764hl/8 i oh = - 2ma v cco - 0.5 - v cco v i oz output current in 3-state mode 0.5 v < v o 1999 jan 12 11 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 b andwidth (f clk =80mh z )/8 version ; b analog bandwidth full-scale sine wave; note 6 - 40 - mhz 75% full-scale sine wave; note 6 - 60 - mhz small signal at mid-scale; v i = 10 lsb at code 512; note 6 - 700 - mhz t stlh analog input settling time low-to-high full-scale square wave; see fig.7 and note 7 - tbf tbf ns t sthl analog input settling time high-to-low full-scale square wave; see fig.7 and note 7 - tbf tbf ns h armonics (f clk =40mh z )/4 version ; h all(fs) harmonics (full-scale); all components f i = 5 mhz second harmonics -- 70 tbf dbc third harmonics -- 90 tbf dbc sfdr spurious free dynamic range f i = 5 mhz - tbf - dbc thd total harmonic distortion f i = 5 mhz -- 70 - db h armonics (f clk =80mh z )/8 version ; h all(fs) harmonics (full-scale); all components f i = 5 mhz second harmonics -- 71 tbf dbc third harmonics -- 87 tbf dbc sfdr spurious free dynamic range f i = 5 mhz - tbf - dbc thd total harmonic distortion f i = 5 mhz -- 70 - db s ignal - to - noise ratio ; note 8 snr (fs) signal-to-noise ratio (full-scale) without harmonics; f i = 5 mhz f clk = 40 mhz; /4 version tbf 58 - db f clk = 80 mhz; /8 version tbf 58 - db e ffective bits ; note 8 eb effective bits tda8764ts/4; tda8764hl/4 f clk = 40 mhz f i = 5 mhz tbf 9.5 tbf bits f i = 7.5 mhz tbf 9.2 tbf bits f i = 10 mhz tbf 9.0 tbf bits f i = 20 mhz tbf tbf tbf bits effective bits tda8764ts/8; tda8764hl/8 f clk = 80 mhz f i = 5 mhz tbf 9.5 tbf bits f i = 10 mhz tbf tbf tbf bits f i = 20 mhz tbf tbf tbf bits f i = 40 mhz tbf tbf tbf bits symbol parameter conditions min. typ. max. unit 1999 jan 12 12 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 t wo - tone ; note 9 ttid two-tone intermodulation distortion f clk = 40 mhz - tbf - db f clk = 80 mhz - tbf - db b it error rate ber bit error rate f i = 5 mhz; v i = 16 lsb at code 512 f clk = 40 mhz - 10 - 13 - times/ sample f clk = 80 mhz - 10 - 13 - times/ sample timing (f clk = 40 mhz; c l = 10 pf) /4 version; see fig.5 and note 10 t ds sampling delay time -- 2ns t h output hold time 5 -- ns t d output delay time v cco = 2.7 v tbf 12 tbf ns v cco = 3.3 v tbf 11 tbf ns c l digital output load capacitance -- 10 pf sr slew rate v cco = 2.7 v; c l =10pf -- tbf v/ m s timing (f clk = 80 mhz; c l = 10 pf) /8 version; see fig.5 and note 10 t ds sampling delay time -- 2ns t h output hold time 4 -- ns t d output delay time v cco = 2.7 v tbf 8 tbf ns v cco = 3.3 v tbf 7 tbf ns c l digital output load capacitance -- 10 pf sr slew rate v cco = 2.7 v; c l =10pf -- tbf v/ m s 3-state output delay times (f clk = 40 mhz) /4 version; see fig.6 t dzh enable high - tbf tbf ns t dzl enable low - tbf tbf ns t dhz disable high - tbf tbf ns t dlz disable low - tbf tbf ns 3-state output delay times (f clk = 80 mhz) /8 version; see fig.6 t dzh enable high - tbf tbf ns t dzl enable low - tbf tbf ns t dhz disable high - tbf tbf ns t dlz disable low - tbf tbf ns symbol parameter conditions min. typ. max. unit 1999 jan 12 13 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. the input admittance is 3. analog input voltages producing code 0 up to and including code 1023: a) v offset(b) (offset voltage bottom) is the difference between the analog input which produces data equal to 00 and the reference voltage bottom (v rb ) at t amb =25 c. b) v offset(t) (offset voltage top) is the difference between reference voltage top (v rt ) and the analog input which produces data outputs equal to code 1023 at t amb =25 c. 4. in order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins v rb and v rt via offset resistors r ob and r ot as shown in fig.4. a) the current flowing into the resistor ladder is and the full-scale input range at the converter, to cover code 0 to code 1023, is b) since r l , r ob and r ot have similar behaviour with respect to process and temperature variation, the ratio will be kept reasonably constant from device to device. consequently variation of the output codes at a given input voltage depends mainly on the difference v rt - v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 5. 6. the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches greater than 2 lsbs, nor any significant attenuation are observed in the reconstructed signal. 7. the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. 8. effective bits are obtained via a fast fourier transform (fft) treatment taking 8 k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: sinad = eb 6.02 + 1.76 db. 9. intermodulation measured relative to either tone with analog input frequencies of 5 and 5.1 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter. 10. output data acquisition: the output data is available after the maximum delay time of t d(max) . for the 80 mhz version it is recommended to have the lowest possible output load. v i 1 r i ----- cijw + ? ?? = i l v rt v rb C r ob r l r ot ++ ----------------------------------------- - = v i r l i l r l r ob r l r ot ++ ----------------------------------------- - v rt v rb C () 0.866 v rt v rb C () = = = r l r ob r l r ot ++ ----------------------------------------- - e g v 1023 v 0 C () v ip p C () C v ip p C () ----------------------------------------------------------- - 100 = 1999 jan 12 14 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 table 1 output coding and input voltage (typical values; referenced to agnd); binary and gray codes table 2 output coding and input voltage (typical values; referenced to agnd); binary and twos complement codes step v i(p-p) ir binary output bits gray output bits d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 u/f 1999 jan 12 15 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 table 3 mode selection table 4 mode selection tc oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; two complement active 1 0 active; binary active gra y oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; binary active 1 0 active; gray active fig.5 timing diagram. handbook, full pagewidth ds t sample n + 1 sample n clk mbg916 sample n + 2 0 v 50% v cco 0 v 50% v cco v l data d0 to d9 t d t h cph t cpl t data n + 1 data n data n - 1 data n - 2 1999 jan 12 16 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 handbook, full pagewidth output data output data oe 50% 50% 50% 10% 90% low low high high t dzh t dzl t dhz v ccd t dlz tda8764 3.3 k w s1 oe v ccd 15 pf fce101 t dlz test s1 t dzl t dhz t dzh v ccd v ccd dgnd dgnd fig.6 timing diagram and test conditions of 3-state output delay time. f oe = 100 khz. fig.7 analog input settling time diagram. mbe566 50% stlh t 2 ns code 0 code 1023 i 50% 0.5 ns 50% 2 ns sthl t 50% 0.5 ns clk v 1999 jan 12 17 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 internal pin configurations fig.8 cmos data and in range outputs. handbook, halfpage mbg915 v cco ognd d9 to d0 ir fig.9 analog inputs. handbook, halfpage mgc040 - 1 agnd v cca v i fig.10 oe, gray and tc inputs. handbook, halfpage fce102 v cco ognd oe tc gray fig.11 v rb , v rm and v rt . handbook, halfpage r lad mbe558 - 1 v rb v rm agnd v rt v cca regulator dec 1999 jan 12 18 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 fig.12 clk input. handbook, halfpage fce103 1.5 v v ccd dgnd clk 1999 jan 12 19 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 application information fig.13 application diagram (ssop28). the analog and digital supplies should be separated and well decoupled. an application note is available which describes the design and the realization of a demonstration board that uses tda8764hl in an application environment. (1) v rb , v rm and v rt are decoupled to agnd. (2) decoupling capacitor for supplies; it must be placed close to the device . handbook, full pagewidth 28 27 26 25 24 23 22 21 20 19 18 17 tda8764ts dgnd1 d3 d4 d5 d6 d7 d8 d9 d2 d1 d0 gray 1 2 3 4 5 6 7 8 9 10 11 12 clk agnd dec v rb (1) v cca v rt (1) v rm (1) v ccd2 dgnd2 ognd v cco v i fce104 16 15 13 14 1 nf 1 nf 1 nf ir oe tc v ccd1 agnd 4.7 nf agnd 100 nf 100 nf agnd agnd (2) 100 nf (2) (2) 100 nf (2) 1999 jan 12 20 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 fig.14 application diagram (lqfp32). the analog and digital supplies should be separated and well decoupled. an application note is available which describes the design and the realization of a demonstration board that uses tda8764hl in an application environment. (1) v rb , v rm and v rt are decoupled to agnd. (2) decoupling capacitor for supplies; it must be placed close to the device . handbook, full pagewidth fce126 32 124 223 322 421 520 619 718 817 9 31 10 30 11 29 12 28 13 27 14 26 15 25 16 100 nf (2) 100 nf (2) 100 nf (2) 100 nf (2) tda8764hl n.c. ir dgnd1 v ccd1 clk v cca agnd 1 nf (1) agnd 1 nf (1) agnd 1 nf (1) agnd 4.7 nf agnd d3 d4 d5 d6 d7 d8 d9 n.c. v ccd2 dgnd2 ognd d2 d0 gray d1 v cco n.c. dec n.c. v rb v i v rt v rm tc oe 1999 jan 12 21 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 package outlines unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0 1999 jan 12 22 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 0.2 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.15 0.05 1.5 1.3 0.25 0.27 0.17 0.18 0.12 5.1 4.9 0.5 7.15 6.85 1.0 0.95 0.55 7 0 o o 0.12 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot401-1 95-12-19 97-08-04 d (1) (1) (1) 5.1 4.9 h d 7.15 6.85 e z 0.95 0.55 d b p e e b 8 d h b p e h v m b d z d a z e e v m a x 1 32 25 24 17 16 9 q a 1 a l p detail x l (a ) 3 a 2 y w m w m 0 2.5 5 mm scale lqfp32: plastic low profile quad flat package; 32 leads; body 5 x 5 x 1.4 mm sot401-1 c pin 1 index 1999 jan 12 23 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1999 jan 12 24 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. 1999 jan 12 25 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 notes 1999 jan 12 26 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 notes 1999 jan 12 27 philips semiconductors preliminary speci?cation 10-bit high-speed low-power adc with internal reference regulator tda8764 notes internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1999 sca61 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 62 5344, fax.+381 11 63 5777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 489 4339/4239, fax. +30 1 481 4240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 printed in the netherlands 295002/750/01/pp28 date of release: 1999 jan 12 document order number: 9397 750 04632 |
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