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www.fairchildsemi.com pentium is a registered trademark of intel corporation. programmable active droop is a trademark of fairchild semiconductor. rev. 1.0.4 features ? rogrammable output for vcore from 1.3v to 3.5v using an integrated 5-bit dac controls adjustable linears for vagp (selectable 1.5v/3.3v), vclock (2.5v), and vtt (1.5v) or vnorthbridge (1.8v) meets vrm speci?ation with as few as 5 capacitors meets 1.550v +40/-70mv over initial tolerance, temperature and transients remote sense programmable active droop (voltage positioning) drives n-channel mosfets ? v ercurrent protection using mosfet sensing 85% ef?iency typical at full load integrated power good and enable/soft start functions 24 pin soic package applications ? o wer supply for pentium iii camino platform ? o wer supply for pentium iii whitney platform vrm for pentium iii processor programmable multi-output power supply description the fan5059 is a synchronous mode dc-dc controller ic which provides a highly accurate, programmable set of output v oltages for multi-voltage platforms such as the intel camino, and provides a complete solution for the intel whitney and other high-performance processors. the fan5059 features remote v oltage sensing, independently adjustable current limit, and a proprietary programmable active droop for optimal converter transient response. the fan5059 uses a 5-bit d/a converter to program the output voltage from 1.3v to 3.5v. the f an5059 uses a high level of integration to deliver load block diagram vid3 vid2 vid1 16 vid0 gndp 23 22 2 18 24 1 17 - + - + osc 1.24v reference digital control power good 5-bit dac vid4 87654 +5v +12v pwrgd - + enable/ss vcc gnda 3 lodrv hidrv vccp 21 vcca +5v 20 - ref ref pwrgd, ocl pwrgd, ocl +3.3v +1.5v 10 9 +2.5v 12 11 19 ocl - + vccp pwrgd, ocl v 3.3/1.5v 15 14 13 r d r s - + + - + - + f an5059 high performance programmable synchronous dc-dc controller for multi-voltage platforms
fan5059 product specification 2 rev. 1.0.4 8/14/03 currents in excess of 16a from a 5v source with minimal e xternal circuitry. synchronous-mode operation offers opti- mum ef?iency over the entire speci?d output voltage range. an on-board precision low tc reference achieves tight toler- ance voltage regulation without expensive external compo- nents, while programmable active droop permits exact tailoring of voltage for the most demanding load transients. the f an5059 includes linear regulator controllers for vtt termina- tion (1.5v), vclock (2.5v), and vnorthbridge (1.8v) or vagp (selectable 1.5v/3.3v), each adjustable with an external divider. the fan5059 also offers integrated functions including power good, output enable/soft start and current limiting, and is av ailable in a 24 pin soic package. pin assignments 24 23 22 21 20 19 18 17 16 15 14 13 fan5059 hidrv sw gnda vid4 vid3 vid2 vid1 vid0 vttgate vttfb vckgate vckfb vccp lodrv gndp vcca vfb droop ilim pwrgd ss/enable typedet vagpgate vagpfb 1 2 3 4 5 6 7 8 9 10 11 12 pin de?itions pin number pin name pin function description 1 hidrv high side fet driver. connect this pin through a resistor to the gate of an n-channel mosfet. the trace from this pin to the mosfet gate should be <0.5". 2sw high side driver source and low side driver drain switching node. together with droop and ilim pins allows fet sensing for vcc current. 3 gnda analog ground. return path for low power analog circuitry. this pin should be connected to a low impedance system ground plane to minimize ground loops. 4-8 vid0-4 voltage identification code inputs. these open collector/ttl compatible inputs will program the output voltage over the ranges specified in table 2. pull-up resistors are internal to the controller. 9 vttgate gate driver for vtt transistor. for 1.5v output. 10 vttfb voltage feedback for vtt. 11 vckgate gate driver for vck transistor. for 2.5v output. 12 vckfb voltage feedback for vck. 13 vagpfb voltage feedback for vagp. 14 vagpgate gate driver for vagp transistor. for 3.3/1.5v output. 15 typedet type detect. sets 3.3v or 1.5v for agp. 16 enable/ss output enable. a logic low on this pin will disable all outputs. an internal current source allows for open collector control. this pin also doubles as soft start for all outputs. 17 pwrgd power good flag. an open collector output that will be logic low if any output voltage is more than ?2% outside of the nominal output voltage setpoint. 18 ilim vcc current feedback. pin 18 is used in conjunction with pin 2 as the input for the vcc current feedback control loop. layout of these traces is critical to system performance. see application information for details. 19 droop droop set. use this pin to set magnitude of active droop. 20 vfb vcc voltage feedback. pin 20 is used as the input for the vcc voltage feedback control loop. see application information for details regarding correct layout. 21 vcca analog vcc. connect to system 5v supply and decouple with a 0.1? ceramic capacitor. 22 gndp power ground. return pin for high currents flowing in pin 24 (vccp). 23 lodrv vcc low side fet driver. connect this pin through a resistor to the gate of an n-channel mosfet for synchronous operation. the trace from this pin to the mosfet gate should be <0.5". 24 vccp power vcc. for all fet drivers. connect to system 12v supply through a 33 ? , and decouple with a 1? ceramic capacitor. product specification fan5059 rev. 1.0.4 8/14/03 3 absolute maximum ratings note: 1. component mounted on demo board in free air. recommended operating conditions supply voltage vcca to gnd 13.5v supply voltage vccp to gnd 15v voltage identification code inputs, vid0-vid4 vcca all other pins 13.5v junction temperature, t j 150? storage temperature -65 to 150? lead soldering temperature, 10 seconds 300? thermal resistance junction-to-ambient, ja 1 75?/w p arameter conditions min. typ. max. units supply voltage vcca 4.5 5 5.25 v input logic high 2.0 v input logic low 0.8 v ambient operating temperature 0 70 c output driver supply, vccp 10.8 12 13.2 v electrical speci?ations (v cca = 5v, v ccp = 12v, v out = 2.0v, and t a = +25? using circuit in figure 1 unless otherwise noted.) the ?denotes speci?ations which apply over the full operating temperature range. p arameter conditions min. typ. max. units vcc regulator output voltage see table 1 1.3 3.5 v output current 18 a initial voltage setpoint i load = 0.8a,v out = 2.400v v out = 2.000v v out = 1.550v 2.397 2.000 1.550 2.424 2.020 1.565 2.454 2.040 1.580 v v v output temperature drift t a = 0 to 70?,v out = 2.000v v out = 1.550v +8 +6 mv mv line regulation v in = 4.75v to 5.25v -4 mv/v internal droop impedance i load = 0.8a to 12.5a 13.0 14.4 15.8 k ? maximum droop 60 mv output ripple 20mhz bw, i load = 18a 11 mvpk total output variation, steady state 1 v out = 2.000v v out = 1.550v 3 1.940 1.480 2.070 1.590 v total output variation, transient 2 i load = 0.8a to 18a, v out = 2.000v v out = 1.550v 3 1.900 1.480 2.100 1.590 v short circuit detect current 45 50 60 a efficiency i load = 18a, v out = 2.0v 85 % output driver rise & fall time see figure 3 50 nsec output driver deadtime see figure 3 50 nsec fan5059 product specification 4 rev. 1.0.4 8/14/03 notes: 1. steady state voltage regulation includes initial voltage setpoint, droop, output ripple and output temperature drift and is measured at the converter? vfb sense point. 2. as measured at the converter? vfb sense point. for motherboard applications, the pcb layout should exhibit no more than 0.5m ? trace resistance between the converter? output capacitors and the cpu. remote sensing should be used for optimal performance. 3. using the vfb pin for remote sensing of the converter? output at the load, the converter will be in compliance with intel? vrm 8.4 specification of +50, ?0mv. if intel specifications on maximum plane resistance from the converter? output capacitors to the cpu are met, the specification of +40, ?0mv at the capacitors will also be met. 4. actual output voltage (v nom ) at 0a load is 1% higher than specified in the ?ypical?column. duty cycle 0 100 % 5v uvlo 3.74 4 4.26 v 12v uvlo 7.65 8.5 9.35 v soft start current 5 10 17 ? vtt linear regulator output voltage 4 i load 2a 1.455 1.5 1.545 v under voltage trip level over current 80 %v o vclk linear regulator output voltage 4 i load 2a 2.425 2.5 2.575 v under voltage trip level over current 80 %v o va gp linear regulator output voltage 4 i load 2a, typedet=0v 1.455 1.5 1.545 v output voltage i load 2a, typedet=open 3.135 3.3 3.465 v under voltage trip level over current 80 %v o common functions oscillator frequency 255 310 345 khz pwrgd threshold logic high, all outputs logic low, any output 88 84 112 116 %v out linear regulator under voltage delay time over current 30 ?ec electrical speci?ations (continued) (v cca = 5v, v ccp = 12v, v out = 2.0v, and t a = +25? using circuit in figure 1 unless otherwise noted.) the ?denotes speci?ations which apply over the full operating temperature range. p arameter conditions min. typ. max. units product specification fan5059 rev. 1.0.4 8/14/03 5 note: 1. 0 = processor pin is tied to gnd. 1 = processor pin is open. table 1. output voltage programming codes vid4 vid3 vid2 vid1 vid0 nominal v out 01111 1.30v 01110 1.35v 01101 1.40v 01100 1.45v 01011 1.50v 01010 1.55v 01001 1.60v 01000 1.65v 00111 1.70v 00110 1.75v 00101 1.80v 00100 1.85v 00011 1.90v 00010 1.95v 00001 2.00v 00000 2.05v 11111 2.0v 11110 2.1v 11101 2.2v 11100 2.3v 11011 2.4v 11010 2.5v 11001 2.6v 11000 2.7v 10111 2.8v 10110 2.9v 10101 3.0v 10100 3.1v 10011 3.2v 10010 3.3v 10001 3.4v 10000 3.5v fan5059 product specification 6 rev. 1.0.4 8/14/03 t ypical operating characteristics (v cca = 5v, v ccp = 12v, and t a = +25? using circuits in figure 1, unless otherwise noted.) droop, v cpu = 2.0v, r d = 8k ? v out (v) v out (v) v cpu (v) v cpu (v) 2.04 2.03 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 1.94 0 3 6 9 12 15 18 output current (a) output programming, vid4 = 1 3.5 3.0 2.5 2.0 1.5 1.0 dac setpoint 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2. 3.3 3.4 3.5 v cpu efficiency vs. output current 88 86 84 82 80 78 76 74 72 70 68 66 64 output current (a) 0 3 6 9 12 15 18 v out = 1.550v v out = 2.000 v efficiency (%) output programming, vid4 = 0 2.1 1.9 1.7 1.5 1.3 1.1 dac setpoint 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 0 5 10 15 20 25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 cpu output voltage vs. output current output current (a) product specification fan5059 rev. 1.0.4 8/14/03 7 t ypical operating characteristics (continued) output ripple, 2.0v @ 18a time (1 s/div) time (1 s/div) v cpu (20mv/div) v cpu (50mv/div) v cpu (50mv/div) v cpu (1v/div) v in (2v/div) hidrv pin lodrv pin 5v/div 5v/div output startup, system power-up t ransient res p onse , 12.5a to 0.5a 1.590v 1.550v 1.480v 1.590v 1.550v 1.480v time (100 s/div) time (100 s/div) time (10ms/div) switching waveforms, 18a load output startup from enable v cpu (1v/div) enable (2v/div) time (10ms/div) t ransient response, 0.5a to 12.5a fan5059 product specification 8 rev. 1.0.4 8/14/03 t ypical operating characteristics (continued) application circuit figure 1. typical application circuit (worst case analyzed! see appendix for details ) 0 25 70 100 t emperature ( c) 2.042 2.040 2.038 2.036 2.034 2.030 2.028 2.026 v cpu (v) linear regulator noise ac coupled v out (10mv/div) time (100 s/div) 9 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 +5v l1 (optional) c in * q1 c2 c1 vid3 vid4 3.3v in typedet enable/ss 1.5v? 2.5v? 3.3/1.5v (agp)? vid2 vid1 vid0 q2 q4 q5 q3 d1 l2 c out * vo r6 r7 r5 r2 r3 c8 c10 c11 c9 c7 c4 c3 pwrgd vcc +12v c5 c6 r4 r1 u1 fan5059 ? adjustable with an external divider. * refer to appendix for values of c in , c out , r5 and r7. c12 product specification fan5059 rev. 1.0.4 8/14/03 9 ta b le 2. fan5059 application bill of materials (components based on worst case analysis?ee appendix for details) notes: 1. inductor l1 is recommended to isolate the 5v input supply from noise generated by the mosfet switching, and to comply with intel di/dt requirements. l1 may be omitted if desired. 2. for 17.4a designs using the to-220 mosfets, heatsinks with thermal resistance sa < 20?/w should be used. for designs using the to-263 mosfets, adequate copper area should be used. for details and a spreadsheet on mosfet selections, refer to applications bulletins ab-8 and ab-15. *refer to appendix for values. reference manufacturer part # quantity description requirements/comments c1 avx tajb475m010r5 1 4.7?, 10v capacitor c2, c5 panasonic ecu-v1c105zfx 2 1?, 16v capacitor c3-4,c6 panasonic ecu-v1h104zfx 3 100nf, 50v capacitor c7-9 sanyo 6mv1000fa 3 1000?, 6.3v electrolytic c10-12 any 3 22?, 6.3v capacitor low esr c in sanyo 10mv1200gx * 1200?, 10v electrolytic i rms = 2a c out sanyo 6mv1500gx * 1500?, 6.3v electrolytic esr 44m ? d1 motorola mbrd835l 1 8a schottky diode l1 any optional 2.5?, 8a inductor dcr ~ 10m ? see note 1. l2 any 1 1.3?, 20a inductor dcr ~ 2m ? q1 fairchild fdb6030l 1 n-channel mosfet r ds(on) = 20m ? @ v gs = 4.5v see note 2. q2 fairchild fdb7030bl 1 n-channel mosfet r ds(on) = 10m ? @ v gs = 4.5v see note 2. q3-5 fairchild fdb4030l 3 n-channel mosfet r1 any 1 33 ? r2-3 any 2 4.7 ? r4 any 1 10k ? r5 any 1 * r6 any 1 10 ? r7 any 1 * u1 fairchild f an5059m 1 dc/dc controller fan5059 product specification 10 rev. 1.0.4 8/14/03 figure 2. application circuit for coppermine/camino motherboards (typical design) 9 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 +5v l1 (optional) c in * q1 c2 c1 vid3 vid4 3.3v in typedet enable/ss 1.5v? 2.5v? 3.3/1.5v (agp)? vid2 vid1 vid0 q2 q4 q5 q3 d1 l2 c out * vo *refer to table 4 for values of c out and c in . r6 r7 r5 r2 r3 c8 c9 c7 c4 c3 pwrgd vcc +12v c5 c6 r4 r1 r8 u1 fan5059 ? adjustable with an external divider. c10 c11 c12 product specification fan5059 rev. 1.0.4 8/14/03 11 ta b le 3. fan5059 application bill of materials for intel coppermine/camino motherboards (typical design) notes: 1. inductor l1 is recommended to isolate the 5v input supply from noise generated by the mosfet switching, and to comply with intel di/dt requirements. l1 may be omitted if desired. 2. for 12.5a designs using the to-220 mosfets, heatsinks with thermal resistance sa < 20?/w should be used. for designs using the to-263 mosfets, adequate copper area should be used. for details and a spreadsheet on mosfet selections, refer to applications bulletins ab-8 and ab-15. reference manufacturer part # quantity description requirements/comments c1 avx tajb475m010r5 1 4.7?, 10v capacitor c2, c5 panasonic ecu-v1c105zfx 2 1?, 16v capacitor c3-4,c6 panasonic ecu-v1h104zfx 3 100nf, 50v capacitor c7-9 sanyo 6mv1000fa 3 1000?, 6.3v electrolytic c10-12 any 3 22?, 6.3v capacitor low esr c in sanyo 10mv1200gx 3 1200?, 10v electrolytic i rms = 2a c out sanyo 6mv1500gx 12 1500?, 6.3v electrolytic esr 44m ? d1 motorola mbrd835l 1 8a schottky diode l1 any optional 2.5?, 5a inductor dcr ~ 10m ? see note 1. l2 any 1 1.3?, 15a inductor dcr ~ 3m ? q1 fairchild fdb6030l 1 n-channel mosfet r ds(on) = 20m ? @ v gs = 4.5v see note 2. q2 fairchild fdb7030bl 1 n-channel mosfet r ds(on) = 10m ? @ v gs = 4.5v see note 2. q3-5 fairchild fdb4030l 3 n-channel mosfet r1 any 1 33 ? r2-3 any 2 4.7 ? r4 any 1 10k ? r5, r7 any 2 6.24k ? r6 any 1 10 ? r8 n/a 1 3.0m ? pcb trace resistor u1 fairchild fan5059m 1 dc/dc controller fan5059 product specification 12 rev. 1.0.4 8/14/03 t est parameters figure 3. ouput drive timing diagram application information the fan5059 controller the fan5059 is a programmable synchronous dc-dc con- troller ic. when designed around the appropriate external components, the fan5059 can be con?ured to deliver more than 16a of output current, as appropriate for the katmai and coppermine and other processors. the fan5059 functions as a ?ed frequency pwm step down regulator. main control loop refer to the fan5059 block diagram on page 1. the f an5059 implements ?umming mode control? which is dif- ferent from both classical voltage-mode and current-mode control. it provides superior performance to either by allow- ing a large converter bandwidth over a wide range of output loads. the control loop of the regulator contains two main sections: the analog control block and the digital control block. the analog section consists of signal conditioning ampli?rs feeding into a comparator which provides the input to the digital control block. the signal conditioning section accepts input from the droop (current feedback) and vfb (voltage feedback) pins and sets up two controlling signal paths. the ?st, the voltage control path, ampli?s the difference between the vfb signal and the reference voltage from the dac and presents the output to one of the summing ampli?r inputs. the second, current control path, takes the difference between the droop and sw pins when the high-side mosfet is on, reproducing the voltage across the mosfet and thus the input current; it presents the resulting signal to another input of the summing ampli?r. these two signals are then summed together. this output is then presented to a comparator looking at the oscillator ramp, which provides the main pwm control signal to the digital control block. the digital control block takes the analog comparator input and the main clock signal from the oscillator to provide the appropriate pulses to the hidrv and lodrv output pins. these two outputs control the external power mosfets. there is an additional comparator in the analog control section whose function is to set the point at which the fan5059 cur- rent limit comparator disables the output drive signals to the e xternal power mosfets. high current output drivers the fan5059 contains two identical high current output driv- ers that utilize high speed bipolar transistors in a push-pull con?uration. the drivers power and ground are separated from the chip s power and ground for switching noise immu- nity. the power supply pin, vccp, is supplied from an exter- nal 12v source through a series 33 ? resistor. the resulting v oltage is suf?ient to provide the gate to source drive to the e xternal mosfets required in order to achieve a low r ds,on . internal voltage reference the reference included in the fan5059 is a precision band- g ap v oltage reference. its internal resistors are precisely trimmed to provide a near zero temperature coef?ient (tc). based on the reference is the output from an integrated 5-bit da c. the dac monitors the 5 voltage identi?ation pins, vid0-4. when the vid4 pin is at logic high, the dac scales the reference v oltage from 2.0v to 3.5v in 100mv increments. when vid4 is pulled low, the dac scales the reference from 1.30v to 2.05v in 50mv increments. all vid codes are available, including those below 1.80v. po wer good (pwrgd) the fan5059 power good function is designed in accor- dance with the pentium ii and iii dc-dc converter speci? cations and provides a continuous voltage monitor on the vfb pin. the circuit compares the vfb signal to the vref v oltage and outputs an active-low interrupt signal to the cpu should the power supply voltage deviate more than ?6% of its nominal setpoint. power good outputs an open collector high when the output voltage is within ?2% of its nominal setpoint. the power good ?g provides no other control function to the fan5059. output enable/soft start (enable/ss) the fan5059 will accept an open collector/ttl signal for controlling the output voltage. the low state disables the output v oltage. when disabled, the pwrgd output is in the low state. even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nf) to softstart the switching. the softstart pin (enable/ss) ramp can be divided into three time periods. the ?st part is represented by t 1 , the second is represented by t 2 and the third is represented by t 3 . the voltage on the pin is: t r 5v t dt t dt t f hidrv to sw lodrv 2v 2v 2v 5v 2v v ss c ss i ss ---------- - ?? ?? t () = t 1 2.25 c ss i ss ---------- - ?? ?? = t 2 2.75 c ss i ss ---------- - ?? ?? t 1 = t 3 5 c ss i ss ---------- - ?? ?? t 1 t 2 + () = product specification fan5059 rev. 1.0.4 8/14/03 13 the softstart ramp begins at t(0) where uvlo is released. during the period of t 1 the softstart pin ramps but the pwm switching is not enabled and thus the duty cycle is zero (d=0) and the output voltage is zero. during t 2 the duty c ycle increased progressively from 0 to 1. this period is where the output voltage ramps, dependent on output capaci- tance and output load. if the duration of t 2 is long enough the output voltage will fully ramp to the point of regulation. during t 3 the softstart pin continues to ramp but without effect on the output voltage. note: if a very large output capacitor bank is used it may be required to use a larger c ss to ensure a full output voltage ramp within t 2 . over-voltage protection the fan5059 constantly monitors the output voltage for pro- tection ag ainst over-voltage conditions. if the voltage at the vfb pin e xceeds the selected program voltage, an over-volt- age condition is assumed and the fan5059 disables the out- put drive signal to the external high-side mosfet. the dc- dc converter returns to normal operation after the output v oltage returns to normal levels. oscillator the fan5059 oscillator section uses a ?ed frequency of operation of 300khz. design considerations and component selection additional information on design and component selection may be found in fairchild s application note 57. mosfet selection this application requires n-channel logic level enhancement mode field effect transistors. desired characteristics are as follows: ? ow static drain-source on-resistance, r ds,on < 20m ? (lower is better) ? ow gate drive voltage, v gs = 4.5v rated ? o wer package with low thermal resistance drain-source voltage rating > 15v. the on-resistance (r ds,on) is the primary parameter for mosfet selection. the on-resistance determines the power dissipation within the mosfet and therefore signi?antly affects the ef?iency of the dc-dc converter. for details and a spreadsheet on mosfet selection, refer to applica- tions bulletin ab-8. inductor selection choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. the system designer can choose any value within the allowed minimum to maximum range in order to either minimize ripple or maximize transient performance. the ?st order equation (close approximation) for minimum inductance is: where: v in = input power supply v out = output voltage f = dc/dc converter switching frequency esr = equivalent series resistance of all output capacitors in parallel v ripple = maximum peak to peak output ripple voltage budget. the ?st order equation for maximum allowed inductance is: where: c o = the total output capacitance i pp = maximum to minimum load transient current v tb = the output voltage tolerance budget allocated to load transient d m = maximum duty cycle for the dc/dc converter (usually 95%). some margin should be maintained away from both l min and l max . adding margin by increasing l almost always adds e xpense since all the variables are predetermined by system performance except for c o , which must be increased to increase l. adding margin by decreasing l can be done by purchasing capacitors with lower esr. the fan5059 provides signi?ant cost savings for the newer cpu systems that typically run at high supply current. f an5059 short circuit current characteristics the fan5059 protects against output short circuit on the core supply by turning off both the high-side and low-side mosfets and resetting softstart. the short circuit limit is set with the r s resistor, as given by the formula note: r s cannot exceed 10.8k. if a higher current is required than 10.8k allows, a fet with lower r dson must be used. 5v 2.75v 2.25v t 1 t 2 t 3 v ss t t(0) l min (v in ?v out ) f x v out v in x esr v ripple = l max (v in ?v out ) d m v tb i pp 2 = 2c o r s i sc *r ds, on i detect = fan5059 product specification 14 rev. 1.0.4 8/14/03 with i detect 50?, i sc is the desired current limit, and r ds,on the high-side mosfet s on resistance. remember to make the r s large enough to include the effects of initial tol- erance and temperature variation on the mosfet s r ds,on . alternately, use of a sense resistor in series with the source of the mosfet eliminates this source of inaccuracy in the current limit. as an example, figure 4 shows the typical characteristic of the dc-dc converter circuit with an fdb6030l high-side mosfet (r ds = 20m ? maximum at 25? * 1.25 at 75? = 25m ? ) and a 8.2k ? r s . figure 4. fan5059 short circuit characteristic the converter exhibits a normal load regulation characteristic until the voltage across the mosfet exceeds the internal short circuit threshold of 50? * 8.2k ? = 410mv, which occurs at 410mv/25m ? = 16.4a. (note that this current limit level can be as high as 410mv/15m ? = 27a, if the mosfet has typical r ds,on rather than maximum, and is at 25?). at this point, the internal comparator trips and signals the con- troller to discharge the softstart capacitor. this causes a drastic reduction in the output voltage as the load regulation collapses into the short circuit control mode. with a 40m ? output short, the voltage is reduced to 16.4a * 40m ? = 650mv. the output v oltage does not return to its nominal value until the output current is reduced to a value within the safe operating ranges for the dc-dc converter. if any of the linear regulator outputs are loaded heavily enough that their output voltage drops below 80% of nominal for >30?ec, all fan5059 outputs, including the switcher, are shut off and remain off until power is recycled. schottky diode selection the application circuit of figure 1 shows a schottky diode, d1, which is used as a free-wheeling diode to assure that the body-diode in q2 does not conduct when the upper mosfet is turning off and the lower mosfet is turning on. it is undesirable for this diode to conduct because its high forward v oltage drop and long reverse recovery time degrades ef?iency, and so the schottky provides a shunt path for the current. since this time duration is very short, the selection criterion for the diode is that the forward voltage of the schottky at the output current should be less than the forward voltage of the mosfet s body diode. output filter capacitors the output bulk capacitors of a converter help determine its output ripple voltage and its transient response. it has already been seen in the section on selecting an inductor that the esr helps set the minimum inductance, and the capacitance value helps set the maximum inductance. for most converters, however, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the esr and not the capacitance value. that is, in order to achieve the necessary esr to meet the transient and ripple requirements, the capacitance value required is already very large. the most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low esr. the only type of aluminum capacitor used should be those that have an esr rated at 100khz. consult application bulletin ab-14 for detailed information on output capacitor selection. the output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1? and 0.01? are recommended values. input filter the dc-dc converter design may include an input inductor between the system +5v supply and the converter input as shown in figure 5. this inductor serves to isolate the +5v supply from the noise in the switching portion of the dc-dc converter, and to limit the inrush current into the input capac- itors during power up. a value of 2.5? is recommended. it is necessary to have some low esr aluminum electrolytic capacitors at the input to the converter. these capacitors deliver current when the high side mosfet switches on. figure 5 shows 3 x 1000?, but the exact number required will vary with the speed and type of the processor. for the top speed katmai and coppermine, the capacitors should be rated to take 9a and 6a of ripple current respectively. capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to ?d out the ripple current rating at the expected operational temperature. f or details on the design of an input ?ter, refer to applica- tions bulletin ab-15. figure 5. input filter v out (v) 0 5 10 15 20 25 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 cpu output voltage vs. output current 2.5 h 5v 0.1 f 1000 f, 10v electrolytic vin product specification fan5059 rev. 1.0.4 8/14/03 15 programmable active droop the fan5059 includes programmable active droop : as the output current increases, the output voltage drops, and the amount of this drop is user adjustable. this is done in order to allow maximum headroom for transient response of the converter. the current is typically sensed by measuring the voltage across the r ds,on of the high-side mosfet dur- ing its on time, as shown in figure 1. to program the amount of droop, use the formula where i max is the current at which the droop occurs, and r sense is the resistance of the current sensor, either the source resistor or the high-side mosfet s on-resistance. for example, to get 30mv of droop with a maximum output current of 12.5a and a 10m ? sense resistor, use r d = 14.4k ? * 12.5a * 10m ? / (30mv * 18) = 3.33k ? . further details on use of the programmable active droop may be found in applications bulletin ab-24. remote sense the fan5059 offers remote sense of the output voltage to minimize the output capacitor requirements of the converter. it is highly recommended that the remote sense pin, pin 20, be tied directly to the processor power pins, so that the effects of power plane impedance are eliminated. further details on use of the remote sense feature of the fan5059 may be found in applications bulletin ab-24. adjusting the linear regulators output voltages any or all of the linear regulators outputs may be adjusted high to compensate for voltage drop along traces, as shown in figure 6. figure 6. adjusting the output voltage of the linear regulator the resistor value should be chosen as note: see note 4 in electrical speci?ations table. f or example, to get the v tt voltage to be 1.55v instead of 1.50v, use r = 10k ? * [(1.55/1.50) ?1] = 333 ? . using the fan5059 for vnorthbridge = 1.8v in some motherboards, intel requires that the agp power can not be greater than 2.2v while the chipset voltage (vnorthbridge = 1.8v) is less than 1.0v. the fan5059 can accomplish this by using the vtt regulator to generate vnorthbridge. use the circuit in figure 6 with r = 2k ? . since the linear regulators on the f an5059 all rise proportionally to one another, when vnorth- bridge = 1.0v, vagp = 1.8v, meeting the intel requirement. pcb layout guidelines placement of the mosfets relative to the fan5059 is critical. place the mosfets such that the trace length of the hidrv and lodrv pins of the fan5059 to the fet gates is minimized. a long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the fet. this noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very dif?ult to suppress. in general, all of the noisy switching lines should be kept aw ay from the quiet analog section of the fan5059. that is, traces that connect to pins 1, 2, 23, and 24 (hidrv, sw, lodrv and vccp) should be kept far away from the traces that connect to pins 3, 20 and 21. place the 0.1? decoupling capacitors as close to the f an5059 pins as possible. extra lead length on these reduces their ability to suppress noise. each vcc and gnd pin should have its own via to the appropriate plane. this helps provide isolation between pins. place the mosfets, inductor, and schottky as close together as possible for the same reasons as in the ?st b ullet above. place the input bulk capacitors as close to the drains of the high side mosfets as possible. in addition, placement of a 0.1? decoupling cap right on the drain of each high side mosfet helps to suppress some of the high frequency switching noise on the input of the dc-dc converter. place the output bulk capacitors as close to the cpu as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. additional space between the output capacitors and the cpu will allow the parasitic resistance of the board traces to degrade the dc-dc converter s performance under severe load transient conditions, causing higher voltage deviation. for more detailed information regarding capacitor placement, refer to application bulletin ab-5. ? pc board layout checklist is available from fairchild applications. ask for application bulletin ab-11. additional information f or additional information contact fairchild semiconductor at http://www.fairchildsemi.com/cf/tsg.htm or contact an autho- rized representative in your area. r d 14.4k ? *i max *r sense v droop *18 vfb vgate vout 10k ? r r 10k ? * 1 v out v nom = fan5059 product specification 16 rev. 1.0.4 8/14/03 appendix wo r st-case formulae for the calculation of cin, cout , r5, r7 and roffset (circuits similar to figure 1 only) the following formulae design the fan5059 for worst-case operation, including initial tolerance and temperature dependence of all of the ic parameters (initial setpoint, reference tolerance and tempco, internal droop impedance, current sensor gain), the initial tolerance and temperature dependence of the mosfet, and the esr of the capacitors. the following information must be provided: v s+ , the value of the positive static voltage limit; |v s- |, the absolute value of the negative static voltage limit; v t+ , the value of the positive transient voltage limit; |v t- |, the absolute value of the negative transient voltage limit; i o , the maximum output current; v nom , the nominal output voltage; v in , the input voltage (typically 5v); i rms , the ripple current rating of the input capacitors, per cap (2a for the sanyo parts shown in this datasheet); r d , the resistance of the current sensor (usually the mosfet); ? r d , the tolerance of the current sensor (usually about 67% for mosfet sensing, including temperature); and esr, the esr of the output capacitors, per cap (44m ? for the sanyo parts shown in this datasheet). the value of r7 must be 8.3k ? . if a greater value is calcu- lated, r d must be reduced. number of capacitors needed for c out = the greater of: example: suppose that the static limits are +89mv/-79mv, transient limits are ?34mv, current i is 14.2a, and the nominal voltage is 2.000v, using mosfet current sensing. we have v s+ = 0.089, |v s- | = 0.079, v t+ = |v t- | = 0.134, i o = 14.2, v nom = 2.000, and ? r d = 1.67. we calculate: since y > x, we choose y, and round up to ?d we need 7 capacitors for c out . a detailed explanation of this calculation may be found in applications bulletin ab-24. 2 i rms 1.01 * v nom v in v nom v in v nom * io c in = 45 * 10 - 6 i o * r d * (1 + ? r d ) r7 * 1k ? = v s+ ?.024 * v nom r offset = 18 * (v s+ + v s- ?.024 * v nom ) 14400 * i o * r d * (1 + ? r d ) *1.1 r5 = v t- + v s+ ?.024 * v nom esr * i o esr * i o x= 18 * r5 * 1.1 14400 * i o * r d y or v t+ ?v s+ + = 2 5 2.000 5 2.000 * 14.2 c in 2 3.47 ? 4 caps = = = = 3.48k ? 18 * (0.089 + 0.079 ?.024 * 2.000) 14400 * 14.2 * 0.020 * (1 + 0.67) * 1.1 r5 = = 5.25k ? 45 * 10 -6 14.2 * 0.010 * (1 + 0.67) r7 = = 20.3 ? *1000 1.01 * 2.000 0.089 ?.024 * 2.000 r offset 3.57 0.134 + 0.089 ?.024 * 2.00 0.044 * 14.2 x = = 6.14 18 * 3640 * 1.1 14400 * 14.2 * 0.020 0.134 ?0.089 0.044 * 14.2 y = + = product specification fan5059 rev. 1.0.4 8/14/03 17 mechanical dimensions 24 lead soic 24 13 112 a .093 .104 2.35 2.65 symbol inches min. max. min. max. millimeters notes a1 .004 .012 0.10 0.30 .020 0.51 b .013 0.33 c .009 .013 0.23 0.32 e .290 .299 7.36 7.60 e .394 .419 10.00 10.65 .010 .020 0.25 0.51 h .050 bsc 1.27 bsc h l .016 .050 0.40 1.27 0 8 0 8 3 6 5 2 2 n24 24 ccc .004 0.10 d .599 .614 15.20 15.60 notes: 1. 2. 3. 4. 5. 6. dimensioning and tolerancing per ansi y14.5m-1982. "d" and "e" do not include mold flash. mold flash or protrusions shall not exceed .010 inch (0.25mm). "l" is the length of terminal for soldering to a substrate. terminal numbers are shown for reference only. "c" dimension does not include solder finish thickness. symbol "n" is the maximum number of terminals. h e a d e b a1 ?c ccc c lead coplanarity seating plane h x 45 l c fan5059 product specification 8/14/03 0.0m 012 stock#ds30005059 ? 2000 fairchild semiconductor corporation disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com ordering information product number package fan5059m 24 pin soic |
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