0 to 125 0 to 125 0 to 125 0 to 125 0 to 125 IMP5111cdp IMP5111cdp IMP5111cdp IMP5111cdp IMP5111cdp IMP5111cpwp IMP5111cpwp IMP5111cpwp IMP5111cpwp IMP5111cpwp imp5112cdp imp5112cdp imp5112cdp imp5112cdp imp5112cdp imp5112cpwp imp5112cpwp imp5112cpwp imp5112cpwp imp5112cpwp 1 description key features n ultra-fast response for fast-20 scsi applications n 35mhz channel bandwidth n 3.3v operation n less than 3pf output capacitance n sleep-mode current less than 275 m a n thermally self limiting n no external compensation capacitors n implements 8-bit or 16-bit (wide) applications n compatible with active negation drivers (60ma / channel) n compatible with passive and active terminations n approved for use with scsi 1, 2, 3 and ultra scsi n hot swap compatible n pin-for-pin compatible with lx5211 and uc5606 (IMP5111) n pin-for-pin compatible with lx5212 and uc5603/5613/5614 (imp5112) receiver imp 5111/5112 lx5268 lx5268 1 meter, awg 28 driver 5111/5112 imp d riving w aveform - 20mh z r eceiving w aveform - 20mh z product highlight the IMP5111/5112 scsi terminators are part of imp's scsi terminator family of high-performance, adaptive, non-linear mode scsi products, which are designed to deliver true ultrascsi performance in scsi applications. the low voltage bicmos architecture employed in their design offers performance superior to older linear passive and active techniques. imp's scsi terminator architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible typically 35mhz, which is 100 times faster than the older linear regulator/ terminator approach used by other manufacturers. products using this older linear regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500khz (see further discussion in the functional description section). this new architecture also eliminates the output compensation capacitor required in earlier terminator designs. each is approved for use with scsi-1, -2, -3, ultrascsi and beyond providing the highest performance alternative available today. another key improvement offered by the IMP5111/5112 lies in their ability to insure reliable, error-free communications even in systems which do not adhere to recommended scsi hardware design guidelines, such as the use of improper cable lengths and impedances. frequently, this situation is not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. the IMP5111/5112 architecture is much more tolerant of marginal system integrations. recognizing the needs of portable and configurable peripherals, the IMP5111/5112 have a ttl compatible sleep/disable mode. quiescent current is typically less than 275 m a in this mode, while the output capacitance is also less than 3pf. the obvious advantage of extended battery life for portable systems is inherent in the product's sleep- mode feature. additionally, the disable function permits factory-floor or production-line configurability, reducing inventory and product-line diversity costs. field configurability can also be accomplished without physically removing components which, often times results in field returns due to mishandling. reduced component count is also inherent in the IMP5111/5112's architecture. traditional termination techniques require large stabilization and transient protection capacitors of up to 20 m f in value and size. the IMP5111/5112 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs. package order information t t t t t a a a a a ( ( ( ( ( c) c) c) c) c) note: all surface-mount packages are available in tape & reel. append the letter "t" to part number. (i.e. IMP5111cdpt) plastic soic 16-pin, power dp pwp plastic tssop 24-pin, power iso 9001 registered i m p 5111/5112 9-line scsi terminator 9-line scsi terminator 9-line scsi terminator 9-line scsi terminator 9-line scsi terminator C35mhz channel bandwidth
2 2.65 2.85 v 69ma 215 225 ma 275 m a 275 m a -21 -23 -24 ma 10 na -90 m a -90 m a 10 m a 10 na 10 na 3pf 35 mhz 60 ma termination voltage v term high level enable input voltage IMP5111 v ih imp5112 low level disable input voltage IMP5111 v il imp5112 operating virtual junction temperature range IMP5111c/5112c parameter symbol units recommended operating conditions min. typ. max. 3.3 5.5 v 2v term v 0 0.8 v 0 0.8 v 2v term v 0 125 c note 2. range over which the device is functional. electrical characteristics term power = 4.75v unless otherwise specified. unless otherwise specified, these specifications apply at the recommended operating ambient temperature of t a = 25 c. low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temper ature. parameter symbol test conditions units lx5111/5112 min. typ. max. output high voltage v out termpwr supply current i cc all data lines = open all data lines = 0.5v IMP5111 disconnect pin < 0.8v imp5112 disconnect pin > 2.0v output current i out v out = 0.5v disconnect input current IMP5111 i in disconnect pin = 4.75v disconnect pin = 0v disconnect input current imp5112 i in disconnect pin = 0v disconnect pin = 4.75v output leakage current IMP5111 i ol disconnect pin = < 0.8v, v o = 0.5v imp5112 disconnect pin = > 2.0v, v o = 0.5v capacitance in disconnect mode c out v out = 0v, frequency = 1mhz channel bandwidth bw termination sink current, per channel i sink v out = 4v termpwr voltage ................................................................................................. +7v signal line voltage .................................................................................... 0v to +7v regulator output current ................................................................................... 0.4a operating junction temperature plastic (dp, pwp packages) ......................................................................... 150 c storage temperature range .............................................................. -65 c to 150 c lead temperature (soldering, 10 seconds) ..................................................... 300 c note 1. exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of the specified terminal. dp? package: thermal resistance-junction to leads, q jl ............................................... 20 c/w thermal resistance-junction to ambient, q ja ..................... 50 c/w pwp package: thermal resistance-junction to leads, q jl .............................................. 27 c/w thermal resistance-junction to ambient, q ja .................. 100 c/w junction temperature calculation: t j = t a + (p d x q ja ). the q ja numbers are guidelines for the thermal performance of the device/pc-board system. all of the above assume no ambient airflow. thermal data absolute maximum ratings (note 1) package pin outs pwp package (top view) t6 t6 t6 t6 t6 t5 t5 t5 t5 t5 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd n.c. n.c. n.c. n.c. n.c. v v v v v term term term term term t4 t4 t4 t4 t4 t3 t3 t3 t3 t3 1 24 223 322 421 520 619 718 817 916 10 15 11 14 12 13 t7 t7 t7 t7 t7 t8 t8 t8 t8 t8 t9 t9 t9 t9 t9 n.c. n.c. n.c. n.c. n.c. gnd gnd gnd gnd gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd disconnect disconnect disconnect disconnect disconnect * * * * * t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t7 t7 t7 t7 t7 t8 t8 t8 t8 t8 t9 t9 t9 t9 t9 heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd gnd gnd gnd gnd gnd disconnect * disconnect * disconnect * disconnect * disconnect * t1 t1 t1 t1 t1 t2 t2 t2 t2 t2 t6 t6 t6 t6 t6 t5 t5 t5 t5 t5 n.c. n.c. n.c. n.c. n.c. heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd heatsink/gnd v v v v v term term term term term t4 t4 t4 t4 t4 t3 t3 t3 t3 t3 1 16 215 314 413 512 611 710 89 dp package (top view) *disconnect *disconnect *disconnect *disconnect *disconnect for the imp5112, and disconnect disconnect disconnect disconnect disconnect for the IMP5111. recommended operating conditions (note 2)
3 block diagram functional description thermal limiting circuit term power current biasing circuit 1.4v disconnect (5111) disconnect (5112) 24ma current limiting circuit data output pin db(0) 2.85v 1 of 9 channels cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage reference when the line is released (deasserted) and as an ideal current source when the line is active (asserted). common active terminators, which consist of linear regulators in series with resistors (typically 110 w ), are a compromise. as the line voltage increases, the amount of current decreases linearly by the equation v = i * r. the IMP5111/5112, with their unique new architecture applies the maximum amount of current regardless of line voltage until the termination high threshold (2.85v) is reached. acting as a near ideal line terminators, the IMP5111/5112 closely reproduce the optimum case when the devices are enabled. to enable the device the disconnect pin (disconnect pin for the imp5112) must be pulled logic high (logic low for the imp5112). during this mode of operation, quiescent current is 6ma and the devices will respond to line demands by delivering 24ma on assertion, and by imposing 2.85v on deassertion. in order to disable the device, the disconnect pin (disconnect pin for the imp5112) must be driven logic low (logic high for the imp5112). this mode of operation places the devices in a sleep state where a meager 275 m a of quiescent current is consumed. additionally, all outputs are in a hi-z (impedance) state. sleep mode can be used for power conservation or to completely eliminate the terminator from the scsi chain. in the second case, termination node capacitance is important to consider. the termina- tors will appear as a parasitic distributed capacitance on the line, which can detract from bus performance. for this reason, the IMP5111/5112 have been optimized to have only 3pf of capacitance per output in the sleep state. an additional feature of the IMP5111/5112 ic's are their compatibility with active negation drivers. these devices handle up to 60ma of sink current for drivers which exceed the 2.85v output high. outputs quiescent current h l enabled 6ma l h hi z 275 m a open open hi z 275 m a IMP5111 imp5112 disconnect disconnect p ower u p / p ower d own f unction t able
4 imp, inc. corporate headquarters 2830 n. first street san jose, ca 95134 tel: 408.432.9100 main tel: 800.438.3722 fax: 408.434.0335 fax-on-demand: 800.249.1614 (usa) fax-on-demand: 303.575.6156 (international) e-mail: info@impinc.com http://www.impweb.com the imp logo is a registered trademark of imp, inc. all other company and product names are trademarks of their respective owners. ? 1997 imp, inc. printed in usa part no.: IMP5111/5112 document number: IMP5111-01-9/97 iso 9001 registered package dimensions millimeters inches 24-pin tssop power pwp 1 2 3 e p seating plane b g a h e l c m d f dim min max min max a 1.73 1.99 0.068 0.078 b 0.25 0.38 0.009 0.015 c 0.13 0.22 0.005 0.008 d 7.70 7.90 0.303 0.311 e 5.20 5.38 0.205 0.212 f 0.65 bsc 0.025 bsc g 0.05 0.21 0.002 0.008 h 1.63 1.83 0.064 0.072 l 0.65 0.95 0.025 0.037 m 0 8 0 8 p 7.65 7.90 0.301 0.311 16-pin plastic soic power dp millimeters inches dim min max min max a 9.78 10.01 0.385 0.394 b 3.81 4.01 0.150 0.158 c 1.35 1.75 0.053 0.069 d 0.35 0.46 0.014 0.018 f 0.51 0.77 0.020 0.030 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.007 0.010 k 0.10 0.25 0.004 0.010 l 4.82 5.21 0.189 0.205 m 0 8 0 8 p 5.79 6.20 0.228 0.244 a b p d g f 16 9 8 1 c k j l m seating plane
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