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| www.fairchildsemi.com SPT7722 8-bit, 250 MSPS A/D Converter with Demuxed Outputs Features * * * * * * * * * TTL/CMOS/PECL input logic compatible High conversion rate: 250 MSPS Single +5V power supply Very low power dissipation: 425mW 350 MHz full power bandwidth Power-down mode: 24mW +3.0V/+5.0V (LVCMOS) digital output logic compatibility Single/demuxed output ports selectable Improved replacement for AD9054 Description The SPT7722 is a high-speed, 8-bit analog-to-digital converter implemented in an advanced BiCMOS process. It is a performance-enhanced version of the SPT7721, offering better linearity and dynamic performance. An advanced folding and interpolating architecture provides both a high conversion rate and very low power dissipation of only 425mW. The analog inputs can be operated in either single-ended or differential input mode. A 2.5V common mode reference is provided on chip for the single-ended input mode to minimize external components. The SPT7722 digital outputs are demuxed (double-wide) with both dual-channel and single-channel selectable output modes. Demuxed mode supports either parallel aligned or interleaved data output. The output logic is both +3.0V and +5.0V compatible. The SPT7722 is available in a 44-lead TQFP surface mount package over the industrial temperature range of -40C to +85C. Applications * * * * * RGB video processing Digital communications High-speed instrumentation Digital Sampling Oscilloscopes (DSO) Projection display systems Block Diagram AGND DGND AVCC OVDD VIN+ VIN 8-Bit 250 MSPS ADC CLK CLK Data Output Latches DA0DA7 DB0DB7 Common Mode Voltage Reference Data Output Mode Control 2 2 DCLKOUT DCLKOUT +2.5 V VCM PD CLK CLK Reset DMODE1,2 & Reset Rev. 1.0.2 December 2002 DATA SHEET SPT7722 Absolute Maximum Ratings Parameter Supply Voltages AVCC OVDD Input Voltages Analog Inputs Digital Inputs Temperature Operating Temperature Storage Temperature (beyond which damage may occur)1 25C Min. Max. +6 +6 -0.5 -0.5 -40 -65 VCC +0.5 VCC +0.5 +85 +125 Unit V V V V C C Note: 1. Operation at any absolute maximum rating is not implied. See Electrical Specifications table for proper nominal applied conditions in typical applications. Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) Parameter Resolution DC Performance (IN = 1kHz) Differential Linearity Error (DLE) Integral Linearity Error (ILE) No Missing Codes @250 MSPS Analog Input Input Voltage Range Input Common Mode (VCM) Input Bias Current Input Resistance Input Capacitance Input Bandwidth Gain Error Offset Error Offset Power Supply Rejection Ratio Timing Characteristics Conversion Rate Output Delay (Clock-to-Data) (tpd1) Output Delay Tempco Aperture Delay Time (tap) Aperture Jitter Time Conditions Test Level Min. Typ. 8 +25C -40C to +85C +25C -40C to +85C VI IV VI IV VI V IV V V V V VI VI V IV IV V V V -0.68 -0.95 0.4 0.7 1.2 1.4 Guaranteed 512 2.5 13 50 5 350 0.68 0.95 1.90 2.15 Max. Unit bits LSB LSB LSB LSB with respect to VIN+25C +25C +25C +25C (-3 dB of FS) +25C +25C AVCC = 5V 0.25V 2.0 3.0 -7.5 -5 <1 25 7.0 250 8 16 0.3 2.0 +3.5 +5 mVpp V A k pF MHz %FS LSB LSB MSPS ns ps/C ns ps-RMS -40C to +85C 9.4 NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. 2 Rev. 1.0.2 December 2002 SPT7722 DATA SHEET Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) Parameter Pipeline Delay (Latency) Single Channel Mode Demuxed Interleaved Mode Demuxed Parallel Mode Channel B Channel A CLK to DCLKOUT Delay Time Single Channel Mode (tpd2) Dual Channel Mode (tpd3) Output Delay (Clock to DClock) Dynamic Performance Effective Number of Bits (ENOB) IN = 70MHz IN = 70MHz Signal-to-Noise Ratio (SNR) IN = 70MHz IN = 70MHz Total Harmonic Distortion (THD) IN = 70MHz IN = 70MHz Signal-to-Noise & Distortion (SINAD) IN = 70MHz IN = 70MHz Power Supply Requirements AVCC Voltage (Analog Supply) OVDD Voltage (Digital Supply) AVCC Current AVCC Current Powerdown OVDD Current Single Mode Parallel Mode Interleave Mode Power Dissipation Common Mode Reference Output Voltage Voltage Tempco Output Impedance Power Supply Rejection Ratio Conditions Test Level V V V V IV IV V 5.0 5.6 Min. Typ. Max. Unit 2.5 2.5 2.5 3.5 5.18 5.73 18.1 5.3 5.9 Cycle Cycle Cycle Cycle ns ns ps/C +25C -40C to +85C +25C -40C to +85C +25C -40C to +85C +25C -40C to +85C VI IV VI IV VI IV VI IV IV IV VI VI V V V VI VI V V V 6.4 6.25 44.3 42.6 7.0 6.8 46.1 45.4 -47 -45.5 -41.5 -40.3 Bits Bits dB dB dB dB dB dB 5.25 5.25 110 5.5 V V mA mA mA mA mA mW V ppm/C k mV/V 40.2 39.3 4.75 2.75 43.7 42.8 5.0 85 4.8 35 55 55 425 +25C OVDD = 3.0V, 10pF load 550 2.56 2.44 IOUT = 50 A 2.5 84 1.07 47.5 NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. Rev. 1.0.2 December 2002 3 DATA SHEET SPT7722 Electrical Specifications (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) Parameter Clock and Reset Inputs Diff Signal Amplitude (VDIFF) Diff High Input Voltage (VIHD) Diff Low Input Voltage (VILD) Diff Common Mode Input (VCMD) SE High Input Voltage (VIH) SE Low Input Voltage (VIL) Input Current High (IIH) Input Current Low (IIL) Power Down & Mode Control Inputs High Input Voltage Low Input Voltage Max Input Current Low Max Input Current High <4.0V Digital Outputs Logic "1" Voltage Logic "0" Voltage TR/TF Data Conditions (Diff & Single-Ended) IV IV IV IV IV IV VI VI IV IV VI VI IOH = -0.5mA IOL = +1.6mA 10pF load OVDD = 3V OVDD = 5V 10pF load OVDD = 3V OVDD = 5V VI VI V V V V 400 1.4 0 1.2 1.8 0 -100 -100 2.0 0 -100 -100 OVDD-0.2 0.2 3.3/3.0 2.3/1.9 1.2/1.0 0.7/0.6 AVCC 3.9 4.1 1.2 +100 +100 AVCC 1.0 +100 +100 mVpp V V V V V A A V V A A V V ns ns ns ns Test Level Min. Typ. Max. Unit VID = 1.5V VID = 1.5V (Single-Ended) 43 43 0.5 50 TR/TF DCLK NOTE: All electrical characteristics are subject to the following condition: All parameters having min/max specifications are guaranteed. The Test Level column indicates the specific devices testing actually performed during production and quality assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL CODES: Level I II II IV V VI Test Procedure 100% production tested at the specified temperature. 100% production tested at TA = +25C and sample tested at the specified temperatures. QA sample tested only at the specified temperatures. Parameter is guaranteed (but not tested) by design and characterization data. Parameter is a typical value for information purposes only. 100% production tested at TA = +25C. Parameter is guaranteed over specific temperature range. 4 Rev. 1.0.2 December 2002 SPT7722 DATA SHEET Typical Operating Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) DLE vs. Sample Rate 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 200 225 IN = 70.1 MHz DLE vs. Temperature 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -50 -25 0 25 LSB LSB IN = 70.1MHz S = 250 MSPS 250 260 50 75 100 Sample Rate (MSPS) DLE vs. AVCC 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 100 IN = 70.1MHz S = 250 MSPS Temperature (C) AVCC Current vs. Temperature 90 80 70 60 50 40 30 20 10 0 Powerdown mode IN = 70.1MHz S = 250 MSPS 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 AVCC Current (mA) LSB -50 -25 0 25 50 75 100 Volts SNR, SINAD vs. Sample Rate 60 55 IN = 70.1 MHz SNR SINAD Temperature (C) SFDR, THD vs. Sample Rate -30 -35 IN = 70.1 MHz SNR, SINAD (dB) 50 45 40 35 30 25 20 200 225 SFDR, THD (dB) -40 -45 -50 -55 -60 -65 -70 THD SFDR 250 260 200 225 250 260 Sample Rate (MSPS) SNR, SINAD vs. Temperature 60 55 IN = 70.1 MHz S = 250 MSPS SNR Sample Rate (MSPS) THD vs. Temperature -30 -35 -40 IN = 70.1 MHz S = 250 MSPS SNR, SINAD (dB) 50 45 SINAD THD (dB) 75 100 -45 -50 -55 -60 -65 -70 40 35 30 25 20 -50 -25 0 25 50 -50 -25 0 25 50 75 100 Temperature (C) Rev. 1.0.2 December 2002 Temperature (C) 5 DATA SHEET SPT7722 Typical Operating Characteristics (TA = TMin to TMax, AVCC= +5V, OVDD = +5V, clk = 250MHz, 50% duty cycle, IN = 70MHz, dual channel mode; unless otherwise noted) SNR, SINAD vs. Duty Cycle 60 55 IN = 70.1 MHz S = 250 MSPS SFDR, THD vs. Duty Cycle -30 -35 IN = 70.1 MHz S = 250 MSPS SNR, SINAD (dB) SFDR, THD (dB) 50 45 SNR SINAD -40 -45 -50 -55 -60 -65 -70 THD SFDR 40 35 30 25 20 35 40 45 50 55 60 35 40 45 50 55 60 % Duty Cycle SNR, SINAD vs. AVCC 60 55 IN = 70.1 MHz S = 250 MSPS SNR % Duty Cycle THD vs. AVCC -30 -35 -40 IN = 70.1 MHz S = 250 MSPS SNR, SINAD (dB) 50 45 THD (dB) -45 -50 -55 -60 -65 -70 SINAD 40 35 30 25 20 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 Volts Volts 6 Rev. 1.0.2 December 2002 SPT7722 DATA SHEET Theory of Operation The SPT7722 is a three-step subranger. It consists of two THAs in series at the input, followed by three ADC blocks. The first block is a three-bit folder with over/under range detection. The second block consists of two single-bit folding interpolator stages. There are pipelining THAs between each ADC block. The analog decode functions are the input buffer, input THAs, three-bit folder, folding interpolators, and pipelining THAs. The input buffer enables the part to withstand rail-torail input signals without latchup or excessive currents and also performs single-ended to differential conversion. All of the THAs have the same basic architecture. Each has a differential pair buffer followed by switched emitter followers driving the hold capacitors. The input THA also has hold mode feedthrough cancellation devices. The three MSBs of the ADC are generated in the first threebit folder block, the output of which drives a differential reference ladder which also sets the full-scale input range. Differential pairs at the ladder taps generate midscale, quarter and three-quarter scale, overrange, and underrange. Every other differential pair collector is cross-coupled to generate the eighth scale zero crossings. The middle ADC block generates two bits from the folded signals of the previous stages after pipeline THAs. Its outputs drive more pipeline THAs to push the decoding of the three LSBs to the next half clock cycle. The three LSBs are generated in interpolators that are latched one full clock cycle after the MSBs. The digital decode consists of comparators, exclusive of cells for gray to binary decoding, and/or cells used for mostly over/under range logic. There is a total of 2.5 clock cycles latency before the output bank selection. In order to reduce sparkle codes and maintain sample rate, no more than three bits at a time are decoded in any half clock cycle. The output data mode is controlled by the state of the demux mode inputs. There are three output modes: * All data on bank A with clock rate limited to one-half maximum * Interleaved mode with data alternately on banks A and B on alternate clock cycles * Parallel mode with bank A delayed one cycle to be synchronous with bank B every other clock cycle If necessary, the input clock is divided by two. The divided clock selects the correct output bank. The user can synchronize with the divided clock to select the desired output bank via the differential RESET input. The output logic family is CMOS with output OVDD supply adjustable from 2.7V to 5.25V. There are also differential clock output pins that can be used to latch the output data in single bank mode or to indicate the current output bank in demux mode. Finally, a power-down mode is available, which causes the outputs to become tri-state, and overall power is reduced to about 24mW. There is a 2V reference to supply common mode for single-ended inputs that is not shut down in powerdown mode. N 2.5 CLK Cycles of Latency tap VIN CLK CLK N+1 N+2 N+3 N+4 N+5 tpd1 D0-D7 (Bank A) DCLKOUT DCLKOUT N-3 tpd2 tpd2 N-2 N-1 N N+1 N+2 Figure 1. Single Mode Timing Diagram Rev. 1.0.2 December 2002 7 DATA SHEET SPT7722 N-2 2.5 CLK Cycles of Latency tap N-1 N+1 N+2 N+3 N+4 VIN CLK Refer to AN7722 CLK U6Reset Reset Reset 550ps 550ps tpd1 tpd1 INTERLEAVED DATA OUTPUT Bank A Bank B N-5 N-6 N-4 Invalid Data N-1 N-2 N N+1 tpd3 Bank A 6ns typ N-7 N-6 N-5 N-4 PARALLEL DATA OUTPUT Invalid Data N-2 N N-1 Bank B DCLKOUT DCLKOUT tpd3 N-2 2.5 CLK Cycles of Latency N-1 N N+1 N+2 N+3 N+4 VIN CLK Refer to AN7722 CLK U6Reset Reset Reset tap 550ps 550ps tpd1 tpd1 INTERLEAVED DATA OUTPUT Bank A Bank B N-6 N-5 N-4 Invalid Data N-2 N-1 N N+1 tpd3 Bank A PARALLEL DATA OUTPUT N-6 N-5 tpd3 Invalid Data N-2 N N-1 Bank B DCLKOUT DCLKOUT Data Output Possibilities w/o Reset Figure 2. Dual Mode Timing Diagram 8 Rev. 1.0.2 December 2002 SPT7722 DATA SHEET Mode Select Reset Diff In Clock Diff Power Down +D3/5 30k DMODE1 DMODE2 CLK CLK RESET T1 AIN 50 VIN- Mini-Circuit T1-6T VIN+ VCM RESET DA0-DA7 SPT7722 DCLKOUT DCLKOUT DB0-DB7 DGND PD Interfacing Logics .01F AGND AVCC .01F .01F Notes: 1) FB = Ferrite bead. It must placed as close to the ADC as possible. 2) All 0.01 microfarad capacitors are surface mount caps. They must be placed as close to the respective pin as possible. 3) For details, refer to the Application Note AN7722. FB 10F + + 10F OVDD +D3/5 +D3/5 +A5 Figure 3. Typical Interface Circuit AVCC 17.5k Typical Interface Circuit Very few external components are required to achieve the stated device performance. Figure 3 shows the typical interface requirements when using the SPT7722 in normal circuit operation. The following sections provide descriptions of the major functions and outline performance criteria to consider for achieving the optimal device performance. CLK & RES 300 300 CLK & RES 100k 7.5k Analog Input AGND Figure 4. CLK and Reset Equivalent Circuit (without ESD Diodes) AVCC 100k 100k The input of the SPT7722 can be configured in various ways depending on whether a single-ended or differential input is desired. The AC-coupled input is most conveniently implemented using a transformer with a center-tapped secondary winding. The center tap is connected to the VCM pin as shown in Figure 3. To obtain low distortion, it is important that the selected transformer does not exhibit core saturation at the full-scale voltage. Proper termination of the input is important for input signal purity. A small capacitor across the input attenuates kickback noise from the internal track-and-hold. Figure 6 illustrates a solution (based on operational amplifiers) that can be used if a DC-coupled single-ended input is desired. VIN+ 300 200 200 300 VIN- 100k 100k AGND Figure 5. Analog Input Equivalent Circuit Rev. 1.0.2 December 2002 9 DATA SHEET R3 R3 VCM Input Voltage (0.5 V) (R3)/2 - + R2 R2 R - + 15pF VIN- 51 VIN+ R ADC SPT7722 Clock Input The clock input on the SPT7722 can be driven by either a single-ended or double-ended clock circuit and can handle TTL, PECL, and CMOS signals. When operating at high sample rates it is important to keep the pulse width of the clock signal as close to 50% as possible. For TTL/CMOS single-ended clock inputs, the rise time of the signal also becomes an important consideration. 51 R R + - R 51 Digital Outputs The output circuitry of the SPT7722 has been designed to be able to support three separate output modes. The demuxed (double-wide) mode supports either parallel aligned or interleaved data output. The single-channel mode is not demuxed and can support direct output at speeds up to 125 MSPS. The output format is straight binary (table 1). Table 1. Output Data Format Analog Input +FS +FS - 1 LSB +1 FS -FS + 1 LSB -FS Output Code D7-D0 1111 1111 1111 111O 1000 000O 0000 000O 0000 0000 Figure 6. DC-Coupled Single-Ended to Differential Conversion (power supplies and bypassing are not shown) Input Protection All I/O pads are protected with an on-chip protection circuit. This circuit provides ESD robustness and prevents latchup under severe discharge conditions without degrading analog transmission times. Power Supplies and Grounding The SPT7722 is operated from a single power supply in the range of 4.75V to 5.25V. Normal operation is suggested to be 5.0V. All power supply pins should be bypassed as close to the package as possible. The analog and digital grounds should be connected together with a ferrite bead as shown in the typical interface circuit and as close to the ADC as possible. O indicates the flickering bit between logic 0 and 1 The data output mode is set using the DMODE1 and DMODE2 inputs (pins 32 & 31 respectively). Table 2 describes the mode switching options. Table 2. Output Data Modes Output Mode DMODE1 DMODE2 Parallel Dual Channel Output 0 0 Interleaved Dual Channel Output 0 1 Single Channel Data Output 1 X (Bank A only 125 MSPS max) Power-Down Mode To save on power, the SPT7722 incorporates a power-down function. This function is controlled by the signal on pin PD. When pin PD is set high, the SPT7722 enters the power-down mode. All outputs are set to high impedance. In the powerdown mode the SPT7722 dissipates 24mW typically. Common-Mode Voltage Reference Circuit The SPT7722 has an on-board common-mode voltage reference circuit (VCM). It is 2.5V and is capable of driving 50A loads typically. The circuit is commonly used to drive the center tap of the RF transformer in fully differential applications. For single-ended applications, this output can be used to provide the level shifting required for the single-to-differential converter conversion circuit. Bypass VCM to AGND by external 0.01F capacitor, as shown in Figure 3. Evaluation Board The EB7721/22 evaluation board is available to aid designers in demonstrating the full performance of the SPT7722. This board includes a clock driver and reset circuit, adjustable references and common mode, a single-ended to differential input buffer and a single-ended to differential transformer (1:1). An application note (AN7722) describing the operation of this board, as well as information on the testing of the SPT7722, is also available. Contact the factory for price and availability of the EB7722. 10 Rev. 1.0.2 December 2002 SPT7722 DATA SHEET Pin Assignments AGND AGND AGND 44 AGND AVCC 42 AVCC 43 AVCC AVCC VIN+ 40 VIN- VCM 41 39 38 37 36 35 34 AGND PD CLK CLK RESET RESET OVDD DGND DA7 (MSB) DA6 DA5 1 2 3 4 5 6 7 8 9 10 11 12 DA4 13 DA3 14 DA2 15 DA1 16 DA0 (LSB) 17 OVDD 18 DGND 19 DB0 (LSB) 20 DB1 21 22 33 32 31 30 AGND DMODE1 DMODE2 OVDD DGND DCLKOUT DCLKOUT DB7 (MSB) DB6 DB5 DB4 SPT7722 TOP VIEW 44L TQFP 29 28 27 26 25 24 23 DB2 DB3 Pin Definitions Pin Name VIN+ VINDA0-DA7 DB0-DB7 DCLKOUT DCLKOUT CLK CLK RESET RESET DMODE1,2 Pin Number 40 39 16-9 19-26 28 27 4 3 5 6 32, 31 Pin Function Description Non-Inverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k pulldown to AGND, internally Inverted Analog Input; nominally 1 VPP; 100k pullup to VCC and 100k pulldown to AGND, internally Data Output Bank A; 3V/5V LVCMOS compatible Data Output Bank B; 3 V/5V LVCMOS compatible Non-Inverted Data Output Clock; 3V/5V LVCMOS compatible Inverted Data Output Clock; 3V/5V LVCMOS compatible Non-Inverted Clock Input Pin; 100k pulldown to AGND, internally Inverted Clock Input Pin; 17.5k pullup to VCC and 7.5k pulldown to AGND, internally RESET synchronizes the data sampling and data output bank relationship when in Dual Channel Mode (DMODE1 = 0); 100k pulldown to AGND, internally Inverted RESET Input Pin; 17.5k pullup to VCC and 7.5 pulldown to AGND, internally Internally: 100k pulldown to AGND on DMODE1 50k pullup to VCC on DMODE2 Data Output Mode Pins: DMODE1 = 0, DMODE2 = 0: Parallel Dual Channel Output DMODE1 = 0, DMODE2 = 1: Interleaved Dual Channel Output DMODE1 = 1, DMODE2 = X: Single Channel Data Output on Bank A (125 MSPS max) Power Down Pin; PD = 1 for power-down mode. Outputs set to high impedance in power-down mode; 100k pulldown to AGND, internally 2.5V Common Mode Voltage Reference Output +5V Analog Supply +3V/+5V Digital Output Supply Analog Ground Digital Ground PD VCM AVCC OVDD AGND DGND 2 37 35, 36, 42, 43 7, 17, 30 1, 33, 34, 38, 41, 44 8, 18, 29 Rev. 1.0.2 December 2002 11 DATA SHEET SPT7722 Ordering Information Model SPT7722 Part Number SPT7722SIT Package TQFP-44 Temperature range for all parts: -40C to +85C. Package Dimensions A B SYMBOL A B C D E F G H I J K TQFP-44 INCHES MIN TYP MAX 0.472 0.394 0.394 0.472 0.031 0.012 0.018 0.053 0.057 0.002 0.006 0.018 0.030 0.039 0-7 MILLIMETERS MIN TYP MAX 12.00 10.00 10.00 12.00 0.80 0.300 0.45 1.35 1.45 0.05 0.15 0.45 0.75 1.00 0-7 PIN1 Index CD E F G K H J I DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com (c) 2002 Fairchild Semiconductor Corporation |
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