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HI5728
Data Sheet July 1999 File Number 4321.4
10-Bit, 125/60MSPS, Dual High Speed CMOS D/A Converter
The HI5728 is a 10-bit, dual 125MSPS D/A converter which is implemented in an advanced CMOS process. It is designed for high speed applications where integration, bandwidth and accuracy are essential. Operating from a single +5V or +3V supply, the converter provides 20.48mA of full scale output current and includes an input data register. Low glitch energy and excellent frequency domain performance are achieved using a segmented architecture. A 60MSPS version and an 8-bit (HI5628) version are also available. Comparable single DAC solutions are the HI5760 (10-bit) and the HI5660 (8-bit). This DAC is a member of the CommLinkTM family of communication devices.
Features
* Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .125MSPS * Low Power . . . . . . . . . . . . . . . 330mW at 5V, 54mW at 3V * Integral Linearity Error . . . . . . . . . . . . . . . . . . . . . 1 LSB * Differential Linearity . . . . . . . . . . . . . . . . . . . . . . 0.5 LSB * Gain Matching (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . .0.5% * SFDR at 5MHz Output . . . . . . . . . . . . . . . . . . . . . . .68dBc * Single Power Supply from +5V to +3V * CMOS Compatible Inputs * Excellent Spurious Free Dynamic Range * Internal Voltage Reference * Dual 10-Bit D/A Converters on a Monolithic Chip
Ordering Information
PART NUMBER HI5728IN HI5728/6IN
www..com
Applications
MAX CLOCK SPEED 125MHz 60MHz 125MHz
TEMP. RANGE (oC)
* Wireless Local Loop * Direct Digital Frequency Synthesis * Wireless Communications * Signal Reconstruction * Arbitrary Waveform Generators * Test Equipment/Instrumentation * High Resolution Imaging Systems
PACKAGE
PKG. NO.
-40 to 85 48 Ld LQFP Q48.7x7A -40 to 85 48 Ld LQFP Q48.7x7A 25 Evaluation Platform
HI5728EVAL1
Pinout
HI5728 (LQFP) TOP VIEW
QD9 (MSB) QD8 ID9 (MSB)
DVDD DGND
QCLK DGND
ICLK
DVDD
ID6 ID5 ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP DVDD DGND NC AVDD
48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 1
ID7
QD7
ID8
QD6 QD5 QD4 QD3 QD2 QD1 QD0 (LSB) DVDD DGND NC AVDD AGND
AGND QOUTB
REFLO
IOUTA
AGND
ICOMP1
QOUTA FSADJ
IOUTB
REFIO
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright (c) Intersil Corporation 1999 CommLinkTM is a trademark of Intersil Corporation.
QCOMP1
AGND
HI5728 Functional Block Diagram
IOUTA IOUTB
(LSB) ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 (MSB) ID9 UPPER 5-BIT DECODER 31 LATCH LATCH 36 SWITCH MATRIX 36 5 LSBs + 31 MSB SEGMENTS CASCODE CURRENT SOURCE
ICLK ICOMP1 INT/EXT REFERENCE SELECT INT/EXT VOLTAGE REFERENCE BIAS GENERATION
REFLO REFIO FSADJ SLEEP QCOMP1
(LSB) QD0 QD1 QD2 QD3 QD4 QD5 QD6 QD7 QD8 UPPER 5-BIT DECODER 31 LATCH LATCH 36 SWITCH MATRIX 36 5 LSBs + 31 MSB SEGMENTS CASCODE CURRENT SOURCE
QCLK
AVDD
AGND
DVDD
DGND
QOUTA QOUTB
2
HI5728 Typical Applications Circuit
ICLK/QCLK 50 DVDD 0.1F DVDD 0.1F ANALOG GROUND PLANE DIGITAL GROUND PLANE
SLEEP
ID6 ID5 ID4 ID3 ID2 ID1 ID0 (LSB)
AGND
DVDD
0.1F AVDD 0.1F
48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 30 7 DVDD 29 8 DGND 28 9 DVDD NC (GROUND) 27 10 DGND AVDD 26 11 NC (GROUND) 25 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND
QD9 (MSB) QD8 QD7
ID7 ID8 ID9 (MSB)
QD6 QD5 QD4 QD3 QD2 QD1 QD0 (LSB) DVDD 0.1F AVDD 0.1F
AGND
QCOMP1 REFIO RSET 2k 0.1F 0.1F
AVDD NOTE: ICOMP1 AND QCOMP1 PINS (24, 14) MUST BE TIED TOGETHER EXTERNALLY
ICOMP1 AV DD 0.1F
50 50
50 50
IOUTA FERRITE BEAD 10H 0.1F
IOUTB
QOUTB
QOUTA FERRITE BEAD
+5V OR +3V SUPPLY + 10F
+5V OR +3V SUPPLY + 10F
DVDD (POWER PLANE)
AVDD (POWER PLANE) 0.1F
10H
3
HI5728 Pin Descriptions
PIN NO. 39-30 1-6, 48-46 8 15 23 22 14, 24 13, 18, 19, 25 17 16 20 21 11, 27 12, 26 10, 28, 41, 44 9, 29, 40, 45 43 42 PIN NAME PIN DESCRIPTION QD9 (MSB) Through Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the Q QD0 (LSB) channel. ID9 (MSB) Through ID0 (LSB) SLEEP REFLO REFIO FSADJ ICOMP1, QCOMP1 AGND IOUTB IOUTA QOUTB QOUTA NC AVDD DGND DVDD ICLK QCLK Digital Data Bit 9, the Most Significant Bit through Digital Data Bit 0, the Least Significant Bit, of the I channel. Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20A active pull-down current. Connect to analog ground to enable internal 1.2V reference or connect to AVDD to disable. Reference voltage input if internal reference is disabled and reference voltage output if internal reference is enabled. Use 0.1F cap to ground when internal reference is enabled. Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current Per Channel = 32 x IFSADJ . Reduces noise. Connect each to AVDD with 0.1F capacitor near each pin. The ICOMP1 and QCOMP1 pins MUST be tied together externally. Analog Ground Connections. The complimentary current output of the I channel. Bits set to all 0s gives full scale current. Current output of the I channel. Bits set to all 1s gives full scale current. The complimentary current output of the Q channel. Bits set to all 0s gives full scale current. Current output of the Q channel. Bits set to all 1s gives full scale current. No Connect. Recommended: connect to ground. Analog Supply (+2.7V to +5.5V). Digital Ground. Supply voltage for digital circuitry (+2.7V to +5.5V). Clock input for I channel. Positive edge of clock latches data. Clock input for Q channel. Positive edge of clock latches data.
4
HI5728
Absolute Maximum Ratings
Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V Analog Supply Voltage AVDD to ACOM . . . . . . . . . . . . . . . . . +5.5V Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Digital Input Voltages (D9-D0, CLK, SLEEP). . . . . . . . . DVDD +0.3V Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . . 50A Reference Input Voltage Range . . . . . . . . . . . . . . . . . . AVDD +0.3V Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Thermal Information
Thermal Resistance (Typical, Note 1) JA(oC/W) TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Power Dissipation TQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .930mW Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for `Power Supply Characteristics.' HI5728IN TA = -40oC TO 85oC
PARAMETER SYSTEM PERFORMANCE (Per Channel) Resolution Integral Linearity Error, INL Differential Linearity Error, DNL Offset Error, IOS Offset Drift Coefficient Full Scale Gain Error, FSE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10 "Best Fit" Straight Line (Note 7) (Note 7) (Note 7) (Note 7) With External Reference (Notes 2, 7) With Internal Reference (Notes 2, 7) -1 -0.5 -0.025 -10 -10 -0.5 FOUT = 10MHz (Note 3) -0.3 2
0.5 0.25 0.1 2 1 50 100 0.1 80 -
+1 +0.5 +0.025 +10 +10 0.5 1.25 20
Bits LSB LSB % FSR ppm FSR/oC % FSR % FSR ppm FSR/oC ppm FSR/oC dB dB V mA
Full Scale Gain Drift
With External Reference (Note 7) With Internal Reference (Note 7)
Gain Matching Between Channels I/Q Channel Isolation Output Voltage Compliance Range Full Scale Output Current, IFS DYNAMIC CHARACTERISTICS (Per Channel) Maximum Clock Rate, fCLK Output Settling Time, (tSETT) Singlet Glitch Area (Peak Glitch) Output Rise Time Output Fall Time Output Capacitance Output Noise IOUTFS = 20mA IOUTFS = 2mA (Note 3) 0.1% (1 LSB, equivalent to 9 Bits) (Note 7) 0.05% (1/2 LSB, equivalent to 10 Bits) (Note 7) RL = 25 (Note 7) Full Scale Step Full Scale Step
125 -
20 35 35 1.5 1.5 10 50 30
-
MHz ns ns pV*s ns ns pF pA/Hz pA/Hz
5
HI5728
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for `Power Supply Characteristics.' (Continued) HI5728IN TA = -40oC TO 85oC PARAMETER AC CHARACTERISTICS (Per Channel) - HI5728IN - 125MHz Spurious Free Dynamic Range, SFDR Within a Window fCLK = 125MSPS, fOUT = 32.9MHz, 10MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist fCLK = 100MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 125MSPS, fOUT = 32.9MHz, 62.5MHz Span (Notes 4, 7) fCLK = 125MSPS, fOUT = 10.1MHz, 62.5MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 40.4MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 20.2MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 5.04MHz, 50MHz Span (Notes 4, 7) fCLK = 100MSPS, fOUT = 2.51MHz, 50MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) AC CHARACTERISTICS (Per Channel) - HI5728/6IN - 60MHz Spurious Free Dynamic Range, SFDR Within a Window fCLK = 60MSPS, fOUT = 10.1MHz, 10MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 2MHz Span (Notes 4, 7) Total Harmonic Distortion (THD) to Nyquist Spurious Free Dynamic Range, SFDR to Nyquist fCLK = 50MSPS, fOUT = 2.00MHz (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz (Notes 4, 7) fCLK = 60MSPS, fOUT = 20.2MHz, 30MHz Span (Notes 4, 7) fCLK = 60MSPS, fOUT = 10.1MHz, 30MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 20.2MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 2.51MHz, 25MHz Span (Notes 4, 7) fCLK = 50MSPS, fOUT = 1.00MHz, 25MHz Span (Notes 4, 7) fCLK = 25MSPS, fOUT = 5.02MHz, 25MHz Span (Notes 4, 7) VOLTAGE REFERENCE Internal Reference Voltage, VFSADJ Internal Reference Voltage Drift Internal Reference Output Current Sink/Source Capability Reference Input Impedance Reference Input Multiplying Bandwidth (Note 7) Voltage at Pin 22 with Internal Reference 1.04 1.16 60 0.1 1 1.4 1.28 V
ppm/oC
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
75 76 75 76 78 71 71 76 54 64 52 60 68 74 63 55 68 73 73
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
-
75 76 78 71 76 56 63 55 68 73 73 71
-
dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
A M MHz
DIGITAL INPUTS D9-D0, CLK (Per Channel) Input Logic High Voltage with 5V Supply, VIH (Note 3) 3.5 5 V
6
HI5728
Electrical Specifications
AVDD = DVDD = +5V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25oC for All Typical Values. Data given is per channel except for `Power Supply Characteristics.' (Continued) HI5728IN TA = -40oC TO 85oC PARAMETER Input Logic High Voltage with 3V Supply, VIH Input Logic Low Voltage with 5V Supply, VIL Input Logic Low Voltage with 3V Supply, VIL Input Logic Current, IIH Input Logic Current, IIL Digital Input Capacitance, CIN TIMING CHARACTERISTICS (Per Channel) Data Setup Time, tSU Data Hold Time, tHLD Propagation Delay Time, tPD CLK Pulse Width, tPW1 , tPW2 POWER SUPPLY CHARACTERISTICS AVDD Power Supply DVDD Power Supply Analog Supply Current (IAVDD) Digital Supply Current (IDVDD) Supply Current (IAVDD) Sleep Mode Power Dissipation (Notes 8, 9) (Notes 8, 9) (5V or 3V, IOUTFS = 20mA) (5V or 3V, IOUTFS = 2mA) (5V, IOUTFS = Don't Care) (Note 5) (3V, IOUTFS = Don't Care) (Note 5) (5V or 3V, IOUTFS = Don't Care) (5V, IOUTFS = 20mA) (Note 6) (5V, IOUTFS = 2mA) (Note 6) (3V, IOUTFS = 20mA) (Note 6) (3V, IOUTFS = 2mA) (Note 6) (5V, IOUTFS = 20mA) (Note 10) (3.3V, IOUTFS = 20mA) (Note 10) (3V, IOUTFS = 20mA) (Note 10) Power Supply Rejection NOTES: 2. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625A). Ideally the ratio should be 32. 3. Parameter guaranteed by design or characterization and not production tested. 4. Spectral measurements made with differential coupled transformer and 100% amplitude. 5. Measured with the clock at 50MSPS and the output frequency at 1MHz, both channels. 6. Measured with the clock at 100MSPS and the output frequency at 40MHz, both channels. 7. See `Definition of Specifications'. 8. For operation below 3V, it is recommended that the output current be reduced to 12mA or less to maintain optimum performance. DVDD and AVDD do not have to be equal. 9. For operation above 125MHz, it is recommended that the power supply be 3.3V or greater. The part is functional with the clock above 125MSPS and the power supply below 3.3V, but performance is degraded. 10. Measured with the clock at 60MSPS and the output frequency at 10MHz, both channels. Single Supply (Note 7) 2.7 2.7 -0.2 5.0 5.0 46 8 6 3 3.2 330 140 170 54 300 150 135 5.5 5.5 60 10 6 +0.2 V V mA mA mA mA mA mW mW mW mW mW mW mW % FSR/V See Figure 41 (Note 3) See Figure 41 (Note 3) See Figure 41 See Figure 41 (Note 3) 3 3 4 1 ns ns ns ns (Note 3)s (Note 3) (Note 3) TEST CONDITIONS MIN 2.1 -10 -10 TYP 3 0 0 5 MAX 1.3 0.9 +10 +10 UNITS V V V A A pF
7
HI5728 Typical Performance Curves, 5 Volt Power Supply
80 75 -6dBFS SFDR (dBc) 0dBFS 65 60 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 OUTPUT FREQUENCY (MHz) -12dBFS SFDR (dBc) 70 76 74 72 -6dBFS 70 68 66 64 62 60 1 2 3 4 5 6 7 8 9 10 OUTPUT FREQUENCY (MHz) 0dBFS -12dBFS
FIGURE 1. SFDR vs fOUT, CLOCK = 5MSPS
80 0dBFS 75 SFDR (dBc) 70 65 60 55 75
FIGURE 2. SFDR vs fOUT, CLOCK = 25MSPS
-6dBFS
SFDR (dBc)
70
-6dBFS
-12dBFS
65 -12dBFS 60
0dBFS 50 45 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz)
55
0
5
10
15
20
25
30
35
40
45
OUTPUT FREQUENCY (MHz)
FIGURE 3. SFDR vs fOUT, CLOCK = 50MSPS
75 70 65 SFDR (dBc) SFDR (dBc) 60 55 50 45 0dBFS 50 0 5 10 15 20 25 30 35 40 45 50 -12dBFS 6dBFS
FIGURE 4. SFDR vs fOUT, CLOCK =100MSPS
80 25MSPS 75 70 65 125MSPS 60 55 50MSPS 100MSPS
45 -25
-20
-15
-10
-5
0
OUTPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
FIGURE 5. SFDR vs fOUT, CLOCK = 125MSPS
FIGURE 6. SFDR vs AMPLITUDE, fCLK /fOUT = 10
8
HI5728 Typical Performance Curves, 5 Volt Power Supply
80 25MSPS 75 50MSPS 70 SFDR (dBc) 100MSPS SFDR (dBc) 65 60 125MSPS 55 50 45 40 -25 -20 -15 -10 -5 0 45 40 -25 125MSPS (16.9/18.1MHz) -20 -15 -10 -5 0 65 60 55 50 100MSPS (13.5/14.5MHz) 50MSPS (6.75/7.25MHz) 70
(Continued)
75 25MSPS (3.38/3.63MHz)
AMPLITUDE (dBFS)
AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS)
FIGURE 7. SFDR vs AMPLITUDE, fCLK /fOUT = 5
75 70 65 SFDR (dBc) 60 55 50 45 40 2.5MHz
FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, fCLK /fOUT = 7
75 70 -6dBFS DIFF
10MHz 65 20MHz 40MHz SFDR (dBc) 60 55 50
0dBFS DIFF
-6dBFS SINGLE
0dBFS SINGLE 45 2 4 6 8 10 12 IOUT (mA) 14 16 18 20 0 5 10 15 20 25 30 35 40 OUTPUT FREQUENCY (MHz)
FIGURE 9. SFDR vs IOUT, CLOCK = 100MSPS
FIGURE 10. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS
80 2.5MHz 75 70 10.1MHz SFDR (dBc) 65 60 55 50 45 40 -40 -20 0 20 40 40.4MHz AMP (dB) Amp (dB)
-10 -10 -20 -20 -30 -30 -40 -40 -50 -50 -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 60 80 -110 -110 0 0 5MHz/div 5MHz/DIV Frequency (MHz) FREQUENCY (MHz) 50 fCLK = 100MSPS = f100MSPS =9.95MHz Fout = OUT 9.95MHz AMPLITUDE = 0dBFS Amplitude = 0dBFS SFDR = 64dBc SFDR = 64dBc 14dB 14dB External Analyzer Attenuation EXTERNAL ANALYZER ATTENUATION
TEMPERATURE (oC)
FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 12. SINGLE TONE SFDR
9
HI5728 Typical Performance Curves, 5 Volt Power Supply
-20 -20 -30 -30 -40 -40 -50 -50 AMP (dB) Amp (dB) -60 -60 -70 -70 -80 -80 -90 -90 -100 -100 -110 -110 0 0 5MHz/div 5MHz/DIV Frequency (MHz) FREQUENCY (MHz) 50 Fclk = 100MSPS fCLK = 100MSPS Fout = 13.5/14.5MHz fOUT = 13.5/14.5MHZ Combined Peak Amplitude =PEAK COMBINED 0dBFS MTPR = 62.9dBc AMPLITUDE = 0dBFS 14dB External Analyzer = 62.9dBc SFDR Attenuation 14dB EXTERNAL ANALYZER ATTENUATION
(Continued)
-10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0.5 fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 71.4dBc (IN A WINDOW)
1.45MHz / DIV
15
FIGURE 13. TWO TONE, CLOCK = 100MSPS
FIGURE 14. FOUR-TONE, CLOCK = 100MSPS
-20 -30 -40 -50 AMP (dB) AMP (dB) -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV FREQUENCY (MHz) 20 fCLK = 100MSPS fOUT = 2.6,3.2,3.8,4.4,5.6,6.2,6.8MHZ COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67dBc (IN A WINDOW)
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0.5 950kHz/DIV FREQUENCY (MHz) 10 fCLK = 50MSPS fOUT = 1.9,2.2,2.8,3.1MHZ COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 73.6dBc (IN A WINDOW)
FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 16. FOUR-TONE, CLOCK = 50MSPS
0.4
0.4
0.2
0.2
LSB
LSB
0
0
-0.2
-0.2
-0.4 0 200 400 CODE 600 800 1000
-0.4 0 200 400 CODE 600 800 1000
FIGURE 17. DIFFERENTIAL NONLINEARITY
FIGURE 18. INTEGRAL NONLINEARITY
10
HI5728 Typical Performance Curves, 5 Volt Power Supply
320 310 300 290 POWER (mW) 280 270 260 250 240 230 220 210 0 20 40 60 80 100 120
(Continued)
CLOCK RATE (MSPS)
FIGURE 19. POWER vs CLOCK RATE, fCLK /fOUT = 10, IOUT = 20mA
Typical Performance Curves, 3V Power Supply
80 75 70 0dBFS 65 60 -12dBFS 55 60 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 2 3 4 5 6 7 8 9 10 SFDR (dBc) 70 -12dBFS 65 -6dBFS 75 SFDR (dBc) -6dBFS 80 0dBFS
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
FIGURE 20. SFDR vs fOUT, CLOCK = 5MSPS
80 75 70 SFDR (dBc) 65 60 55 50 0 2 4 6 8 10 12 14 16 18 20 OUTPUT FREQUENCY (MHz) -6dBFS SFDR (dBc) -12dBFS 80
FIGURE 21. SFDR vs fOUT, CLOCK = 25MSPS
0dBFS 75 70 65 -12dBFS 60 55 50 45 -6dBFS
0dBFS
0
5
10
15
20
25
30
35
40
45
OUTPUT FREQUENCY (MHz)
FIGURE 22. SFDR vs fOUT, CLOCK = 50MSPS
FIGURE 23. SFDR vs fOUT, CLOCK = 100MSPS
11
HI5728 Typical Performance Curves, 3V Power Supply
80 0dBFS 75 70 SFDR (dBc) 65 60 55 50 45 SFDR (dBc) -6dBFS -12dBFS 75 50MSPS 70 100MSPS 65 125MSPS 60 55 50 0 5 10 15 20 25 30 35 40 45 50 45 -25
(Continued)
80 25MSPS
-20
-15
-10
-5
0
OUTPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
FIGURE 24. SFDR vs fOUT, CLOCK = 125MSPS
FIGURE 25. SFDR vs AMPLITUDE, fCLK /fOUT = 10
75
80 75 70 SFDR (dBc)
25MSPS 70 65 SFDR (dBc) 50MSPS 100MSPS 60 55 50 45 40 -25 50MSPS (6.75/7.25MHz) 100MSPS (13.5/14.5MHz) 125MSPS (16.9/18.1MHz) -20 -15 -10 -5 0 25MSPS (3.38/3.63MHz)
65 60 55 50 45 40 -25 -20 -15 -10 5MSPS
2
5A
ND
50
MS
PS
125MSPS
-5
0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
FIGURE 26. SFDR vs AMPLITUDE, fCLK /fOUT = 5
80 2.5MHZ 75 70 SFDR (dBc) 65 60 55 50 45 40MHZ 10MHZ 20MHZ
FIGURE 27. SFDR vs AMPLITUDE OF TWO TONES, fCLK/fOUT = 7
80 75 70 SFDR (dBc) 65 60 55 50 0dBFS SINGLE 45 -6dBFS SINGLE -6dBFS DIFF 0dBFS DIFF
2
4
6
8
10
12
14
16
18
20
0
5
10
15
20
25
30
35
40
IOUT (MA)
OUTPUT FREQUENCY (MHz)
FIGURE 28. SFDR vs IOUT, CLOCK = 100MSPS
FIGURE 29. DIFFERENTIAL vs SINGLE-ENDED, CLOCK = 100MSPS
12
HI5728 Typical Performance Curves, 3V Power Supply
80 75 70 10.1MHz SFDR (dBc) AMP (dB) 65 60 55 50 40.4MHz 45 40 -40 -20 0 20 40 60 80 -40 -50 -60 -70 -80 -90 -100 -110 0 5MHz/DIV FREQUENCY (MHz) 50 2.5MHz
(Continued)
-10 -20 -30 fCLK = 100MSPS fOUT = 9.95MHz AMPLITUDE = 0dBFS SFDR = 63dBc 14dB EXTERNAL ANALYZER ATTENUATION
TEMPERATURE (oC)
FIGURE 30. SFDR vs TEMPERATURE, CLOCK = 100MSPS
FIGURE 31. SINGLE TONE SFDR
-20 -30 -40 -50 AMP (dB) -60 -70 -80 -90 -100 -110 0 5MHz/DIV FREQUENCY (MHz) 50 fCLK = 100MSPS fOUT = 13.5/14.5MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 61.5dBc 14dB EXTERNAL ANALYZER ATTENUATION
-10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0.5 1.45MHz/DIV FREQUENCY (MHz) 15 fCLK = 100MSPS fOUT = 3.8,4.4,5.6,6.2MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 70.6dBc (IN A WINDOW)
FIGURE 32. TWO-TONE, CLOCK = 100MSPS
FIGURE 33. FOUR-TONE, CLOCK = 100MSPS
-20 -30 -40 -50 AMP (dB) -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV FREQUENCY (MHz) 20 fCLK = 100MSPS fOUT = 2.6, 3.2, 3.8, 4.4, 5.6, 6.2, 6.8MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 67.4dBc (IN A WINDOW)
-10 -20 -30 -40 AMP (dB) -50 -60 -70 -80 -90 -100 0 950kHz/DIV FREQUENCY (MHz) 10 fCLK = 50MSPS fOUT = 1.9, 2.2, 2.8, 3.1MHz COMBINED PEAK AMPLITUDE = 0dBFS SFDR = 74.2dBc (IN A WINDOW)
FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS
FIGURE 35. FOUR-TONE, CLOCK = 50MSPS
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HI5728 Typical Performance Curves, 3V Power Supply
0.4
(Continued)
0.4
0.2
LSB
LSB
0.2
0
0
-0.2
-0.2
-0.4 0 200 400 CODE 600 800 1000
-0.4 0 200 400 CODE 600 800 1000
FIGURE 36. DIFFERENTIAL NONLINEARITY
152 148 144 POWER (mW) 140 136 132 128 124 120 0 20 40 60 80
FIGURE 37. INTEGRAL NONLINEARITY
100
120
CLOCK RATE (MSPS)
FIGURE 38. POWER vs CLOCK RATE, fCLK /fOUT = 10, IOUT = 20mA
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HI5728 Timing Diagrams
CLK
50%
D9-D0 V
GLITCH AREA = 1/2 (H x W)
1 LSB ERROR BAND
HEIGHT (H)
IOUT WIDTH (W) tSETT tPD t(ps)
FIGURE 39. OUTPUT SETTLING TIME DIAGRAM
FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT METHOD
tPW2
tPW1
CLK
50%
tSU tHLD D9-D0
tSU tHLD
tSU tHLD
tPD
tSETT
IOUT
tPD
tSETT
tPD
tSETT
FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured
from the beginning of the output transition. The measurement was done by switching from code 0 to 256, or quarter scale. Termination impedance was 25 due to the parallel resistance of the output 50 and the oscilloscope's 50 input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. Singlet Glitch Area, is the switching transient appearing on the output during a code transition. It is measured as the area under the overshoot portion of the curve and is expressed as a Volt-Time specification. This is tested under the same conditions as `Output Settling Time.'
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HI5728
Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Full Scale Gain Drift, is measured by setting the data inputs to all ones and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (full scale range) per oC. Total Harmonic Distortion, THD, is the ratio of the DAC output fundamental to the RMS sum of the first five harmonics. Spurious Free Dynamic Range, SFDR, is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance load should be chosen such that the voltage developed does not violate the compliance range. Offset Error, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Offset Drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX. It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX. The units are ppm of FSR (Full Scale Range) per oC. Power Supply Rejection, is measured using a single power supply. Its nominal +5V is varied 10% and the change in the DAC full scale output is noted. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 of its original value. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. of equivalent current. The five LSBs are comprised of binary weighted current sources. Consider an input waveform to the converter which is ramped through all the codes from 0 to 1023. The five LSB current sources would begin to count up. When they reached the all high state (decimal value of 31) and needed to count to the next code, they would all turn off and the first major current source would turn on. To continue counting upward, the 5 LSBs would count up another 31 codes, and then the next major current source would turn on and the five LSBs would all turn off. The process of the single, equivalent, major current source turning on and the five LSBs turning off each time the converter reaches another 31 codes greatly reduces the glitch at any one switching point. In previous architectures that contained all binary weighted current sources or a binary weighted resistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worstcase transition points such as mid-scale and quarter scale transitions. By greatly reducing the amount of current switching at certain `major' transitions, the overall glitch of the converter is dramatically reduced, improving settling times and transient problems.
Digital Inputs And Termination
The HI5728 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. To minimize reflections, proper termination should be implemented. If the lines driving the clock(s) and digital inputs are 50 lines, then 50 termination resistors should be placed as close to the converter inputs as possible.
Ground Plane(s)
If separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. The same is true for the analog components and the analog ground plane. Refer to the Application Note on the HI5728 Evaluation Board for further discussion of the ground plane(s) upon availability.
Noise Reduction
To minimize power supply noise, 0.1F capacitors should be placed as close as possible to the converter's power supply pins, AVDD and DVDD. Also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for DVDD and to the analog ground for AVDD. Additional filtering of the power supplies on the board is recommended. See the Application Note on the HI5728 Evaluation Board for more information upon availability.
Detailed Description
The HI5728 is a dual, 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 330mW of power when using a +5V supply with the data switching at 100MSPS. The architecture is based on a segmented current source arrangement that reduces glitch by reducing the amount of current switching at any one time. The five MSBs are represented by 31 major current sources 16
Voltage Reference
The internal voltage reference of the device has a nominal value of +1.2V with a 60 ppm/ oC drift coefficient over the full
HI5728
temperature range of the converter. It is recommended that a 0.1F capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin (15) selects the reference. The internal reference can be selected if pin 15 is tied low (ground). If an external reference is desired, then pin 15 should be tied high (to the analog supply voltage) and the external reference driven into REFIO, pin 23. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, through operation below 2mA is possible, with performance degradation. If the internal reference is used, VFSADJ will equal approximately 1.16V (pin 22). If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT(Full Scale) is: IOUT (Full Scale) = (VFSADJ/RSET)x 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.16V) and a 1.86k RSET resistor, then the input coding to output current will resemble the following:
TABLE 1. INPUT CODING vs OUTPUT CURRENT (Per DAC) INPUT CODE (D9-D0) 11111 11111 10000 00000 00000 00000 IOUTA (mA) 20 10 0 IOUTB (mA) 0 10 20
These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 1). With the center tap grounded, the output swing of pins 16 and 17 will be biased at zero volts. It is important to note here that the negative voltage output compliance range limit is -300mV, imposing a maximum of 600mVP-P amplitude with this configuration. The loading as shown in Figure 1 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA.
50 PIN 17 (20) PIN 16 (21) IOUTB (QOUTB) 100 IOUTA (QOUTA) 50
V OUT = (2 x I OUT x R EQ)V
50
FIGURE 42.
VOUT = 2 x IOUT x REQ ,where REQ is ~12.5. Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. The 50 load on the output of the transformer represents the spectrum analyzer's input impedance.
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of -0.3V to 1.25V. RLOAD should be chosen so that the desired output voltage is produced in conjunction with the output full scale current, which is described above in the `Reference' section. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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