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Beyond Innovation Technology Co., Ltd.
BIT3193
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BIT3193
High Performance PWM Controller
Version 1.0
Notice Information contained in this document is believed to be accurate and reliable and subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Beyond Innovation Technology Co., Ltd. The information presented in this document does not form part of any quotation or contract. BiTEK is not liable for any consequence of the usage and/or application of the information contained therein. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
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This product is not designed for use in life support appliances, devices, or systems where malfunction of this product can reasonably be expected to result in personal injury. BiTEK customers' using or selling this product for May 31, 2005 use in such applications shall do so at their own risk and agree to fully indemnify BiTEK for any damage resulting from such improper use or sale.
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BIT3193
Contents
1. 2. Introduction.................................................................................................................................................1 BIT3193 functional description .................................................................................................................1 2.1. 2.2. 2.3. 2.4. 2.5.
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INN and CMP..............................................................................................................................2 Clock and ramp wave generator..............................................................................................3 LOAD Resistor vs. CTOSC Frequency....................................................................................3 Timing diagram..........................................................................................................................4 ISEN and Timer..........................................................................................................................5 Low frequency PWMOUT .........................................................................................................6 BIT3193 initial status ................................................................................................................8 Over voltage clamping..............................................................................................................8 Output driving circuit................................................................................................................9 Feedback scheme ...................................................................................................................10 ISEN protection circuit ........................................................................................................... 11 CLAMP protection circuit .......................................................................................................11 Fig. 1 BIT3193 block diagram .............................................................................................................2 Fig. 2 Error amplifier and modulation................................................................................................2
Fig. 3 The schematic of ramp wave generator .........................................................................................3 Fig. 4 The relationship of CTOSC and frequency .....................................................................................3
2.6. 2.7. 2.8. 2.9.
3.
Referenced external circuit design.........................................................................................................10 3.1. 3.2. 3.3.
List of Figures
Fig. 5 Connected a resistor in LOAD pin...........................................................................................4 Fig. 6 LOAD resistor vs. CTOSC frequency deviation .....................................................................4
Fig. 7 BIT3193 Modulation technique.......................................................................................................4 Fig. 8 ISEN and TIMER ............................................................................................................................5 Fig. 9 Delay time of ISEN.........................................................................................................................6 Fig. 10 The schematic associated with TIMER and ISEN..........................................................................6 Fig. 11 The schematic of Low frequency PWMOUT..................................................................................7 Fig. 12 MODE vs. PWMOUT.....................................................................................................................7 Fig. 13 PWMOUT maximum duty cycle limitation.....................................................................................8 Fig. 14 The scheme of over voltage clamping..........................................................................................9 Fig. 15 Delay of CLAMP protection..........................................................................................................9 Fig. 16 BIT3193 NOUT output driving circuit..........................................................................................10 Fig. 17 IC_VDD power circuit.................................................................................................................10 Fig. 18 Feedback scheme...................................................................................................................... 11 Fig. 19 ISEN protection scheme ............................................................................................................ 11 Fig. 20 Clamp circuit scheme ................................................................................................................12
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List of Tables
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Table 1 BIT3193 initial state ................................................................................................................8
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BIT3193
Edit by: Tim Yu &
BIT3193 Application note
Bill Huang
Abstract
BiTEK new developed BIT3193 general purpose PWM controller with a kind of two output signals with 180 degree out of phase. A built-in low frequency PWM generator makes the design job easy especially when you need it in the Latched-off functions, which are also built-in, make BIT3193 more reliable in system protection. A
application circuit.
Built-in soft-start function simplifies the peripheral circuit design and reduces inrush current when the system is
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starting-up.
The highly integrated design of BIT3193 get the both advantages of high performance and low price.
1. Introduction
General purposed PWM controllers developed in many specified application like switching power supply design are popular especially when designed for various topologies. They can increase the efficiency more comparing to the traditional Fly-back converters and Forward converters.
For various topologies of converter design, the output voltage feeds a voltage signal into the input of an error amplifier for comparing to the reference voltage, and then the error amplifier delivers an error signal by a compensation circuit. This error signal is modulated as PWM signal by comparing with a triangular wave. There are some logic
timing circuits to separate the phases of this PWM signal to have a dual-PWM-output to drive power switches of used power circuit. Beside the basic functions of feedback control in different converter design, some specific applications Such signal can be used as an indication
such as to use a DC/PWM transfer circuit without feedback are also popular. signal or simple ON/OFF control to other systems.
To avoid inrush current when the switching power been turned on, normally it needs a soft-start circuit.
The built-in This
soft-start function can reduce the number and rating of external components and increases the system reliability. specific function latches the designed system that can also avoid the more serious problems.
A Clamped circuit design
provides a fast response loop to reduce the output voltage when there is a high output voltage occurred in the initial stage. The Low power consumption by adopting CMOS process for controller provides the system higher efficiency.
2. BIT3193 functional description
Fig. 1 shows a block diagram of BIT3193. All of its detailed internal block diagrams show in following sections.
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BIT3193
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Fig. 1 BIT3193 block diagram
2.1. INN and CMP
The INN pin and the CMP pin are the input and output of the error amplifier in BIT3193, which is shown as Fig. 2. The PWM signal is generated when a triangular wave and a DC voltage feed into CMP_PWM. The error
amplifier has the job of compensation for the whole system in a close-loop design by accomplishing with a RC-network. The triangular wave is generated when a capacitor connected in CTOSC pin. About the basic
operation of error amplifier, the INN pin is worked to receive the feedback signal then compare it with an internal 1.25V reference voltage in the error amplifier (ERR_AMP). The error amplifier works as both a comparator and The tolerance of 1.25V
a compensator when a RC-network connected between its output pin and INN pin. reference voltage in BIT3193 is designed as O 3%.
RC-Network
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Fig. 2 Error amplifier and modulation
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2.2. Clock and ramp wave generator
A capacitor is connected in CTOSC pin, which can produce a triangular wave; the frequency of this wave is also called the oscillation frequency, shown as Fig. 3. Comparing with 0.5V and 2.25V, the two current sources The relationship of frequency and
charged and discharged then generate the necessary triangular wave. capacitor value is shown as Fig. 4.
In addition, BIT3193 is a two output signals with 180 degree out of phase
and its triangular frequency is double of its output frequency.
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250.00 200.00 Frequency(KHz) 150.00 100.00 50.00
0.5V
+ -
CTOSC VS. Frequency
2.25V
+
CTOSC
0.00 300
500
700
900 CTOSC(pF)
1100
1300
1500
Fig. 3 The schematic of ramp wave generator
Fig. 4 The relationship of CTOSC and frequency
The generated frequency can be referred as following equation:
FHFPWM = K HF , K HF = 8.2e - 5 CCTOSC
If the required frequency is 50kHz, the selected triangular wave frequency is 100kHz, therefore we can know:
100kHz = 8.2e - 5 CCTOSC
And choose a 820pF capacitor and connect it to CTOSC pin. In addition, considering about temperature factor and the tolerance of capacitor, to choose the NPO type with O 5% tolerance so as to meet the requirement,O 8% design specification, because of the O 3% frequency tolerance of BIT3193. For a 50 KHz frequency design, the maximum tolerance of O 8% equals O 4KHz.
2.3. LOAD Resistor vs. CTOSC Frequency
BIT3193 supports the higher start-up frequency when a resistor connected to its LOAD pin, shown as Fig 5. The function of LOAD pin is related to ISEN pin. When the voltage of ISEN pin is lower than 1.3V, the internal
O B When the switch (connected to LOAD pin) is "closed" that makes BIT3193 generate a higher start-up frequency.i T E K
voltage of ISEN pin is higher than 1.3V, the internal switch connected is "opened" that makes BIT3193 generate a normal operation frequency. 6. The relationship of LOAD resistor and CTOSC frequency deviation is shown as Fig.
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BIT3193
LOAD Resistor VS. CTOSC Frequency Deviation
1:1
0.75V
200.00 175.00 150.00 Frequency evaoin Dit (KHz) 125.00 100.00 75.00 50.00 25.00 0.00 0 173.30 151.10 126.50 108.70 91.40 76.20 63.50 54.40 45.70 38.70
ISEN LOAD CTOSC
CTOSC
32.10 26.80
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20
40
60
80
100
LOAD Resisor (Kohm)
Fig. 5 Connected a resistor in LOAD pin
Fig. 6 LOAD resistor vs. CTOSC frequency deviation
The equation of deviation is shown as following equation:
Fn = F100KHz x Fn 100 KHz
When CTOSC is in 100KHz and the start-up frequency is 140KHz, G Fn will be 40KHz and the resistor connected to LOAD will be 51K.
2.4. Timing diagram
The output PWM signal is accomplished by comparing the ramp wave and the output of error amplifier (CMP_PWM OUT). The ramp wave is generated in CTOSC pin when a capacitor is connected here; its The Delay elements and AND logics feed the PWM signal of
frequency is determined by the capacitor. CMP_PWM into NOUT1 and NOU2. time is needed and must be enough.
To avoid a short circuit happened between NOUT1 and NOUT2, the delay
E rr _ A m p O u tp u t R a m p W a ve C M P _ PW M O utp ut 1 /2 F C lo c k N OU T1 N OU T2
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D e la y D e la y D e la y

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Fig. 7 BIT3193 Modulation technique
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2.5. ISEN and Timer
The TIMER pin is charged by an internal current source when an external capacitor is connected to this pin. The timing chart is shown as Fig. 8. Firstly, the ON/OFF input voltage of BIT3193 is higher than 1V, the voltage
of TIMER pin is lower than 0.5V and there is no signal input on ISEN pin, the period in above conditions is called "Turn on delay time". During the "Turn on delay time" there is no signal for NOUT output. Secondly, TIMER pin
increases its charged voltage to make NOUT enable until it is in 2.5V.
Thirdly, because there is no signal fed into
ISEN, BIT3193 will count 32 cycles based on CTPWM cycle time then shut itself down when the voltage of
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TIMER pin is higher than 2.5V.
NOUT 2.5V
0.5V 0.3V Timer ON/OFF ISEN 1V 1V
Turn On Delay Time
CTPWM 32cycle Latch Off Time
Fig. 8 ISEN and TIMER
Fig. 9 is another condition when the voltage of TIMER pin is higher than 2.5V, NOUT has normal output and ISEN detects a signal, which is higher than 1.3V in its first state. and becomes low. The second state is that ISEN detects nothing
This condition will not shut BI3193 down immediately because it assumes this condition
maybe caused by noise, then the internal counter of BIT3193 begins to count 32 cycles. If the voltage of ISEN pin is still lower than 1.3V after 32 cycles then BIT3193 will shut itself down.
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BIT3193
NOUT 4V Timer 2.5V
ISEN CTPWM
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1.3V
32cycle
Fig. 9 Delay time of ISEN
The realized circuit is shown as Fig. 10.
The two comparators compare TIMER pin voltage and ISEN pin
voltage to 2.5V and 1.3V respectively. After delayed 32 cycles, the Latch Circuit may decide to disable BIT3193.
Besides, BIT3193 offers ON/OFF pin to turn on/off itself when there is an input voltage higher than 1V, shown as Fig. 10. There is a built-in 80K resistor connected to ground in ON/OFF pin and engineers need to pay
attention more about the load effect of it. When IC supplied voltage is 5V and a 200K resistor connects to ON/OFF pin, an about 1.42V voltage in this pin may turn on BIT3193. Such kind of turn-on/off circuit needs a
paralleled capacitor connected here to avoid the noise interference in this pin. When start up BIT3193 by turning on its ON/OFF pin, all of IC's internal functions will be reset to ensure all the parameters in initial states. initial states are built when the voltage of TIMER pin is between 0V and 0.3V. These
Tim er 2.5 V
+ -
1.3 V
+
VDD
Lat sh Cir cuit
80K? 5%
To All Circuit
ISEN
ON/OFF
Fig. 10 The schematic associated with TIMER and ISEN
2.6.
Low frequency PWMOUT
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The frequency of triangular
The realized circuit of low frequency PWMOUT with polarity selection is shown as Fig. 31, 2005 maximum May 11. The voltage and minimum voltage of triangular wave are 2.5V and 0.5V respectively. wave is controlled by the capacitor connected to CTPWM pin and the dutyDCC PWMOUT is controlled by cycle of CONTROLLED PWMDC voltage level.
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Finally, the signal voltage level of MODE controls the polarity of PWMOUT.
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BIT3193
MODE PWM OUT PWMOUT Output Control Circuit PWM DC
ISE N
Low Frequ ency P WM Generator 220 HZ 2.5 V 1V INN
+
FB
CTPWM CMP
+ -
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2.25V 0.5V
1.2 5V
50K HZ
Fig. 11 The schematic of Low frequency PWMOUT
The PWMOUT pin generates a low frequency PWM signal when the level of ISEN is higher than 1.3V, shown as Fig. 12. The duty cycle of PWMOUT is proportional to PWMDC when MODE pin is connected to ground. In
the other side, the duty cycle of PWMOUT is inverse proportional to PWMDC when MODE pin is connected to a logic high level (e. g. IC_VDD). When a 0.022uF capacitor is selected to connect to CTPWM pin that can produce the frequency about 220Hz. To choose X7R type of capacitors can avoid frequency from drafted when
environmental temperature is changed.
CTPWM PWMDC
ISEN
1.3V
PWMOUT(MODE="0") PWMOUT(MODE="1")
Fig. 12 MODE vs. PWMOUT
For the proportional relationship of PWMOUT duty cycle and PWMDC, when MODE is selected to logic "0" then PWMOUT has the maximum duty cycle limitation of 92%, shown as Fig. 13.
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BIT3193
CTPWM
PWMDC
ISEN PWMOUT
1.3V
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92%
Fig. 13 PWMOUT maximum duty cycle limitation
2.7. BIT3193 initial status
Shown in Table 1 are initial states of BIT3193 when it is powered on. During the initial state, there will be a 60uA current flows into INN pin, the error amplifier input in BIT3193, to make the output of error amplifier as the low level. Output pins of NOUT1 and NOUT2 are in the same level with ground and two frequency generators,
high triangular wave and low frequency triangular wave, have normal oscillation signals.
Table 1 BIT3193 initial state
P in N u m b e r P in N a m e S tatu s
1 4 8 9 11 12
IN N C TO SC NO U T1 NO U T2 PW MOUT C TPW M
F o r c e to V D D ( W ith ~ 6 0 u A c u r r e n t so u r c e ) N o r m a lly r u n F o r c e d to G N D F o r c e d to G N D F lo a tin g N o r m a lly r u n
2.8.
Over voltage clamping
The internal circuit of CLAMP pin in BIT3193 is designed by comparing with 2V, shown as Fig. 14. When a signal voltage higher than 2Vwhich feeds to CLAMP pin then the internal switch will be turned on to let the 60uA current flow to INN pin to increase the potential level of INN pin and reduces Othe potential level of CMP, hence K B i T E the NOUT duty cycle will be reduced.
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BIT3193
60uA
CLAMP TIME_INI
INN
+
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Rs 1.25V
2.25V 0.5V
Fig. 14 The scheme of over voltage clamping
Another function of CLAMP pin is shown as Fig. 15. When voltage level of ISEN pin is higher than 2.5V then NOUT has PWM output and CLAMP level is higher than 2V (e. g. 2.5V). counting 14 cycles based on CTOSC frequency. BIT3193 will shut down its output after
2.5V 1.5V
NOUT
CTOSC
14 CYCLES
Fig. 15 Delay of CLAMP protection
2.9.
Output driving circuit
NOUT of BIT3193 is controlled by PWMOUT, protection circuit and ON/OFF associated by an AND gate,
shown as Fig. 16. The output PWM signal level is IC_VDD and ground by its output driving MOSFET circuit.
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-
CMP
+ -
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VDD
BIT3193
O N /O F F P ro te c t C irc u it PW M O UT
NOUT
Fig. 16 BIT3193 NOUT output driver
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3. Referenced external circuit design
There will be some referenced external circuit designs for BIT3193 in following sections. recommended and matched to the characteristics of BIT3193. They are
The working voltage range of BIT3193 is 4.5V~8V and recommended operation voltage is 6.5V. When the input voltage is lowed than the UVLO voltage (3.8V) of BIT3193, it will be shut down. When input voltage of
BIT3193 is higher than UVLO (4V) and the input of ON/OFF pin is higher than 1V, then BIT3193 will be turned on. Fig. 17 is a fixed input voltage design, like a LDO, to supply stable voltage to BIT3193 when the system input voltage is fluctuant. This regulator circuit needs to be designed carefully to supply enough input voltage to
BIT3193, also the power rating of R2 and D1 need to be considered when they operate at maximum input voltage. The capacitor C3 used in this voltage regulator should be large enough to avoid high voltage ripple occurred in BIT3193 VDD pin.
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Fig. 17 IC_VDD power circuit

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3.1. Feedback scheme
The current sensing and feedback control circuit is shown as Fig. 18that the load is operated at
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BIT3193
LOAD
Vs
D3 R9 866
INN
+
Is 1.25V
CMP
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Fig. 18 Feedback scheme
The load current can be learned as following equation:
IS = VS R9
VD 1.25V + 2 x VS = 2
When R9 is 866 , the lamp current is about 4.1mA
3.2. ISEN protection circuit
ISEN pin is used as an alternative current detection circuit by connecting a resistor (R9) and a diode (D3), shown as Fig. 7. In this circuit, R8, R10 and C8 are a low-pass filter worked for filtering the ripple voltage of
ISEN pin when there is a normal operation alternative current. When open-load is happened, ISEN pin voltage is lower than 1.3V, and TIMER pin is higher than 2.5V after CTPWM counts over 32 cycles, then BIT3193 assumes it is operated under open-load condition and shut down itself.
LOAD
FB
R8 ISEN R10 1 2 D3 3 R9
Is
C8
Fig. 19 ISEN protection scheme
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3.3. CLAMP protection circuit
high voltage to damage itself.
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CLAMP used as the over voltage protection function that can avoid the transformer provides an unexpected The referenced alternative voltage clamping circuit is shown as Fig. 20.
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BIT3193
transformer output voltage is divided by capacitors C2 and C3 then feeds to CLAMP pin by a rectifier diode D2.
Fig. 20 Clamp circuit scheme
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The clamped voltage is calculated by following equations.
VA( P - P ) = VC x 2VD
VCLAMP ( P - P ) = VA( P - P ) x X C 2 + X C3 X C3
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