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PHD/PHU77NQ03T N-channel TrenchMOS FET Rev. 01 -- 28 November 2006 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features I Fast switching I Low thermal resistance 1.3 Applications I DC-to-DC converters I Computer motherboard 1.4 Quick reference data I VDS 25 V I RDSon 9.5 m I ID 75 A I QGD = 3.2 nC (typ) 2. Pinning information Table 1. Pin 1 2 3 mb Pinning Description gate (G) drain (D) source (S) mounting base; connected to drain (D) 2 1 3 1 2 3 G mbb076 Simplified outline [1] Symbol mb mb D S SOT428 (DPAK) [1] It is not possible to make a connection to pin 2 of the SOT428 package. SOT533 (IPAK) NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 3. Ordering information Table 2. Ordering information Package Name PHD77NQ03T PHU77NQ03T DPAK IPAK Description plastic single-ended surface-mounted package; 3 leads (one lead cropped) plastic single-ended package; 3 leads (in-line) Version SOT428 SOT533 Type number 4. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage drain-gate voltage (DC) gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C Tmb = 25 C; pulsed; tp 10 s unclamped inductive load; ID = 32 A; tp = 0.17 ms; VDS 25 V; RGS = 50 ; VGS = 10 V; starting at Tj = 25 C Tmb = 25 C; VGS = 10 V; see Figure 2 and 3 Tmb = 100 C; VGS = 10 V; see Figure 2 Tmb = 25 C; pulsed; tp 10 s; see Figure 3 Tmb = 25 C; see Figure 1 Conditions 25 C Tj 175 C 25 C Tj 175 C; RGS = 20 k Min -55 -55 Max 25 25 20 75 55.9 240 107 +175 +175 75 240 100 Unit V V V A A A W C C A A mJ Source-drain diode Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 2 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 120 Pder (%) 80 03aa16 120 Ider (%) 80 003aab282 40 40 0 0 50 100 150 Tmb (C) 200 0 0 50 100 150 200 Tmb (C) P tot P der = ----------------------- x 100 % P tot ( 25C ) Fig 1. Normalized total power dissipation as a function of mounting base temperature 103 ID (A) Limit RDSon = VDS / ID ID I der = ------------------- x 100 % I D ( 25C ) Fig 2. Normalized continuous drain current as a function of mounting base temperature 003aab283 tp = 10 s 10 2 100 s DC 10 1 ms 1 1 10 VDS (V) 102 Tmb = 25 C; IDM is single pulse Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 3 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 5. Thermal characteristics Table 4. Rth(j-mb) Rth(j-a) Thermal characteristics Conditions Min [1] [1] Symbol Parameter thermal resistance from junction to ambient SOT428 SOT533 [1] Mounted on a printed-circuit board; vertical in still air. Typ 75 50 70 Max 1.4 - Unit K/W K/W K/W K/W thermal resistance from junction to mounting base see Figure 4 minimum footprint SOT404 minimum footprint vertical in free air - 10 Zth(j-mb) (K/W) 1 003aab284 = 0.5 0.2 0.1 0.05 0.02 single pulse tp t T P = tp T 10-1 10-2 10-5 10-4 10-3 10-2 10-1 tp (s) 1 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 4 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 6. Characteristics Table 5. Characteristics Tj = 25 C unless otherwise specified. Symbol Parameter Static characteristics V(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V Tj = 25 C Tj = -55 C VGS(th) gate-source threshold voltage ID = 1 mA; VDS = VGS; see Figure 9 and 10 Tj = 25 C Tj = 175 C Tj = -55 C IDSS drain leakage current VDS = 25 V; VGS = 0 V Tj = 25 C Tj = 175 C IGSS RG RDSon gate leakage current gate resistance drain-source on-state resistance VGS = 20 V; VDS = 0 V f = 1 MHz VGS = 10 V; ID = 25 A; see Figure 6 and 8 Tj = 25 C Tj = 175 C Dynamic characteristics QG(tot) QGS QGS1 QGS2 QGD VGS(pl) QG(tot) Ciss Coss Crss Ciss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge pre-VGS(th) gate-source charge post-VGS(th) gate-source charge gate-drain charge gate-source plateau voltage total gate charge input capacitance output capacitance reverse transfer capacitance input capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 25 A; VGS = 0 V; see Figure 13 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V VGS = 0 V; VDS = 0 V; f = 1 MHz VDS = 12 V; RL = 0.5 ; VGS = 10 V; RG = 5.6 ID = 0 A; VDS = 0 V; VGS = 4.5 V VGS = 0 V; VDS = 12 V; f = 1 MHz; see Figure 14 ID = 25 A; VDS = 12 V; VGS = 10 V; see Figure 11 and 12 17.1 6 3.2 2.8 3.2 5 6.2 860 400 165 1200 8.3 7.6 24.8 6.6 0.9 34 12.5 1.2 nC nC nC nC nC V nC pF pF pF pF ns ns ns ns V ns nC 8.3 15 9.5 17.1 m m 1.2 10 500 100 A A nA 2.1 1.35 2.65 3.2 3.65 V V V 25 25 V V Conditions Min Typ Max Unit Source-drain diode PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 5 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 80 VGS (V) = 10 ID (A) 60 003aab285 8 7 20 RDSon (m) VGS (V) = 5.2 003aab286 5.6 6 6 5.6 15 7 40 5.2 4.8 10 8 10 20 4.4 4 3.8 0 0.2 0.4 0.6 0.8 VDS (V) 1 5 0 0 0 20 40 60 ID (A) 80 Tj = 25 C Tj = 25 C Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 80 ID (A) 60 003aab287 Fig 6. Drain-source on-state resistance as a function of drain current; typical values 2 a 1.5 03af18 40 1 20 Tj = 150 C 25 C 0.5 0 0 2 4 6 VGS (V) 8 0 -60 0 60 120 Tj (C) 180 Tj = 25 C and 175 C; VDS > ID x RDSon R DSon a = ----------------------------R DSon ( 25C ) Fig 8. Normalized drain-source on-state resistance factor as a function of junction temperature Fig 7. Transfer characteristics: drain current as a function of gate-source voltage; typical values PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 6 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 4 VGS(th) (V) 3 typ min 2 003aab303 10-3 ID (A) min 10-4 typ 003aab304 max max 10-5 1 0 -60 10-6 0 60 120 Tj (C) 180 0 1 2 3 VGS (V) 4 ID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V Fig 9. Gate-source threshold voltage as a function of junction temperature 10 VGS (V) 8 12 V 6 VDS = 19 V ID = 25 A Tj = 25 C 003aab288 Fig 10. Sub-threshold drain current as a function of gate-source voltage VDS ID VGS(pl) 4 VGS(th) 2 VGS QGS1 QGS2 QGD QG(tot) 003aaa508 0 0 4 8 12 16 20 QG (nC) QGS ID = 25 A; VDS = 12 V and 19 V Fig 11. Gate-source voltage as a function of gate charge; typical values Fig 12. Gate charge waveform definitions PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 7 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 80 IS (A) 60 003aab289 104 003aab290 C (pF) 40 103 Ciss 20 Coss 150 C Tj = 25 C Crss 0 0.2 0.4 0.6 0.8 1 1.2 VSD (V) 102 10-1 1 10 VDS (V) 102 Tj = 25 C and 175 C; VGS = 0 V VGS = 0 V; f = 1 MHz Fig 13. Source current as a function of source-drain voltage; typical values Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 003aab291 104 C (pF) Ciss 103 Crss 102 10-1 1 VGS (V) 10 VGS = 0 V; f = 1 MHz Fig 15. Input and reverse transfer capacitances as a function of gate-source voltage; typical values PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 8 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 7. Package outline Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped) SOT428 y E b2 A A1 A E1 mounting base D1 HD D2 2 L2 1 3 L L1 b1 e e1 b w M A c 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 b1 1.1 0.9 b2 5.46 5.00 c 0.56 0.20 D1 6.22 5.98 D2 min 4.0 E 6.73 6.47 E1 min 4.45 e 2.285 e1 4.57 HD 10.4 9.6 L 2.95 2.55 L1 min 0.5 L2 0.9 0.5 w 0.2 y max 0.2 OUTLINE VERSION SOT428 REFERENCES IEC JEDEC TO-252 JEITA SC-63 EUROPEAN PROJECTION ISSUE DATE 06-02-14 06-03-16 Fig 16. Package outline SOT428 (DPAK) PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 9 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET Plastic single-ended package (IPAK); 3 leads (in-line) SOT533 E E1 A1 A D1 mounting base D2 L1 Q L 1 2 3 e1 e b w M c 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 2.38 2.22 A1 0.93 0.46 b 0.89 0.71 c 0.56 0.46 D1 1.10 0.96 D2 6.22 5.98 E 6.73 6.47 E1 e e1 L 9.6 9.2 L1 (2) max 2.7 Q 1.1 1.0 w 0.3 2.285 5.21 4.57 5.00 BSC (1) BSC (1) Notes 1. Basic spacing between centers. 2. Terminal dimensions are uncontrolled within zone L1. OUTLINE VERSION SOT533 REFERENCES IEC JEDEC TO-251 JEITA EUROPEAN PROJECTION ISSUE DATE 05-02-11 06-02-14 Fig 17. Package outline SOT533 (IPAK) PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 10 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 8. Revision history Table 6. Revision history Release date 20061128 Data sheet status Product data sheet Change notice Supersedes Document ID PHD_PHU77NQ03T_1 PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 11 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 9.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com PHD_PHU77NQ03T_1 (c) NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 -- 28 November 2006 12 of 13 NXP Semiconductors PHD/PHU77NQ03T N-channel TrenchMOS FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 11 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2006. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 November 2006 Document identifier: PHD_PHU77NQ03T_1 |
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