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SSM9585GM P-channel Enhancement-mode Power MOSFET Simple drive requirement Lower gate charge Fast switching characteristics Pb-free; RoHS compliant. D BVDSS R DS(ON) ID -80V 180m -2.7A G S DESCRIPTION D Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM9585GM is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications. This device is suitable for low voltage applications such as DC/DC converters. D D D G SO-8 S S S ABSOLUTE MAXIMUM RATINGS Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating -80 25 -2.7 -2.1 -20 2.5 0.02 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range THERMAL DATA Symbol Rj-a Parameter Maximum Thermal Resistance Junction-ambient 3 Value 50 Unit C/W 3/21/2005 Rev.2.01 www.SiliconStandard.com 1 of 5 SSM9585GM ELECTRICAL CHARACTERISTICS (at Tj = 25C, unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=-250uA 2 Min. -80 -1 - Typ. -0.07 5 18 5 7 10 6 67 30 140 98 Max. Units 180 200 -3 -1 -25 100 28 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=-1mA Static Drain-Source On-Resistance VGS=-10V, ID=-2.7A VGS=-4.5V, ID=-2.5A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25oC) Drain-Source Leakage Current (Tj=70oC) VDS=VGS, ID=-250uA VDS=-10V, ID=-2.7A VDS=-80V, VGS=0V VDS=-64V, VGS=0V VGS=25V ID=-2.7A VDS=-64V VGS=-4.5V VDS=-40V ID=-1A RG=3.3 , VGS=-10V RD=40 VGS=0V VDS=-25V f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 2 1790 2860 SOURCE-DRAIN DIODE Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=-2A, VGS=0V IS=-2.7A, VGS=0V, dI/dt=100A/s Min. - Typ. 80 320 Max. Units -1.2 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by maximum junction temperature. 2.Pulse width <300us, duty cycle <2%. 3.Surface-mounted on 1 in2 copper pad on FR4 board; 125C/W when mounted on minimum copper pad. 3/21/2005 Rev.2.01 www.SiliconStandard.com 2 of 5 SSM9585GM 40 30 35 T A = 25 o C -ID , Drain Current (A) 30 -ID , Drain Current (A) -10V -6.0V -5.0V -4.5V TA=150oC 25 -10V -6.0V -5.0V -4.5V 20 25 20 15 15 10 10 V G = -3.0 V 5 5 V G = -3.0 V 0 0 4 8 12 16 20 0 0 2 4 6 8 10 12 14 -V DS , Drain-to-Source Voltage (V) -V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 150 2.2 145 I D = -2.5 A T A =25C Normalized R DS(ON) 2.0 1.8 I D = -2.7 A V G =-10V 1.6 RDS(ON) (m ) 140 1.4 1.2 135 1.0 0.8 130 0.6 125 0.4 3 4 5 6 7 8 9 10 11 -50 0 50 100 150 -V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 6 2.5 4 2 -VGS(th) (V) 1.4 -IS(A) T j =150 o C 2 T j =25 o C 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 0 -50 0 50 100 150 -V SD , Source-to-Drain Voltage (V) T j , Junction Temperature ( C) o Fig 5. Forward Characteristic of Reverse Diode 3/21/2005 Rev.2.01 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9585GM 12 10000 f=1.0MHz -VGS , Gate to Source Voltage (V) 10 I D = -2.7A V DS = -64V C iss 8 1000 6 C (pF) 4 100 C oss C rss 2 0 0 10 20 30 40 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) -V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 Duty factor=0.5 Normalized Thermal Response (Rthja) 0.2 10 0.1 0.1 1ms -ID (A) 1 0.05 0.02 10ms 100ms 0.1 0.01 PDM 0.01 Single Pulse t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=125C/W T A =25 o C Single Pulse 1s DC 10 100 1000 0.01 0.1 1 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 -V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VDS 90% VG QG -4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform 3/21/2005 Rev.2.01 Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9585GM Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 3/21/2005 Rev.2.01 www.SiliconStandard.com 5 of 5 |
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