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| 19-4598; Rev 1; 7/09 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System General Description The MAXQ7667 smart system-on-a-chip (SoC) provides a time-of-flight ultrasonic distance-measuring solution. The device is optimized for applications involving large distance measurement with weak input signals or multiple target identification. The MAXQ7667 features high signalto-noise ratio achieved by combining flexible electronics with the intelligence necessary to optimize each function as environmental and target conditions change. An integrated burst signal generator and echo reception components process ultrasonic signals between 25kHz and 100kHz. Echo reception components include a programmable gain low-noise amplifier (LNA), a 16-bit sigma-delta ADC to digitize the received echo signals, and digital signal processing (DSP). DSP limits noise with a bandpass filter, and creates an echo envelope through demodulation and lowpass filtering. Input referred noise is a low 0.7V RMS . A programmable phase-locked loop (PLL) frequency synthesizer supplies the reference frequency for the burst generator and the clock for the echo receiver's digital filter. An embedded 16-bit MAXQ20 microcontroller (C) controls all the preceding functions. The C optimizes the burst frequency and reception frequency for each transmission at any temperature. The MAXQ7667 achieves smart sensing by monitoring the echo signals and then actively changing the transmitted and received parameters to obtain optimum results. Digital filtering and burst synthesis do not require CPU intervention. This leaves all the CPU power available for echo optimization, communication, diagnostics, and additional signal processing. The MAXQ7667 operates with three different power supply voltages: +5V, +3.3V, and +2.5V. Two internal linear regulators allow operation from a single +5V supply when three external power supplies are not available. Alternatively, the MAXQ7667 can control an external pass transistor to allow operation from a single supply voltage of +8V to +65V or more, depending on the external component tolerance. The device is available in a 48-pin LQFP package and is specified to operate from -40C to +125C. Features o Smart Analog Peripherals Dedicated Ultrasonic Burst Generator Echo Receiving Path (Includes LNA, SigmaDelta ADC) 5-Channel, 12-Bit SAR ADC with 250ksps Sampling Rate Internal Bandgap Voltage Reference for the ADCs (Also Accepts External Voltage Reference) o Timer/Digital I/O Peripherals o High-Performance, Low-Power, 16-Bit RISC Core o Program and Data Memory o Crystal/Clock Module o 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock Cycle o Power-Management Module o JTAG Interface o Universal Asynchronous Receiver-Transmitter (UART) o Local Interconnect Network (LIN) See the Detailed Features section for complete list of features. MAXQ7667 Ordering Information PART MAXQ7667AACM/V+ PIN-PACKAGE 48 LQFP RAM (KB) 4 FLASH (KB) 32 Note: All devices are specified over the -40C to +125C operating temperature range. /V denotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. Applications Automotive Parking Vehicle Security Industrial Processing Automation Handheld Devices Pin Configuration appears at end of data sheet. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: ww.maxim-ic.com/errata. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 ABSOLUTE MAXIMUM RATINGS DVDDIO, GATE5, REG3P3, REG2P5 to DGND ................................................................-0.3V to +6.0V AVDD to AGND .....................................................-0.3V to +4.0V DVDD to DGND .....................................................-0.3V to +3.0V DVDDIO to DVDD..................................................-0.3V to +6.0V AVDD to DVDD......................................................-0.3V to +4.0V AGND to DGND.....................................................-0.3V to +0.3V Digital Inputs/Outputs to DGND..........-0.3V to (VDVDDIO + 0.3V) Analog Inputs/Outputs to AGND ............-0.3V to (VAVDD + 0.3V) XIN, XOUT to DGND ..............................-0.3V to (VDVDD + 0.3V) Maximum Current into Any Pin............................................50mA Continuous Power Dissipation (TA = +70C) 48-Pin LQFP (derate 21.7mW/C above +70C).....1739.1mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER Input-Referred Noise (Note 1) Minimum Detectable Signal SYMBOL CONDITIONS VGA gain adjust = 1.55VP-P/LSB VGA gain adjust = 0.1V P-P/LSB VGA gain adjust = 1.55VP-P/LSB VGA gain adjust = 0.1V P-P/LSB VGA gain adjust = 1.55VP-P/LSB, unclipped Operating Input Range VGA gain adjust = 0.1V P-P/LSB, unclipped VGA gain adjust From echo input to = 1.55V /LSB P-P bandpass filter in VGA gain adjust reply to input = 0.1V P-P/LSB (Note 2) 6.7 1.55 VP-P/LSB 0.1 10 150 80 x fBPF 10 x fBPF 16 RIN For each echo input 14 14 VAVDD/2 Recover from 2VP-P input 10 % kHz kHz kHz Bits k pF V s MIN TYP 5.6 0.7 80 10 100 mVP-P MAX UNITS ECHO INPUT (Low-Noise Amplifier and Sigma-Delta ADC) VRMS VP-P Programmable Gain Programmable-Gain Adjust Resolution LNA Bandwidth ADC Sampling Rate ADC Output Data Rate ADC Output Data Resolution Echo-Input Resistance Echo-Input Capacitance Echo-Input DC Bias Voltage Maximum Overvoltage Recovery Time 2 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER BANDPASS FILTER Center Frequency Passband Width Minimum Stopband Rejection Output Data Rate Output Data Resolution LOWPASS FILTER Corner Frequency Rolloff Output Data Rate Output Data Resolution SAR ADC Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Offset-Error Drift Gain Error Gain-Error Temperature Coefficient Input-Referred Noise Differential Input Range Absolute Input Range Input Leakage Current Conversion Time Input Capacitance Track-and-Hold Acquisition Time Turn-On Time Conversion Clock Conversion Rate fADCCLK fADCCLK = 4MHz (not production tested) Three ADCCLK cycles at 2MHz Eight ADCCLK cycles at 2MHz 0.5 13 ADCCLK cycles at 2MHz 14 1.5 4 4 250 At ADC inputs Unipolar Bipolar 0 -VREF/2 0 0.1 6.5 0.4 400 VREF +VREF/2 VAVDD Measurement No missing codes Tested at 125ksps Tested at 125ksps -2 1 5 1 12 11 1 2 +2 3 Bits LSB LSB mV V/C % ppmFS/C VRMS V V A s pF s s MHz ksps fLPF -3dB 0.1 x fBPF 40 5 x fBPF 16 kHz dB/Decade ksps Bits fBPF -3dB One decade away from center frequency 25 0.14 x fBPF -60 10 x fBPF 16 100 kHz kHz dB ksps Bits SYMBOL CONDITIONS MIN TYP MAX UNITS MAXQ7667 _______________________________________________________________________________________ 3 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER REFERENCE BUFFER Offset Minimum Load Output Bypass Capacitor EXTERNAL VOLTAGE REFERENCE (Reference Buffer Disabled) Reference Input Range Reference Input Impedance Applied at REF Measured at REF with the SAR and sigma-delta ADCs running at maximum frequency 1.0 50 VAVDD V k 2.5 0.47 5 mV k F SYMBOL CONDITIONS MIN TYP MAX UNITS INTERNAL VOLTAGE REFERENCE (REFBG) Initial Accuracy Maximum Temperature Coefficient Output Impedance Power-Supply Rejection Ratio Output Noise PROGRAMMABLE BURST-FREQUENCY OSCILLATOR Burst-Frequency Range Burst-Frequency Resolution Burst-Frequency Locking Time CRYSTAL OSCILLATOR Tested crystal frequency Frequency Range Temperature Stability Startup Time XIN Input Low Voltage XIN Input High Voltage INTERNAL RC OSCILLATOR Frequency Initial Accuracy Temperature Drift Supply Rejection TA = TMIN to TMAX VDVDD = 2.25V to 2.75V 13.5 10.5 700 -1.5 MHz % ppm % Minimum crystal frequency External clock input Excluding crystal 16MHz crystal When driven with external clock source When driven with external clock source 0.7 x VDVDD 4 25 10 0.3 x VDVDD 16 4 16 ppm/C ms V V MHz Change from 40kHz to 60kHz Change from 50kHz to 50.5kHz 0.025 0.1 5 2 1.335 MHz % ms VAVDD = 3.0V to 3.6V 2.45 2.5 100 1.1 60 0.5 2.55 V ppm/C k dB mVRMS 4 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER Adjustable Frequency Range Frequency Adjustment Resolution SUPPLY VOLTAGE SUPERVISORS DVDD Reset Threshold DVDD Interrupt Threshold Minimum Reset and Interrupt Threshold Difference AVDD Interrupt Threshold DVDDIO Interrupt Threshold Supervisor Operating Range Supervisor Hysteresis RESET Release Delay After VDVDD rises above the reset threshold Time from RESET is released to the execution of the first instruction (serial bootloader off) Generates an interrupt if VAVDD falls below this threshold Generates an interrupt if VDVDDIO falls below this threshold At DVDD Asserts RESET if VDVDD falls below this threshold Generates an interrupt if VDVDD falls below this threshold 2.10 2.25 150 2.95 4.5 1.5 1 35 3.15 4.75 2.75 2.25 2.38 V V mV V V V % s SYMBOL CONDITIONS Using the RCTRM register MIN -40 0.2 TYP MAX +40 UNITS % % MAXQ7667 Power-Up Time 1 s +5V LINEAR REGULATOR (DVDDIO, GATE5, Requires External Pass Transistor, see the Typical Application Circuit/Functional Diagram) Regulator Output Voltage GATE5 Output High Voltage GATE5 Output Low Voltage GATE5 Output Resistance Gain Bandwidth Gain GATE5 Slew Rate Maximum Load Capacitance +3.3V LINEAR REGULATOR (REG3P3) REG3P3 Output Voltage Load Current Output Short-Circuit Current REG3P3 shorted to AGND 150 3.15 3.45 50 V mA mA Maximum capacitance on DVDDIO when using an external pass transistor At DVDDIO ISOURCE = 0A (no load) ISINK = 500A ISINK = 0A to 50A DVDDIO to GATE5 DVDDIO to GATE5 330 1.58 1700 4.3 1 4.75 VDVDDIO - 0.1 2 5.25 V V V kHz V/V V/ms F _______________________________________________________________________________________ 5 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER REG2P5 Output Voltage Load Current Output Short-Circuit Current POWER REQUIREMENTS DVDD Supply Voltage Range AVDD DVDDIO All analog functions enabled All analog functions disabled LNA Sigma-delta ADC SAR ADC, 250ksps, fADCCLK = 4MHz AVDD Supply Current PLL Incremental AVDD supply current Supply voltage supervisors Internal voltage reference Reference buffer Bias (any AVDD module enabled) DVDD Supply Current DVDDIO Supply Current DIGITAL INPUTS (GPIO, UART, JTAG, SPITM) Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Pullup/Pulldown Resistance Input Capacitance VDVDDIO = 5.0V Digital input voltage = DGND or DVDDIO, pullup disabled Pulled up to DVDDIO internally, pulled down to DGND internally 500 0.01 150 15 1 VDVDDIO -1 0.8 V V mV A k pF 2.25 3.00 4.5 2.5 3.3 5.0 12 3 2.4 12 600 300 3 220 300 1.5 11 2.5 mA mA mA A 2.75 3.6 5.5 18 10 mA A mA V REG2P5 shorted to DGND 100 SYMBOL CONDITIONS MIN 2.38 TYP MAX 2.62 50 UNITS V mA mA +2.5V LINEAR REGULATOR (REG2P5) SPI is a trademark of Motorola, Inc. 6 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS I SINK = 0.5mA, drive strength = low I SINK = 1.0mA, drive strength = high I SOURCE = 0.5mA, drive strength = low Output High Voltage ISOURCE = 1.0mA, drive strength = high Maximum Output Impedance Three-State Leakage Three-State Capacitance BURST OUTPUT Output Low Voltage Output High Voltage Maximum Output Impedance Three-State Leakage Three-State Capacitance Short-Circuit Current RESET Internal Pullup Resistance Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage UART/LIN INTERFACE (UTX, URX) Asynchronous mode (system clock/32) Synchronous mode (system clock/8) LIN 2.0 compatibility (Note 3) 1 500 2000 20 kbps Pulled up to DVDDIO I SINK = 0.5mA No external load When driven by external source When driven by external source VDVDDIO 1 VDVDDIO 0.5 0.8 120 0.4 k V V V V Burst drive set to high I SINK = 8mA I SOURCE = 8mA Drive strength = low Drive strength = high VDVDDIO 0.5 90 45 0.01 15 50 1 A pF mA 0.4 V V Drive strength = low Drive strength = high VDVDDIO 0.5 880 450 0.01 15 1 A pF VDVDDIO 0.5 V MIN TYP MAX 0.4 0.4 UNITS MAXQ7667 DIGITAL OUTPUTS (GPIO, UART, JTAG, SPI) Output Low Voltage V UART Baud Rates _______________________________________________________________________________________ 7 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 ELECTRICAL CHARACTERISTICS (continued) (VDVDDIO = +5V, VAVDD = +3.3V; VDVDD = +2.5V, system clock (fSYSCLK) = 16MHz, burst frequency (fBURST) = bandpass frequency (fBPF) = 50kHz, CREFBG = CREF = 1F in parallel with 0.01F, fADCCLK = 2MHz (SAR data rate = 125ksps), TA = TMIN to TMAX, unless otherwise specified. Typical values are at TA = +25C.) PARAMETER SPI Master Operating Frequency SPI Slave Operating Frequency SCLK Output Pulse-Width High/Low MOSI Output Hold Time After SCLK Sample Edge MOSI Output Valid to Sample Edge MISO Input Valid to SCLK Sample Edge MISO Input Hold Time After SCLK Sample Edge SCLK Inactive to MOSI Inactive SCLK Input Pulse-Width High/Low SS Active to First Shift Edge MOSI Input Setup Time to SCLK Sample Edge MOSI Input Hold Time After SCLK Sample Edge MISO Output Valid After SCLK Shift Edge Transition SS Inactive Duration SCLK Inactive to SS Rising Edge FLASH PROGRAMMING Flash Erase Time Flash Programming Time Write/Erase Cycles Data Retention Average temperature = +85C Mass erase Page erase (512 bytes per page) 20s per word 200 20 657 10,000 15 ms ms Cycles Years SYMBOL CONDITIONS MIN TYP MAX UNITS SPI INTERFACE TIMING (Figures 11 and 12) 1/tMCK 1/tSCK tMCH, tMCL tMOH tMOV tMIS tMIH tMLH tSCH, tSCL tSSE tSIS tSIH tSOV tSSH tSD tSYSCLK + 25 tSYSCLK + 25 4tSYSCLK 25 25 50 0.5 x fSYSCLK 0.25 x fSYSCLK tMCK/2 - 25 tMCK/2 - 25 tMCK/2 - 25 25 0 0 tSCK/2 8 4 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Noise measured at bandpass filter output with ECHO+ and ECHO- shorted divided by the gain with fBPF = 50kHz. Note 2: Gain adjust resolution typically ranges between 6.25% and 12.5%. Note 3: LIN 2.0 specifies a maximim data rate of 20kbps. Higher data rates could be possible with compatible devices and suitable line conditions. 8 _______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Typical Operating Characteristics (VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25C, unless otherwise noted.) BURST OUTPUT FREQUENCY vs. TEMPERATURE 50.04 BURST OUTPUT FREQUENCY (kHz) 50.03 50.02 50.01 50.00 49.99 49.98 49.97 49.96 49.95 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) USING PLL MAXQ7667 toc01 MAXQ7667 LOWPASS FILTER OUTPUT vs. ECHO INPUT AMPLITUDE MAXQ7667 toc02 LOWPASS FILTER OUTPUT vs. ECHO INPUT FREQUENCY PROGRAMMABLE ECHO GAIN = MINIMUM ECHO INPUT AMPLITUDE = 20mVP-P 10,000 LPF OUTPUT (LSB) MAXQ7667 toc03 50.05 65,536 PROGRAMMABLE ECHO GAIN = MINIMUM 57,344 49,152 LPF OUTPUT (LSB) 40,960 32,768 24,576 16,384 8192 0 0 0.02 0.04 0.06 0.08 100,000 1000 100 10 0.10 25 40 55 70 85 100 ECHO INPUT AMPLITUDE (VP-P) ECHO INPUT FREQUENCY (kHz) BANDPASS FILTER OUTPUT NOISE FLOOR vs. BANDPASS FILTER CENTER FREQUENCY MAXQ7667 toc04 RECEIVE PATH RESPONSE TIME (ECHO INPUT TO LOWPASS FILTER OUTPUT) 14,000 12,000 ADC COUNT (LSB) 10,000 8000 6000 4000 INPUT ON 2000 INPUT OFF MINIMUM ECHO GAIN 20mVP-P ECHO AMPLITUDE 50kHz ECHO FREQUENCY 250ksps MAXQ7667 toc05 MAXQ7667 toc07 15 RECEIVE PATH GAIN AT MAXIMUM BANDPASS FILTER OUTPUT (LSBRMS) 12 TA = +105C 16,000 TA = +25C 9 6 TA = -40C 3 0 20 40 60 FREQUENCY (kHz) 80 100 0 0 200 400 600 800 1000 TIME (s) LOWPASS FILTER OUTPUT RIPPLE vs. TIME 14,500 14,000 LPF OUTPUT (LSB) 13,500 13,000 12,500 12,000 11,500 11,000 10,500 10,000 0 2 4 6 TIME (ms) 8 10 12 MINIMUM ECHO GAIN 20mVP-P ECHO AMPLITUDE 50kHz ECHO FREQUENCY 250ksps MAXQ7667 toc06 SAR ADC OFFSET ERROR vs. TEMPERATURE 2.0 1.5 OFFSET ERROR (mV) 1.0 0.5 VAVDD = 3.3V 0 -0.5 -1.0 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) VAVDD = 3V 15,000 VAVDD = 3.6V _______________________________________________________________________________________ 9 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Typical Operating Characteristics (continued) (VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25C, unless otherwise noted.) SAR ADC GAIN ERROR vs. TEMPERATURE MAXQ7667 toc08 SAR ADC INL vs. CODE MAXQ7667 toc09 SAR ADC DNL vs. CODE 1.5 1.0 DNL (LSB) 0.5 0 -0.5 -1.0 -1.5 -2.0 MAXQ7667 toc10 3.0 2.0 1.5 1.0 INL (LSB) 0.5 0 -0.5 -1.0 -1.5 2.0 2.5 GAIN ERROR (mV) VAVDD = 3.3V VAVDD = 3V 2.0 1.5 VAVDD = 3.6V 1.0 0.5 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) -2.0 0 512 1024 1536 2048 2560 3072 3584 4096 CODE 0 512 1024 1536 2048 2560 3072 3584 4096 CODE REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 2.519 REF OUTPUT VOLTAGE (V) 2.518 2.517 2.516 2.515 2.514 2.513 2.512 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD SUPPLY VOLTAGE (V) 2.45 -50 MAXQ7667 toc11 REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7667 toc12 2.520 2.55 REF OUTPUT VOLTAGE (V) 2.53 2.51 2.49 2.47 -25 0 25 50 75 100 125 TEMPERATURE (C) SUPPLY BROWNOUT THRESHOLDS vs. TEMPERATURE MAXQ7667 toc13 REGULATOR OUTPUT VOLTAGE vs. TEMPERATURE MAXQ7667 toc14 5.0 4.5 SUPPLY THRESHOLD (V) DVDDIO INTERRUPT 4.0 3.5 3.0 DVDD INTERRUPT 2.5 2.0 -50 -25 0 25 50 75 100 DVDD RESET AVDD INTERRUPT 5.0 REGULATOR OUTPUT VOLTAGE (V) 4.5 4.0 AVDD 3.5 3.0 2.5 2.0 DVDD DVDDIO 125 -50 -25 0 25 50 75 100 125 TEMPERATURE (C) TEMPERATURE (C) 10 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Typical Operating Characteristics (continued) (VDVDDIO = +5V, VAVDD = +3.3V, VDVDD = +2.5V, fSYSCLK = 16MHz, burst frequency = bandpass frequency = 50kHz, TA = +25C, unless otherwise noted.) DVDDIO REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT DVDDIO REGULATOR OUTPUT VOLTAGE (V) MAXQ7667 toc15 MAXQ7667 REG3P3 REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT REG3P3 REGULATOR OUTPUT VOLTAGE (V) MAXQ7667 toc16 5.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5.0 DRAIN = 14V 4.5 DRAIN = 8V 4.0 3.5 3.0 0 EXTERNAL VOLTAGE SOURCE CONNECTED TO THE DRAIN OF EXTERNAL PASS TRANSISTOR BSP129 50 100 150 200 0 20 40 60 80 100 120 DVDDIO LOAD CURRENT (mA) REG3P3 LOAD CURRENT (mA) REG2P5 REGULATOR OUTPUT VOLTAGE vs. LOAD CURRENT REG2P5 REGULATOR OUTPUT VOLTAGE (V) MAXQ7667 toc17 RC OSCILLATOR FREQUENCY vs. TEMPERATURE MAXQ7667 toc18 3.0 2.5 2.0 1.5 1.0 0.5 0 0 20 40 60 80 100 15.0 RC OSCILLATOR FREQUENCY (MHz) 14.5 14.0 13.5 13.0 12.5 12.0 VDVDD = 2.50V VDVDD = 2.75V VDVDD = 2.25V 120 -50 -25 0 25 50 75 100 125 REG2P5 LOAD CURRENT (mA) TEMPERATURE (C) ______________________________________________________________________________________ 11 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Pin Description PIN 1 2 3 NAME P1.3/TCK P1.4/MOSI P1.5/MISO FUNCTION Port 1 Data 3/JTAG Serial Clock Input. P1.3 is a general-purpose digital I/O. TCK is the JTAG serial test clock input. Refer to the MAXQ7667 User's Guide Sections 5 and 11. Port 1 Data 4/SPI Serial Data Output. P1.4 is a general-purpose digital I/O. MOSI is the master output, slave input for the SPI interface. Refer to the MAXQ7667 User's Guide Sections 5 and 9. Port 1 Data 5/SPI Serial Data Input. P1.5 is a general-purpose digital I/O. MISO is the master input, slave output for the SPI interface. Refer to the MAXQ7667 User's Guide Sections 5 and 9. Port 1 Data 6/SPI Serial Clock Output. P1.6 is a general-purpose digital I/O. SCLK is the serial clock for the SPI interface. SCLK is an input when operating as a slave and an output when operating as a master. Refer to the MAXQ7667 User's Guide Sections 5 and 9. Port 1 Data 7/Schedule Timer Sync Input/SPI Slave Select. P1.7 is a general-purpose digital I/O. A rising edge on the SYNC input resets the schedule timer. In SPI slave mode, SS is the SPI slave-select input. In SPI master mode, use SS or a GPIO to manually select an external slave. Refer to the MAXQ7667 User's Guide Sections 5, 7, and 9. Digital Supply Voltage. Connect DVDD directly to a +2.5V external source or to REG2P5 output for single supply operation. Bypass DVDD to DGND with a 0.1F capacitor as close as possible to the device. Connect all DVDD nodes together. Digital Ground. Connect all DGND nodes together. Connect to AGND at a single point. Digital I/O Supply Voltage. DVDDIO powers all digital I/Os except for XIN and XOUT. Bypass DVDDIO to DGND with a 0.1F capacitor as close as possible to the device. Connect all DVDDIO nodes together. Port 0 Data 0/UART Receive Data Input. P0.0 is a general-purpose digital I/O. URX is a UART or LIN data receive input. Refer to the MAXQ7667 User's Guide Sections 5 and 8. Port 0 Data 1/UART Transmit Data Output. P0.1 is a general-purpose digital I/O. UTX is a UART or LIN data transmit output. Refer to the MAXQ7667 User's Guide Sections 5 and 8. Port 0 Data 2/UART Transmit Output. P0.2 is a general-purpose digital I/O. TXEN asserts low when the UART is transmitting. Use TXEN to enable an external LIN/UART transceiver. Refer to the MAXQ7667 User's Guide Sections 5 and 8. Port 0 Data 3/Timer 0 I/O/ADC Control Input. P0.3 is a general-purpose digital I/O. T0 is the primary Type 2 timer/counter 0 output or input. ADCCTL is a sampling/conversion trigger input for the SAR ADC. Refer to the MAXQ7667 User's Guide Sections 5, 6, and 14. Port 0 Data 4/Timer 0B I/O/Comparator Output. P0.4 is a general-purpose digital I/O. T0B is the secondary Type 2 timer/counter 0 output or input. Refer to the MAXQ7667 User's Guide Sections 5 and 6. Port 0 Data 5/Timer 1 I/O. P0.5 is a general-purpose digital I/O. T1 is the primary Type 2 timer/counter 1 output or input. Refer to the MAXQ7667 User's Guide Sections 5 and 6. Port 0 Data 6/Timer 2 I/O. P0.6 is a general-purpose digital I/O. T2 is the primary Type 2 timer/counter 2 output or input. Refer to the MAXQ7667 User's Guide Sections 5 and 6. Port 0 Data 7/Timer 2B I/O. P0.7 is a general-purpose digital I/O. T2B is the secondary Type 2 timer/counter 2 output or input. Refer to the MAXQ7667 User's Guide Sections 5 and 6. Crystal Oscillator Input. Connect an external crystal or resonator between XIN and XOUT. When using an external clock source drive XIN with 2.5V level clock while leaving XOUT unconnected. Connect XIN to DGND when an external clock source is not used. 4 P1.6/SCLK 5 P1.7/SYNC/SS 6, 19, 42 7, 18, 43 8, 17, 44 DVDD DGND DVDDIO 9 10 P0.0/URX P0.1/UTX 11 P0.2/TXEN 12 P0.3/T0/ ADCCTL 13 P0.4/T0B 14 15 16 P0.5/T1 P0.6/T2 P0.7/T2B 20 XIN 12 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Pin Description (continued) PIN 21 22 23 24 NAME XOUT REG2P5 REG3P3 GATE5 RESET FUNCTION Crystal Oscillator Output. Connect an external crystal or resonator between XIN and XOUT. Leave XOUT unconnected when driving XIN with a 2.5V level clock or when an external clock source is not used. +2.5V Voltage Regulator Output +3.3V Voltage Regulator Output +5V DVDDIO Voltage Regulator Control Output. GATE5 controls an external npn or nMOS transistor that passes power to DVDDIO. Reset Input/Output. RESET is open drain with an internal pullup resistor to DVDDIO. Internal circuitry pulls RESET low when VDVDDIO falls below its brownout reset value or watchdog reset is enabled and the watchdog timeout period expires. Force RESET low externally for manual reset. PLL VCO Control Input. Connect external filter components on FILT for the internal PLL circuit. See the Typical Application Circuit/Functional Diagram. Analog Supply Voltage. Connect all AVDD inputs directly to a +3.3V source or to REG3P3 for selfpowered operation. Bypass each AVDD to AGND with a 0.1F capacitor as close as possible to the device. Analog Ground. Connect all AGND nodes together. Connect to DGND at a single point. Negative Echo Input. AC-couple ECHON to an ultrasonic transducer. Positive Echo Input. AC-couple ECHOP to an ultrasonic transducer. ADC Reference Input/Reference Buffer Output. When using the internal reference, the buffered bandgap reference voltage (VREF) is provided for both SAR and sigma-delta ADCs. When using an external reference, apply an external voltage source ranging between 1V and VAVDD at REF. Disable the reference buffer when applying an external reference at REF. Bypass REF to AGND with a 0.47F capacitor. +2.5V Reference Output/Reference Buffer Input. Bypass to AGND with a 0.47F capacitor. SAR ADC Input 0. AIN0 pairs with AIN1 in differential mode. SAR ADC Input 1. AIN1 pairs with AIN0 in differential mode. SAR ADC Input 2. AIN2 pairs with AIN3 in differential mode. SAR ADC Input 3. AIN3 pairs with AIN2 in differential mode. SAR ADC Input 4 No Connection. Internally connected. Leave unconnected. Burst Output. Burst is the ultrasonic transducer excitation pulse output. BURST remains in threestate mode on power-up. Port 1 Data 0/JTAG Output. P1.0 is a general-purpose digital I/O. TDO is the JTAG serial data output. Refer to the MAXQ7667 User's Guide Sections 5 and 11. Port 1 Data 1/JTAG Test Mode-Select Input. P1.1 is a general-purpose digital I/O. TMS is the JTAG mode-select input. Refer to the MAXQ7667 User's Guide Sections 5 and 11. Port 1 Data 2/JTAG Input. P1.2 is a general-purpose digital I/O. TDI is the JTAG serial data input. Refer to the MAXQ7667 User's Guide Sections 5 and 11. MAXQ7667 25 26 FILT 27, 32 28, 31, 33 29 30 AVDD AGND ECHON ECHOP 34 REF 35 36 37 38 49 40 41 45 46 47 48 REFBG AIN0 AIN1 AIN2 AIN3 AIN4 N.C. BURST P1.0/TDO P1.1/TMS P1.2/TDI ______________________________________________________________________________________ 13 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Typical Application Circuit/Functional Diagram 0.47F TRANSDUCER 0.47F REFBG REF AIN0 AIN1 12-BIT SAR ADC AIN2 AIN3 AIN4 THERMISTOR AVDD BURST BURST ENABLE BURST OUTPUT DUTY CYCLE AND PULSE COUNTER VOLTAGE REFERENCE 0.01F BATTERY+ 470pF 0.01F ECHON 470pF ECHOP LNA SIGMADELTA ADC DIGITAL BANDPASS FILTER FULLWAVE RECTIFIER DIGITAL LOWPASS FILTER INTERRUPT MAXQ20 RISC C FIFO THRESHOLD ADJUST 0V 2mVP-P BSP129 DVDDIO 0.1F GATE5 PROGRAMMABLE PLL REG3P3 0.1F AVDD 16 x 16 HW MULT PLUS ACCUM FLASH RAM ROM FILT 330pF 24k 33nF MAXQ7667 CLOCK PRESCALER DIVIDE BY 1 TO 128 V+ GND CONNECTOR +8V TO +20V 0.1F REG2P5 DVDD DGND GPIO/JTAG LIN LIN Rx P0.0/URX P0.1/UTX GPIO/SPI INTERFACE MODULE POR/ BROWNOUT AGND WATCHDOG LIN Tx TRANSCEIVER 13.5MHz RC OSCILLATOR CRYSTAL OSCILLATOR XIN XOUT 16MHz SCHEDULE TIMER TIMER 2 TIMER 1 TIMER 0 PO.6/T2 PO.7/T2B PO.5/T1 PO.3/T0/ADCCTL PO.4/T0B RESET 20pF 20pF 14 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Detailed Features o Smart Analog Peripherals Dedicated Ultrasonic Burst Generator Echo Receiving Path Low-Noise Amplifier Time Variable Gain Amplifier 16-Bit Sigma-Delta ADC Digital Bandpass Filter Full-Wave Rectifier and Digital Lowpass Filter 8-Deep, 16-Bit Wide FIFO Simplifies Real-Time Processing Magnitude Comparator 5-Channel, 12-Bit SAR ADC with 250ksps Sampling Rate Internal Bandgap Voltage Reference for the ADCs (Also Accepts External Voltage Reference) o Timer/Digital I/O Peripherals SPI Interface Three 16-Bit (or Six 8-Bit) Programmable Type 2 Timers/Counters 16-Bit Schedule Timer Programmable Watchdog Timer 16 General-Purpose Digital I/Os with Multipurpose Capability o High-Performance, Low-Power, 16-Bit RISC Core 1MHz-16MHz Operation, Approaching 1MIPS per 1MHz Low Power (< 2.5mA/MIPS, DVDD = +2.5V) 16-Bit Instruction Word, 16-Bit Data Bus 33 Instructions (Most Require Only One Clock Cycle) 16-Level Hardware Stack Three Independent Data Pointers with Automatic Increment/Decrement o Program and Data Memory Internal 32KB Program Flash Internal 4KB Data RAM Internal 8KB Utility ROM o Crystal/Clock Module 1MHz-16MHz External Crystal Oscillator 13.5MHz Internal RC Oscillator External Clock Source Operation o 16 x 16 Hardware Multiplier with 48-Bit Accumulator, Single Clock Cycle Operation o Power-Management Module Power-On Reset (POR) Power-Supply Supervisor/Brownout Detection for All Supplies On-Chip +5V, +3.3V, and +2.5V Regulators for Single Supply Operation o JTAG Interface Extensive Debug and Emulation Support In-System Test Capability Flash-Memory-Program Download o UART Synchronous and Asynchronous Transfers Independent Baud-Rate Generator 2-Wire Interface Transmit and Receive FIFOs o LIN Supports LIN 1.3, LIN 2.0, and SAE J2602 Automatic Baud-Rate Detection and LIN Frame Synchronization Up to 64 Bytes Frame Length Automatic Calculation of Standard (LIN 1.3) and Enhanced (LIN 2.0) Checksums o 7mm x 7mm, 48-Pin LQFP Package o -40C to +125C Operating Temperature Range MAXQ7667 ______________________________________________________________________________________ 15 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Detailed Description The ultrasonic distance-measurement peripherals in the MAXQ7667 include a burst signal generator for acoustic transmission and mixed signal circuits for amplifying and digitizing echo signals ranging between 25kHz and 100kHz. The burst signal is a square wave with adjustable duty cycle and pulse count. The burst is derived either directly from the system clock or from a programmable PLL locked to the system clock. The MAXQ7667 effectively digitizes the echo signals received at the ECHOP and ECHON inputs using an LNA, sigma-delta ADC with variable analog gain amplifier, noise-limiting digital bandpass filter, digital fullwave rectifier, and a digital lowpass filter (see the Typical Application Circuit/Functional Diagram). The device detects echo signals at the burst frequency with amplitudes ranging from 10VP-P to 100mVP-P. Echoes greater than 100mVP-P and less than 2VP-P are internally clipped but do not saturate the receiver. To optimize echo reception, the clock used for processing the echo locks to the burst frequency. The MAXQ7667's burst generator can generate higher frequencies, but the maximum usable frequency for the echo receive path is 100kHz . For applications requiring transducer frequencies above 100kHz, implement an external echo receive path. The SAR ADC can then digitize the filtered echo envelope. An integrated 16-bit RISC C (MAXQ20) provides timing control, signal processing, and data I/O. The 16-bit Harvard architecture RISC core executes most instructions in a single clock cycle from instruction fetch to cycle completion. The MAXQ20 provides optimal performance for noise-sensitive analog applications. The MAXQ7667 includes a 13.5MHz RC oscillator, external crystal oscillator, watchdog timer, schedule timer, three general-purpose Type 2 timers/counters, two 8-bit GPIO ports, SPI interface, JTAG interface, LIN capable UART interface, 12-bit SAR ADC with five multiplexed input channels, supply-voltage monitors, and a voltage reference for communication, diagnostics, and miscellaneous support. Burst Controller The MAXQ7667 provides a square-wave burst signal at the BURST output. Use the burst control to transmit an ultrasonic signal. Typical applications use the burst signal to switch an external transistor that drives a highvoltage transformer, which excites the transducer (see the Typical Application Circuit/Functional Diagram). Use software to configure the duty cycle, frequency, number of pulses, and drive current of the burst. See Section 17 of the MAXQ7667 User's Guide. Derive the burst signal either directly from the system clock or from a programmable oscillator phase locked to the system clock (Figure 1). Using the system clock limits the burst frequency to one of 16 choices. Integer division of the system clock generates these 16 frequencies. The PLL allows a fractional division of the system clock. Any frequency within the PLL range is selectable to a resolution of 0.13% or better. When using the internal PLL, connect external filter components (C1, R1, and C2) to FILT as shown in Figure 1. These components filter the analog voltage that controls the VCO in the PLL. The filter component values shown in the figure are suitable for the entire PLL frequency range. SYSTEM CLOCK (fSYSCLK) BTRN[15:12]:BDIV[3:0] RECEIVE CLOCK PRESCALE ECHO RECEIVE CLOCK 2mVP-P DIAGNOSTIC BURST BTRN.8:BGT BTRN.9:BTRI 1 0 FILT R1 24k C1 33nF C2 330pF PLL BTRN.10:BCKS PLLF[8:0] PLLF[10:9]:PLLC[1:0] BURST CLOCK GENERATOR BURST BPH[9:0] BTRN[7:0]:BCNT[7:0] BPH.15:BSTT PWM BTRN.11:BPOL BPH.14:BDS MAXQ7667 Figure 1. Burst Transmission Stage 16 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Echo Receive Path Low-Noise Amplifier (LNA) The LNA provides a 40V/V fixed gain to the input signal. The differential inputs of the LNA are ECHOP and ECHON. For proper biasing of the LNA, AC-couple the transducer or any external circuitry to ECHOP and ECHON. For a single-ended input signal, AC-couple the signal to ECHOP with a 0.01F capacitor and connect ECHON to AGND through a 0.01F capacitor placed as close as possible to the signal source. The outputs of the LNA connect to the inputs of a 16-bit sigma-delta ADC and can connect internally to the AIN0 and AIN1 inputs of the SAR ADC for external monitoring (Figure 2). Diagnostic Signals An analog multiplexer located at the input of the LNA selects one of three possible signals for processing by the echo receive path; the normal echo signal AC-coupled to the ECHOP and ECHON inputs, 0V signal, or a 2mV P-P internally generated signal (Figure 2). The 2mVP-P square-wave signal, with frequency and duty cycle matching the burst signal, allows the echo receive chain to process a simulated echo. MAXQ7667 TO EXTERNAL VOLTAGE REFERENCE 0.47F AGND REFGB APE.12:BGE 2mVP-P 0V MUX RCVC[7:6]:LNAISEL[1:0] 40R* ECHOP R* BPFI[15:0] AVDD/2 ECHON R* LNA VARIABLE GAIN SIGMADELTA ADC BANDPASS FILTER FULL-WAVE RECTIFIER PLUS LOWPASS FILTER AIE.1:LPFIE 40R* RCVC.8:LNAOSEL ECHO RECEIVE CLOCK CLOCK CONTROL LPFD[15:0] BPFO[15:0] ASR.3:CMPI AIE.3:CMPIE APE.13:RSARE CMPT[15:0] RCVC[4:0]:RCVGN[4:0] CMPC[14:0]:CMPH[14:0] 2.5V BANDGAP REF COMPARATOR CMPC.15:CMPP REF 0.47F AGND ASR.12:CMPLVL DATA READY INTERRUPT ASR.1:LPFRDY LPFC.3:FFLD FIFO 8 x 16 LPFF[15:0] AIN0 AIN1 TO SAR ADC TIMER 0 TIMER 1 TIMER 2 LPFC[2.0]:FFLS[2:0] FIFO CONTROL LPFC[11:8]:FFDP[3:0] LPFC.7:FFOV ASR.2:LPFFL MAXQ7667 LPFC[15:12]:FFIL[3:0] AIE.2:LFLIE *R = ECHO INPUT RESISTANCE. SEE THE ELECTRICAL CHARACTERISTICS SECTION. Figure 2. Echo Receive Path ______________________________________________________________________________________ 17 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Sigma-Delta ADC The MAXQ7667 features a 16-bit sigma-delta ADC with an analog gain adjustable from 38dB to 60dB (including the fixed LNA gain) with a maximum gain step of 12.5% (typical). Gain changes settle within one ADC conversion. Use software to create a virtual time variable gain amplifier. A digital bandpass and lowpass filters remove switching glitches and DC offset at the output of the ADC. In a typical application, the software sets the gain to a low value when the burst is first sent and increases the gain as the time from when the burst was sent increases. As a result, strong echoes from nearby objects are processed without clipping while small signals from distant objects are processed with the maximum gain. The ADC samples the amplified echo signal from the LNA at 80 times the burst output frequency. The ADC provides conversion results at a data rate equal to 10 times the burst output frequency. The ADC conversion results also load to an 8-deep first-in-first-out (FIFO) at the native data rate or a separate time base without loading the CPU. MAXQ7667 Digital Bandpass Filter The digital bandpass filter has a center frequency that tracks the burst output frequency. The bandpass width is 14% of the center frequency. The bandpass filter provides the 16-bit output data at a data rate equal to 10 times the burst output frequency. Full-Wave Rectifier The full-wave rectifier detects the envelope of the digital bandwidth filter output to generate a DC output proportional to the peak-to-peak amplitude of the input signal. Full-wave rectification allows the digital lowpass filter to respond faster without excessive ripple. Digital Lowpass Filter The lowpass filter removes the ripple from the full-wave detector output. The output of the lowpass filter is available at a data rate equal to five times the burst output frequency. The corner frequency is 1/5 the burst frequency with approximately 40dB per decade rolloff. The 16-bit output data of the lowpass filter is stored in a FIFO register with a depth of eight samples. The MAXQ7667 allows data transfer from the lowpass filter REF SARC.7:SARBIP SARC.6:SARDUL SARC.4:SARASD SARC[2:0]:SARS[2:0] SARC.3:SARBY MUX SARC[11:9]:SARMX[2:0] ASR.0:SARRDY ADC DATA READY INTERRUPT AVDD REFERENCE TO SIGMA-DELTA ADC APE.12:BGE BANDGAP REF REFBG VREF APE.14:RBUFE BUF x1.0 AIN0 AIN1 AIN2 AIN3 AIN4 VREF AGND MUX 12-BIT ADC TIMER 0 TIMER 1 TIMER 2 AIE.0:SARIE ADCCTL APE.4:SARE SARC[11:9]:SARMX[2:0] SARC.8:SARDIF SYSCLK ADC CLOCK DIV ADCCLK AVDD AGND OSCC[3:2]:SARCD[1:0] DATA BUS[15:0] Figure 3. SAR ADC Block Diagram 18 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System output to the FIFO automatically each time the lowpass filter output updates, through the control of one of the timer outputs, or through software. The device includes a FIFO depth counter with programmable interrupt levels and generates an interrupt if a FIFO overflow condition occurs. The output of the digital lowpass filter connects to a digital comparator that can generate an interrupt for a specified echo signal level. ture, battery voltage, or other parameters using five single-ended or two fully differential analog inputs (AIN0-AIN4). All of the analog inputs have a range of 0 to VREF in unipolar mode and VREF/2 in bipolar mode. The SAR ADC supports three different conversion start sources: timers, ADC control input (ADCCTL), and software write. The conversion start source triggers the ADC acquisition and conversion. The system clock provides the ADC clock frequency programmable to 1/2, 1/4, 1/8, or 1/16 of the system clock. Use internal bandgap reference, external reference, or AVDD for voltage reference of the SAR ADC. Figure 3 shows a simplified block diagram of the SAR ADC. The output of the SAR ADC is straight binary in unipolar mode and two's complement in bipolar mode. Figures 4 and 5 show the ADC transfer functions in unipolar mode and bipolar mode. MAXQ7667 Digital Comparator and Threshold Adjust The digital comparator output asserts when the echo amplitude at the output of the digital lowpass filter crosses a given threshold. The comparator's threshold level, hysteresis, and interrupt polarity are programmable. SAR ADC The MAXQ7667 incorporates a 12-bit unbuffered SAR ADC with sample-and-hold and conversion rate up to 250ksps. The ADC allows measurements of tempera- FFF FFE FFD FFC OUTPUT CODE (hex) FFB FS = REF ZS = 0 1 LSB = REF/4096 FULL-SCALE TRANSITION 7FF 7FE +FS = REF/2 ZS = 0 -FS = -REF/2 1 LSB = REF/4096 FULL-SCALE TRANSITION 001 OUTPUT CODE (hex) 0 1 2 3 4 FS 000 FFF FFE 004 003 002 001 000 FS - 1.5 LSB 801 800 -FS -FS + 0.5 LSB 0 +FS - 1.5 LSB +FS DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 4. Unipolar Transfer Function Figure 5. Bipolar Transfer Function ______________________________________________________________________________________ 19 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 SAR ADC Analog Input Track-and-Hold (T/H) Figures 6 and 7 show the equivalent input circuit of the MAXQ7667 analog input architecture. During acquisition (track), a sampling capacitor charges to the positive input voltage at AIN0-AIN4 in single-ended mode or AIN0 and AIN2 in differential mode while a second sampling capacitor connects to AGND in single-ended mode or AIN1 and AIN3 in differential mode. The ADC conversion start source and the ADC dual mode selection bits control the T/H timing. vides the reference to the SAR ADC and sigma-delta ADC. Bypass REFBG and REF to AGND with a 0.47F capacitor for optimum performance. See Section 14 of the MAXQ7667 User's Guide. Schedule Timer The MAXQ7667's schedule timer provides general timekeeping and software synchronization to an external I/O. The schedule timer features include the following: * 16-bit autoreload up-counter for the timer * Programmable 16-bit alarm register * Alarm interrupts * Schedule timer incremented by a programmable system clock prescaler (1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128) * Schedule timer up-counter resettable through an external I/O pin, which allows synchronization of a schedule timer to an external event * Wake-up alarm to pull the system clock from stopmode to normal operation Figure 8 shows a simplified block diagram of the schedule timer. Voltage Reference The MAXQ7667 supports three possible voltage reference sources for ADC conversion; 2.5V internal buffered bandgap reference, external source, and AVDD. The internal 2.5V bandgap reference has high initial accuracy and temperature coefficient of typically less than 100ppm/C. When operating in internal reference mode, either the buffered output of the internal reference or AVDD connects to the SAR ADC while the buffered output of the internal reference connects to the sigma-delta ADC. When operating in external reference mode, an external source ranging between 1V and VAVDD applied at either the REF or REFBG inputs pro- AVDD AVDD CIN+ AIN+ CIN+ AIN+ RIN+ RIN+ CINAIN- RINAIN- CIN- RIN- AGND AGND Figure 6. Equivalent Input Circuit (Track/Acquisition Mode) Figure 7. Equivalent Input Circuit (Hold/Conversion Mode) 20 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Type 2 Timers/Counters The MAXQ7667 includes three 16-bit timers/counters with programmable I/O (Figure 9). Each timer is a Type 2 timer implemented in the MAXQ(R) family. The Type 2 timer is an autoreload 16-bit timer/counter offering the following functions: * 8-bit/16-bit timer/counter * Up/down autoreload * Counter function of external pulse * Capture * Compare * Internal, fast-starting, 13.5MHz RC oscillator (default oscillator at startup and in the event the external crystal fails) * External 4MHz-16MHz clock input MAXQ7667 Crystal Selection The MAXQ7667 requires a crystal with the following specifications: Frequency: 1MHz-16MHz CLOAD: 6pF (min) Drive level: 5W Series resonance resistance: 30 (max) Note: Quartz crystal vendors often specify series resonance resistance (R1). Series resonance resistance is the resistance observed when the resonator is in the series resonant condition. When a resonator is used in the parallel resonant mode with an external load capacitance, as is the case with the MAXQ7667 oscillator circuit, the effective resistance at the loaded frequency of oscillation is: R1 x (1 + (CO/CLOAD))2 For typical shunt capacitance (CO) and load capacitance (CLOAD) values, the effective resistance potentially exceeds R1 by a factor of 2. Clock Sources The MAXQ7667 oscillator module supplies the system clock for the C core and all of the peripheral modules. The high-frequency oscillator operates with a 1MHz to 16MHz crystal. Use the internal RC oscillator as the system clock for applications that do not require precise timing. See Section 15 of the MAXQ7667 User's Guide. The MAXQ7667 supports the following master clock sources: * Internal high-frequency oscillator drives an external 1MHz-16MHz crystal or ceramic resonator MAXQ is a registered trademark of Maxim Integrated Products, Inc. ______________________________________________________________________________________ 21 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 SCNT.0:STIME SCNT.11:STDIV2 MAXQ7667 SCHEDULE TIMER SCNT.1:SALME AN INTERRUPT IS GENERATED WHEN SALIE = 1 AND SALMF = 1 SYSTEM CLOCK PROGRAMMABLE DIVIDE BY 1, 2, 4, ..., 128 STIM 16-BIT UPCOUNTER CLR STIM[15:0] COMPARATOR STIM = SALM SCNT.6:SALMF INT SCNT.7:SALIE SALM REGISTER P1.7/SYNC SCNT.8:SSYNC_EN CLR Figure 8. Schedule-Timer Module Block Diagram CAPTURE T2Cx REGISTER 16-BIT CAPTURE/COMPARE SALM[15:0] EQUAL INPUT CONDITIONING SCALING GATING CLOCK T2Vx REGISTER 16-BIT UP-COUNTER OVERFLOW OUTPUT CONDITIONING POLARITY SELECTION RELOAD T2Rx REGISTER 16-BIT RELOAD Figure 9. Type 2 Timer/Counter in 16-Bit Mode 22 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System JTAG Interface The joint test action group (JTAG) IEEE 1149.1 standard defines a unique method for in-circuit testing and programming. The MAXQ7667 conforms to this standard, implementing an external test access port (TAP) and internal TAP controller for communication with a JTAG bus master, such as an automatic test equipment (ATE) system. The MAXQ7667 JTAG interface does not allow boundary scan. For detailed information on the TAP and TAP controller, refer to IEEE Std 1149.1 "IEEE Standard Test Access Port and Boundary-Scan Architecture" on the IEEE website at www.standards.ieee.org. The TAP controller communicates synchronously with the host system (bus master) through four digital I/Os: test mode select (TMS), test clock (TCK), test data input (TDI), and test data output (TDO). The internal TAP module consists of shift registers and a TAP controller (Figure 10). The shift registers serve as transmit and receive data buffers for a debugger. Maintain the maximum TCK clock frequency to below 1/8 the system clock frequency for proper operation. MAXQ7667 READ TO DEBUG ENGINE WRITE SHADOW REGISTER MAXQ7667 7 MUX 6 5 43210 SYSTEM PROGRAMMING REGISTER BYPASS MUX 4 3 2 1 0 S1 S0 DEBUG REGISTER DVDDIO DVDDIO MUX P1.2/TDI DVDDIO 2 INSTRUCTION REGISTER 1 0 MUX P1.0/TDO P1.1/TMS DVDDIO TAP CONTROLLER P1.3/TCK POWER-ON RESET UPDATE-DR UPDATE-DR Figure 10. JTAG Interface Block Diagram ______________________________________________________________________________________ 23 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System The following four digital I/Os form the TAP interface: * TDO--Serial output signal for test instruction and data. Data transitions on the falling edge of TCK. TDO idles high when inactive. TDO serially transfers internal data to the external host. Data transfers lease significant bit first. * TDI--Serial input signal for test instruction and data. Transition data on the rising edge of TCK. TDO pulls high when unconnected. TDI serially transfers data from the external host to the internal TAP module shift registers. Data transfers least significant bit first. * TCK--Serial clock for the test logic. When TCK stops at 0, storage elements in the test logic must retain their data indefinitely. Force TCK high when inactive. * TMS--Test mode selection. The rising edge of TCK samples the test signals at TMS. The TAP controller decodes the test signals at TMS to control the test operation. Force TMS high when inactive. MAXQ7667 * Supports common RS-232 and LIN baud rates: 1000, 1200, 2400, 4800, 9600, 19,200, 20,000, 38,400, 57,600, and 115,200 with system clock = 16MHz. SPI Interface The MAXQ7667 supports 4-wire SPI interface communication with 8-bit or 16-bit data streams operating in either master mode or slave mode. The SPI interface allows synchronous half-duplex or full-duplex serial data transfers to a wide variety of external serial devices using MISO, MOSI, SS, and SCLK signals. Collision detection is provided when two or more masters attempt a data transfer at the same time. See Section 9 of the MAXQ7667 User's Guide. General-Purpose Digital I/O Ports Two 8-bit digital I/O ports (P0._ and P1._), with dedicated one or more alternative functions, are available as general-purpose I/Os (GPIOs) under the control of the integrated MAXQ20. Set each I/O within each port individually as an input or output. The GPIOs incorporate a Schmitt trigger receiver and a full CMOS output driver (Figure 13). Each GPIO configures as an input with pullup to DVDDIO at power-up. When programmed as an input, each I/O is configurable for high-impedance, weak pullup to DVDDIO or pulldown to DGND. When programmed as an output, writing to the port output register (PO) controls the output logic state. The outputs source or sink at least 1.6mA. Configure the drive strength for each I/O within each port to high or low using the pad drive strength register for optimum EMI performance. All the I/O ports have interrupt capability that wake up the device while in stop mode and have protection circuitry to DVDDIO and DGND. UART/LIN Interface The MAXQ7667 includes a UART/LIN transceiver combination that supports communication speeds up 2MBd. The LIN standard for example limits communication speed to 20kBd or less. Connect a LIN transceiver or other UART connections such as RS-232 and RS-485 directly to the MAXQ7667's 2-wire interface: URX and UTX. The MAXQ7667 operates as a LIN slave or LIN master device. The UART provides the programmable baud-rate generators to communicate effectively to or from the LIN transceiver. The device holds up to 8 bytes of data in each of the transmit and receive FIFOs. The following characteristics apply to the MAXQ7667 UART/LIN interface: * Full-duplex operation for asynchronous data transfers up to 500kBd (system clock/32) * Half-duplex operation for synchronous data transfers up to 2MBd (system clock/8) * 8-deep receive and transmit FIFO with programmable interrupt for receive and transmit * Independent baud-rate generator * Programmable 9th data bit (commonly used for parity or address/data selection)--UART mode only * Hardware support for LIN including break detection, autobaud, address identity filtering, checksum calculation, and block length checking Supply-Voltage Regulators The MAXQ7667 requires three different power-supply voltages. DVDDIO, nominally +5V, allows interfacing to standard 5V logic on all the digital I/Os including the LIN/UART, JTAG, and SPI ports. DVDD, nominally +2.5V, powers all the high-speed digital circuits. AVDD, nominally 3.3V, powers the analog circuits. External power supplies or internal voltage regulators provide each of the supply voltages. The internal voltage regulators provide 3.3V and 2.5V supplies from the 5V DVDDIO input. Obtain the 5V supply from a higher external voltage supply by using a few external components. The MAXQ7667 includes an internal error amplifier used to regulate the voltage on DVDDIO by driving the gate or base of an external pass transistor. Refer to the MAXQ7667 User's Guide for more details on the external components needed for 5V regulation. 24 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 SHIFT SS tMCK SCLK CKPOL/CKPHA 0/1 OR 1/0 SCLK CKPOL/CKPHA 0/0 OR 1/1 SAMPLE SHIFT SAMPLE tMCH tMCL tMOH tMLH MSB - 1 tMOV LSB MOSI MSB tMIS MISO MSB MSB - 1 tMIH LSB Figure 11. SPI Timing Diagram in Master Mode SHIFT SS tSSE SAMPLE SHIFT SAMPLE tSSH tSCK SCLK CKPOL/CKPHA 0/1 OR 1/0 SCLK CKPOL/CKPHA 0/0 OR 1/1 tSIS MOSI MSB tSOV MISO MSB MSB - 1 MSB - 1 tSD tSCH tSCL tSIH LSB Figure 12. SPI Timing Diagram in Slave Mode ______________________________________________________________________________________ 25 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 I/O PAD MAXQ7667 PD0._ MUX SF DIRECTION DVDDIO 100K SF ENABLE PO0._ MUX SF OUTPUT PS0._ DGND 100K PR0._ P0._ DGND PI0._ OR SF INPUT FLAG INTERRUPT FLAG DETECT CIRCUIT EIE0._ EIES0._ Figure 13. Port 0 Digital I/O Basic Circuitry. Port 1 Circuitry is the Same as Port 2. Connect bypass capacitors at each power-supply input as close as possible to the device. Use a bypass capacitor less than 0.47F on DVDDIO. For most applications, 0.1F bypass capacitors are adequate. Supply Brownout Monitor Power supplies DVDD, AVDD, and DVDDIO each include a brownout monitor/supervisor that alerts the C when their corresponding supply voltages drop below the interrupt threshold. Activate each brownout monitor independently using the corresponding brownout enable bits: VDBE, VIBE, and VABE. Four different sources reset the MAXQ7667: POR, watchdog timer reset, external reset, and internal system reset. During normal operation, force RESET low for at least four system clock cycles for an external reset. Set the ROD bit in the SC register, while the SPE bit in the ICDF register is set, for an internal system reset. See Section 16 of the MAXQ7667 User's Guide. Reset In reset mode, no instruction execution occurs and all inputs/outputs return to their default states. Code execution resumes at address 8000h (in the utility ROM) once the reset condition is removed. Power-On Reset (POR) The MAXQ7667 includes a DVDD voltage supervisor to control the C POR. On power-up, internal circuitry pulls RESET low and resets all the internal registers. RESET is held low for the duration of the power-on delay after VDVDD rises above the DVDD reset threshold. The internal RC oscillator starts up and software execution begins at the reset vector location 8000h immediately after the device exits POR while RESET is 26 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System not externally forced low. An internal POR flag indicates the source of a reset. Ramp up the DVDD supply at a minimum rate of 60mV/ms to keep the device in POR until DVDD fully settles. * Signed 16-bit multiplication * Signed 16-bit multiplication and negation * Signed 16-bit multiplication and accumulation * Signed 16-bit multiplication and subtraction MAXQ7667 Watchdog Timer The primary function of the watchdog timer is to watch for stalled or stuck software. The watchdog timer performs a controlled system restart when the P fails to write to the watchdog timer register before a selectable timeout interval expires. The internal 13.5MHz RC oscillator drives the MAXQ7667's watchdog timer. Figure 14 shows the watchdog timer functions as the source of both the watchdog interrupt and watchdog reset. The watchdog interrupt timeout period is programmable to 212, 215, 218, or 221 cycles of the RC oscillator resulting in a nominal range of 273s to 139.8ms. The watchdog reset timeout period is a fixed 512 RC clock cycles (34s). When enabled, the watchdog generates an interrupt upon expiration; then, if not reset within 512 RC clock cycles, the watchdog asserts RESET low for eight RC clock cycles. MAXQ Core Architecture The MAXQ20 C is an accumulator-based Harvard memory architecture. Fetch and execution operations complete in one clock cycle without pipelining because the instruction contains both the op code and data. The C streamlines 16 million instructions per second (MIPS). Integrated 16-level hardware stack enables fast subroutine calling and task switching. Manipulate data quickly and efficiently with three internal data pointers. Multiple data pointers allow more than one function to access data memory without having to save and restore data pointers each time. The data pointers automatically increment or decrement following an operation, eliminating the need for software intervention. Instruction Set The instruction set consists of a total of 33 fixed-length 16-bit instructions that operate on registers and memory locations. The highly orthogonal instruction set allows arithmetic and logical operations to use any register along with the accumulator. System registers control functionality common to all MAXQ Cs, while peripheral registers control peripherals and functions specific to the MAXQ7667. All registers are subdivided into register modules. The architecture is transport-triggered. Writes or reads from certain register locations potentially have side effects. These side effects form the basis for the higher level op codes defined by the assembler, such as ADDC, OR, JUMP, etc. The op codes are implemented as MOVE instructions between system registers. The assembler handles all the instruction encoding. Hardware Multiplier/Accumulator A hardware multiplier supports high-speed multiplications. The multiplier completes a 16-bit x 16-bit multiplication in a single clock cycle and contains a 48-bit accumulator. The multiplier is a peripheral that performs seven different multiplication operations: * Unsigned 16-bit multiplication * Unsigned 16-bit multiplication and accumulation * Unsigned 16-bit multiplication and subtraction RC CLOCK (13.5MHz) DIV 212 DIV 23 DIV 23 DIV 23 Memory Organization WD1 WD0 RWT 212 215 218 221 TIME TIMEOUT WDIF EWDI WTRF RESET EWT RESET INTERRUPT In addition to the internal register space, the device incorporates several memory areas: * 16Kwords of flash memory for program storage * 2Kword of SRAM for storage of temporary variables * 4Kwords utility ROM * 16-level, 16-bit-wide hardware stack for storage of program return addresses and general-purpose use Use the internal memory-management unit (MMU) to map data memory space into a predefined program memory segment for code execution from data memory. Use the MMU to map program memory space as data space for access to constant data stored in program 27 Figure 14. Watchdog Functional Diagram ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System memory. Access physical memory segments (other than the stack and register memories) as either program memory or data memory, but not both at once. By default, the memory is arranged in a Harvard architecture, with separate address spaces for program and data memory. The configuration of program and data space depends on the current execution location. * When executing code from flash memory, access the SRAM and utility ROM in data space. * When executing code from SRAM, access the flash memory and utility ROM in data space. * When executing code from the utility ROM, access the flash memory and SRAM in data space. Data Memory The 2K x 16 internal data SRAM maps into either program or data space. The contents of the SRAM are maintained during stop mode and across non-POR resets, as long as DVDD remains within the operating voltage range. A data memory cycle requires only one system clock period to support fast internal execution. This allows a complete read or write operation on SRAM in one clock cycle. The MMU handles data memory mapping and access control. Read or write to the data memory with word or byte-wide commands. Stack Memory The MAXQ7667 provides a 16 x 16 hardware stack to support subroutine calls and system interrupts. A 16-bit wide internal hardware stack provides storage for program return addresses and general-purpose use. The stack is used automatically by the processor when the CALL, RET, and RETI instructions are executed and interrupts serviced. MAXQ7667 Utility ROM (see Section 18 of the MAXQ7667 User's Guide) The utility ROM is a 4K x 16 block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines called from application software. The subroutines include: * In-system programming (bootloader) over the JTAG or UART interface * In-circuit debug routines * Test routines (internal memory tests, memory loader, etc.) * User-callable routines for in-application flash programming and code space table lookup Following any reset, execution begins in the utility ROM. The ROM software determines whether the program execution immediately jumps to the start of the userapplication code (located at address 0000h) or to one of the special routines mentioned above. Call the routines within the utility ROM using the application software. Refer to the MAXQ7667 User's Guide for more information on the utility ROM contents. Password protect in-system programming, in-application programming, and in-circuit debugging functions using a password-lock (PWL) bit. The PWL bit is implemented in the SC register. When the PWL bit is set to one (POR default), the password is required to access the utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal memory. When the PWL bit is cleared to zero, these utilities are fully accessible without the password. The password is automatically set to all ones following a mass erase. Register Set Sets of registers control most functions. These registers provide a working space for memory operations as well as configuring and addressing peripheral registers on the device. Registers are divided into two major types; system registers and peripheral registers. The register set common to most MAXQ-based devices, also known as the system registers, includes the ALU, accumulator registers, data pointers, interrupt vectors and control, and stack pointer. The peripheral registers define additional functionality. Tables 1 and 3 show the MAXQ7667 register set. Programming Two different methods program the flash memory: insystem programming and in-application programming. Both methods afford great flexibility in system design as well as reduce the life-cycle cost of the embedded system. The MAXQ7667 password protects these features to prevent unauthorized access to code memory. In-System Programming An internal bootstrap loader reloads the device over a simple JTAG or UART interface allowing cost savings in system software upgrade. During power-up, the MAXQ7667 first checks for activity on the JTAG port. If no activity is present, the device checks if a passwordprotected program is present. If the password is set, 28 ______________________________________________________________________________________ 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System the application code executes. The application codes initiate reprogramming. If the password is not set, the MAXQ7667 monitors the UART for an autobaud character (0x0D). If this character is received, the device sets its serial baud rate and initiates a boot loader procedure. If 0x0D is not received after five seconds, the device begins execution of the application code. The following bootloader functions are supported: * Load * Dump * CRC * Verify * Erase individually, or by module. When an interrupt condition occurs, its individual flag is set even if the interrupt source is disabled at the local, module, or global level. Clear interrupt flags within the interrupt routine to avoid repeated false interrupts from the same source. Provide an adequate delay between the write to the flag and the RETI instruction using application software to allow time for the interrupt hardware to remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and synchronous interrupt flags require a two-instruction delay. When an enabled interrupt is detected, software jumps to a user-programmable interrupt vector location. The IV register defaults to 0000h on reset or power-up. Once software control transfers to the ISR, use the interrupt identification register (IIR) to determine if the source of the interrupt is a system register or peripheral register. The specified module identifies the specific interrupt source. The following interrupt sources are available: * Watchdog interrupt * External interrupts 0-7 on port 0 and port 1 * Timer 0 low compare, low overflow, capture/compare, and overflow interrupts * Timer 1 low compare, low overflow, capture/compare, and overflow interrupts * Timer 2 low compare, low overflow, and overflow interrupts * Schedule timer alarm interrupt * SPI data transfer complete, mode fault, write collision and receive overrun interrupts * UART transmit, receive interrupts * LIN mode master or slave interrupt * SAR ADC data ready interrupt * Echo envelope LPF output, FIFO full, and comparator interrupts * Digital and I/O voltage brownout interrupts * High-frequency oscillator failure interrupt MAXQ7667 In-Application Programming The in-application programming feature allows the C to modify its own flash program memory while simultaneously executing its application software. This allows on the fly software updates in mission-critical applications that cannot afford downtime. Erase and program the flash memory using the flash programming functions in the utility ROM. Refer to Section 18 of the MAXQ7667 User's Guide for a detailed description of the utility ROM functions. Stop Mode Power consumption reaches its minimum in stop mode (STOP = 1). In this mode, the external oscillator, internal RC oscillator, system clock, and all processing halts. Trigger an enabled external interrupt input or directly apply an external reset on RESET to exit stop mode. Upon exiting stop mode, the C either waits for the external high-frequency crystal to complete its warmup period or starts execution immediately from its internal RC oscillator while the crystal warms up. Interrupts Multiple interrupt sources quickly respond to internal and external events. The MAXQ architecture uses a single interrupt vector (IV) and single interrupt-service routine (ISR) design. Enable interrupts globally, ______________________________________________________________________________________ 29 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Table 1. System Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh MODULE NAME (BASE SPECIFIER) AP (8h) AP APC -- -- PSF IC IMR -- SC -- -- IIR -- -- CKCN WDCN A (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] -- -- -- -- -- -- -- PFX (Bh) PFX[0] PFX[1] PFX[2] PFX[3] PFX[4] PFX[5] PFX[6] PFX[7] IP (Ch) IP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SP (Dh) -- SP IV -- -- -- LC[0] LC[1] -- -- -- -- -- -- -- -- DPC (Eh) -- -- -- OFFS DPC GR GRL BP GRS GRH GRXL FP -- -- -- -- DP (Fh) -- -- -- DP[0] -- -- -- DP[1] -- -- -- -- -- -- -- -- Note: Registers in italics are read-only. Registers in bold are 16-bit wide. 30 ______________________________________________________________________________________ Table 2. System Register Bit and Reset Values REGISTER BIT 14 -- 0 CLR 0 Z 1 -- 0 IMS 0 TAP 1 IIS 0 XTRC s* POR s* A[n] (16 Bits) 0 PFX[n] (16 Bits) 0 IP (16 Bits) 0 -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LC[1] (16 Bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV (16 Bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LC[0] (16 Bits) -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 -- 0 0 -- 0 0 -- 0 1 0 0 1 0 SP (4 Bits) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s* 0 0 EWDI WD1 WD0 0 0 0 -- RGMD STOP 0 WDIF 0 0 0 0 0 SWB -- II5 II4 II3 0 0 0 0 0 II2 0 PMME 0 WTRF s* -- CDA1 CDA0 -- ROD 0 0 0 0 0 -- IM5 IM4 IM3 IM2 0 PWL s* II1 0 CD1 0 EWT s* 0 0 0 0 0 0 IM1 -- CGDS -- -- -- INS 0 0 0 0 0 0 0 IGE 0 IM0 0 -- 0 II0 0 CD0 0 RWT 0 S -- GPF1 GPF0 OV C E 0 0 0 0 0 0 0 IDS -- -- -- MOD2 MOD1 MOD0 0 0 0 0 0 0 0 -- -- -- AP (4 Bits) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REGISTER 15 AP APC PSF IC IMR SC IIR CKCN WDCN A[n] (0..15) 0 PFX[n] (0..7) 0 IP 1 SP -- 0 IV 0 LC[0] 0 LC[1] 0 MAXQ7667 ______________________________________________________________________________________ *Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the MAXQ7667 User's Guide for more information. 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 31 MAXQ7667 REGISTER BIT 14 OFFS (8 Bits) 0 -- 0 GR13 0 GRL7 0 BP (16 Bits) 0 GRS13 0 GR15 0 GRXL7 0 FP (16 Bits) 0 DP[0] (16 Bits) 0 DP[1] (16 Bits) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GRXL6 GRXL5 GRXL4 0 0 0 0 0 0 0 0 0 0 0 0 GRXL3 GR14 GR13 GR12 GR11 0 0 0 0 0 0 0 0 0 0 0 GR10 0 GRXL2 0 GRS12 GRS11 GRS10 GRS9 GRS8 GRS7 GRS6 GRS5 GRS4 GRS3 GRS2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GRS1 0 GR9 0 GRXL1 0 0 GRS0 0 GR8 0 GRXL0 0 0 0 0 0 0 0 GRL6 GRL5 GRL4 GRL3 GRL2 GRL1 0 0 0 0 0 0 0 0 0 0 0 0 0 GRL0 0 GR12 GR11 GR10 GR9 GR8 GR7 GR6 GR5 GR4 GR3 GR2 GR1 GR0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 -- -- -- -- -- -- -- -- -- WBS2 WBS1 WBS0 SDPS1 SDPS0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 32 Table 2. System Register Bit and Reset Values (continued) REGISTER 15 OFFS DPC -- 0 GR GR15 GR14 0 GRL BP 0 GRS GRS15 GRS14 0 GRH GRXL GRXL15 GRXL14 GRXL13 GRXL12 GRXL11 GRXL10 GRXL9 GRXL8 0 FP 0 DP[0] 0 DP[1] 0 ______________________________________________________________________________________ *Bits indicated by an "s" are only affected by a POR and not by other forms of reset. These bits are set to 0 after a POR. Refer to the MAXQ7667 User's Guide for more information. 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Table 3. Peripheral Register Map REGISTER INDEX 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh MODULE NAME (BASE SPECIFIER) M0 (0h) PO0 PO1 -- EIF0 EIF1 -- -- -- PI0 PI1 -- EIE0 EIE1 -- -- -- PD0 PD1 -- EIES0 EIES1 -- -- -- PS0 PS1 -- PR0 PR1 -- -- -- M1 (1h) MCNT MA MB MC2 MC1 MC0 SPIB SPICN SPICF SPICK -- -- MC1R MC0R SCNT STIM SALM FPCTL -- -- -- -- -- RCTRM -- -- -- -- ID0 ID1 -- -- M2 (2h) T2CNA0 T2H0 T2RH0 T2CH0 T2CNA1 T2H1 T2RH1 T2CH1 T2CNB0 T2V0 T2R0 T2C0 T2CNB1 T2V1 T2R1 T2C1 T2CFG0 T2CFG1 -- -- -- -- -- -- ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD -- M3 (3h) T2CNA2 T2H2 T2RH2 T2CH2 -- CNT1 SCON SBUF T2CNB2 T2V2 T2R2 T2C2 FSTAT ERRR CHKSUM ISVEC T2CFG2 STA0 SMD FCON CNT0 CNT2 IDFB SADDR SADEN BT TMR -- -- -- -- -- M4 (4h) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- M5 (5h) BPH BTRN SARC RCVC PLLF AIE CMPC CMPT ASR SARD LPFC OSCC BPFI BPFO LPFD LPFF APE -- FGAIN B1COEF B2COEF B3COEF A2A A2B -- A2D -- A3A A3B -- A3D -- ______________________________________________________________________________________ 33 MAXQ7667 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 34 13 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA13 0 MB13 0 MC213 0 MC113 0 MC013 0 SPIB13 0 -- 0 -- 0 -- 0 -- 0 MC1R13 0 MC0R13 0 12 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA12 0 MB12 0 MC212 0 MC112 0 MC012 0 SPIB12 0 -- 0 -- 0 -- 0 -- 0 MC1R12 0 MC0R12 0 11 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA11 0 MB11 0 MC211 0 MC111 0 MC011 0 SPIB11 0 -- 0 -- 0 -- 0 -- 0 MC1R11 0 MC0R11 0 10 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA10 0 MB10 0 MC210 0 MC110 0 MC010 0 SPIB10 0 -- 0 -- 0 -- 0 -- 0 MC1R10 0 MC0R10 0 9 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA9 0 MB9 0 MC29 0 MC19 0 MC09 0 SPIB9 0 -- 0 -- 0 -- 0 -- 0 MC1R9 0 MC0R9 0 REGISTER BIT 8 7 -- PO07 0 1 -- PO17 0 1 -- IE7 0 0 -- IE7 0 0 -- PI07 0 ST -- PI17 0 ST -- EX7 0 0 -- EX7 0 0 -- PD07 0 0 -- PD17 0 0 -- IT7 0 0 -- IT7 0 0 -- PS07 0 0 -- PS17 0 0 -- PR07 0 1 -- PR17 0 1 -- OF 0 0 MA8 MA7 0 0 MB8 MB7 0 0 MC28 MC27 0 0 MC18 MC17 0 0 MC08 MC07 0 0 SPIB8 SPIB7 0 0 -- STBY 0 0 -- ESPII 0 0 -- SPICK7 0 0 -- FBUSY 0 1 MC1R8 MC1R7 0 0 MC0R8 MC0R7 0 0 6 PO06 1 PO16 1 IE6 0 IE6 0 PI06 ST PI16 ST EX6 0 EX6 0 PD06 0 PD16 0 IT6 0 IT6 0 PS06 0 PS16 0 PR06 1 PR16 1 MCW 0 MA6 0 MB6 0 MC26 0 MC16 0 MC06 0 SPIB6 0 SPIC 0 SAS 0 SPICK6 0 -- 0 MC1R6 0 MC0R6 0 5 PO05 1 PO15 1 IE5 0 IE5 0 PI05 ST PI15 ST EX5 0 EX5 0 PD05 0 PD15 0 IT5 0 IT5 0 PS05 0 PS15 0 PR05 1 PR15 1 CLD 0 MA5 0 MB5 0 MC25 0 MC15 0 MC05 0 SPIB5 0 ROVR 0 -- 0 SPICK5 0 -- 0 MC1R5 0 MC0R5 0 4 PO04 1 PO14 1 IE4 0 IE4 0 PI04 ST PI14 ST EX4 0 EX4 0 PD04 0 PD14 0 IT4 0 IT4 0 PS04 0 PS14 0 PR04 1 PR14 1 SQU 0 MA4 0 MB4 0 MC24 0 MC14 0 MC04 0 SPIB4 0 WCOL 0 -- 0 SPICK4 0 -- 0 MC1R4 0 MC0R4 0 3 PO03 1 PO13 1 IE3 0 IE3 0 PI03 ST PI13 ST EX3 0 EX3 0 PD03 0 PD13 0 IT3 0 IT3 0 PS03 0 PS13 0 PR03 1 PR13 1 OPCS 0 MA3 0 MB3 0 MC23 0 MC13 0 MC03 0 SPIB3 0 MODF 0 -- 0 SPICK3 0 -- 0 MC1R3 0 MC0R3 0 2 PO02 1 PO12 1 IE2 0 IE2 0 PI02 ST PI12 ST EX2 0 EX2 0 PD02 0 PD12 0 IT2 0 IT2 0 PS02 0 PS12 0 PR02 1 PR12 1 MSUB 0 MA2 0 MB2 0 MC22 0 MC12 0 MC02 0 SPIB2 0 MODFE 0 CHR 0 SPICK2 0 FC2 0 MC1R2 0 MC0R2 0 1 PO01 1 PO11 1 IE1 0 IE1 0 PI01 ST PI11 ST EX1 0 EX1 0 PD01 0 PD11 0 IT1 0 IT1 0 PS01 0 PS11 0 PR01 1 PR11 1 MMAC 0 MA1 0 MB1 0 MC21 0 MC11 0 MC01 0 SPIB1 0 MSTM 0 CKPHA 0 SPICK1 0 FC1 0 MC1R1 0 MC0R1 0 0 PO00 1 PO10 1 IE0 0 IE0 0 PI00 ST PI10 ST EX0 0 EX0 0 PD00 0 PD10 0 IT0 0 IT0 0 PS00 0 PS10 0 PR00 1 PR10 1 SUS 0 MA0 0 MB0 0 MC20 0 MC10 0 MC00 0 SPIB0 0 SPIEN 0 CKPOL 0 SPICK0 0 FC0 0 MC1R0 0 MC0R0 0 Table 4. Peripheral Register Bit Functions and Reset Values REGISTER PO0 PO1 EIF0 EIF1 PI0 PI1 EIE0 EIE1 PD0 PD1 EIES0 EIES1 PS0 PS1 PR0 PR1 MCNT MA MB MC2 MC1 MC0 SPIB SPICN SPICF ______________________________________________________________________________________ SPICK FCNTL MC1R MC0R 15 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA15 0 MB15 0 MC215 0 MC115 0 MC015 0 SPIB15 0 -- 0 -- 0 -- 0 -- 0 MC1R15 0 MC0R15 0 14 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 MA14 0 MB14 0 MC214 0 MC114 0 MC014 0 SPIB14 0 -- 0 -- 0 -- 0 -- 0 MC1R14 0 MC0R14 0 Table 4. Peripheral Register Bit Functions and Reset Values (continued) REGISTER SCNT STIM SALM FPCNTL RCTRM ID0 ID1 T2CNA0 T2H0 T2RH0 T2CH0 T2CNA1 T2H1 T2RH1 T2CH1 T2CNB0 T2V0 T2R0 T2C0 T2CNB1 T2V1 T2R1 T2C1 T2CFG0 T2CFG1 ICDT0 ICDT1 MAXQ7667 ______________________________________________________________________________________ ICDC 15 -- 0 STIM15 0 SALM15 0 -- 0 -- 0 ID015 0 ID115 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V015 0 T2R015 0 T2C015 0 -- 0 T2V115 0 T2R115 0 T2C115 0 -- 0 -- 0 ICDT015 DB ICDT115 DB -- 0 14 -- 0 STIM14 0 SALM14 0 -- 0 -- 0 ID014 0 ID114 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V014 0 T2R014 0 T2C014 0 -- 0 T2V114 0 T2R114 0 T2C114 0 -- 0 -- 0 ICDT014 DB ICDT114 DB -- 0 13 -- 0 STIM13 0 SALM13 0 -- 0 -- 0 ID013 0 ID113 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V013 0 T2R013 0 T2C013 0 -- 0 T2V113 0 T2R113 0 T2C113 0 -- 0 -- 0 ICDT013 DB ICDT113 DB -- 0 12 -- 0 STIM12 0 SALM12 0 -- 0 -- 0 ID012 0 ID112 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V012 0 T2R012 0 T2C012 0 -- 0 T2V112 0 T2R112 0 T2C112 0 -- 0 -- 0 ICDT012 DB ICDT112 DB -- 0 11 STDIV2 0 STIM11 0 SALM11 0 -- 0 -- 0 ID011 0 ID111 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V011 0 T2R011 0 T2C011 0 -- 0 T2V111 0 T2R111 0 T2C111 0 -- 0 -- 0 ICDT011 DB ICDT111 DB -- 0 10 STDIV1 0 STIM10 0 SALM10 0 -- 0 -- 0 ID010 0 ID110 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V010 0 T2R010 0 T2C010 0 -- 0 T2V110 0 T2R110 0 T2C110 0 -- 0 -- 0 ICDT010 DB ICDT110 DB -- 0 9 STDIV0 0 STIM9 0 SALM9 0 -- 0 -- 0 ID09 0 ID19 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 -- 0 T2V09 0 T2R09 0 T2C09 0 -- 0 T2V19 0 T2R19 0 T2C19 0 -- 0 -- 0 ICDT09 DB ICDT19 DB -- 0 REGISTER BIT 8 7 SSYNC_EN SALIE 0 0 STIM8 STIM7 0 0 SALM8 SALM7 0 0 -- -- 0 0 RCTRM8 RCTRM7 0 0 ID08 ID07 0 0 ID18 ID17 0 0 -- ET2 0 0 -- T2H07 0 0 -- T2RH07 0 0 -- T2CH07 0 0 -- ET2 0 0 -- T2H17 0 0 -- T2RH17 0 0 -- T2CH17 0 0 -- ET2L 0 0 T2V08 T2V07 0 0 T2R08 T2R07 0 0 T2C08 T2C07 0 0 -- ET2L 0 0 T2V18 T2V17 0 0 T2R18 T2R17 0 0 T2C18 T2C17 0 0 -- T2C1 0 0 -- T2C1 0 0 ICDT08 ICDT07 DB DB ICDT18 ICDT17 DB DB -- DME 0 DW 6 SALMF 0 STIM6 0 SALM6 0 -- 0 RCTRM6 0 ID06 0 ID16 0 T2OE0 0 T2H06 0 T2RH06 0 T2CH06 0 T2OE0 0 T2H16 0 T2RH16 0 T2CH16 0 T2OE1 0 T2V06 0 T2R06 0 T2C06 0 T2OE1 0 T2V16 0 T2R16 0 T2C16 0 T2DIV2 0 T2DIV2 0 ICDT06 DB ICDT16 DB -- 0 5 -- 0 STIM5 0 SALM5 0 -- 0 RCTRM5 0 ID05 0 ID15 0 T2POL0 0 T2H05 0 T2RH05 0 T2CH05 0 T2POL0 0 T2H15 0 T2RH15 0 T2CH15 0 T2POL1 0 T2V05 0 T2R05 0 T2C05 0 T2POL1 0 T2V15 0 T2R15 0 T2C15 0 T2DIV1 0 T2DIV1 0 ICDT05 DB ICDT15 DB REGE DW 4 -- 0 STIM4 0 SALM4 0 -- 0 RCTRM4 0 ID04 0 ID14 0 TR2L 0 T2H04 0 T2RH04 0 T2CH04 0 TR2L 0 T2H14 0 T2RH14 0 T2CH14 0 -- 0 T2V04 0 T2R04 0 T2C04 0 -- 0 T2V14 0 T2R14 0 T2C14 0 T2DIV0 0 T2DIV0 0 ICDT04 DB ICDT14 DB -- 0 3 -- 0 STIM3 0 SALM3 0 -- 0 RCTRM3 0 ID03 0 ID13 0 TR2 0 T2H03 0 T2RH03 0 T2CH03 0 TR2 0 T2H13 0 T2RH13 0 T2CH13 0 TF2 0 T2V03 0 T2R03 0 T2C03 0 TF2 0 T2V13 0 T2R13 0 T2C13 0 T2MD 0 T2MD 0 ICDT03 DB ICDT13 DB CMD3 DW 2 -- 0 STIM2 0 SALM2 0 -- 0 RCTRM2 0 ID02 0 ID12 0 CPRL2 0 T2H02 0 T2RH02 0 T2CH02 0 CPRL2 0 T2H12 0 T2RH12 0 T2CH12 0 TF2L 0 T2V02 0 T2R02 0 T2C02 0 TF2L 0 T2V12 0 T2R12 0 T2C12 0 CCF1 0 CCF1 0 ICDT02 DB ICDT12 DB CMD2 DW 1 SALME 0 STIM1 0 SALM1 0 -- 0 RCTRM1 0 ID01 0 ID11 0 SS2 0 T2H01 0 T2RH01 0 T2CH01 0 SS2 0 T2H.1 0 T2RH11 0 T2CH11 0 TCC2 0 T2V01 0 T2R01 0 T2C01 0 TCC2 0 T2V11 0 T2R11 0 T2C11 0 CCF0 0 CCF0 0 ICDT01 DB ICDT11 DB CMD1 DW 0 STIME 0 STIM0 0 SALM0 0 DPMG 0 RCTRM0 0 ID00 0 ID10 0 G2EN 0 T2H00 0 T2RH00 0 T2CH00 0 G2EN 0 T2H10 0 T2RH10 0 T2CH10 0 TC2L 0 T2V00 0 T2R00 0 T2C00 0 TC2L 0 T2V10 0 T2R10 0 T2C10 0 C/T2 0 C/T2 0 ICDT00 DB ICDT10 DB CMD0 DW 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 35 MAXQ7667 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 36 REGISTER BIT 8 7 -- -- 0 0 -- ICDB.7 0 0 ICDA8 ICDA7 0 0 ICDD8 ICDD7 0 0 -- ET2 0 0 -- T2H27 0 0 -- T2RH27 0 0 -- T2CH27 0 0 -- RTN 0 1 -- SM0/FE 0 0 -- SBUF7 0 0 -- ET2L 0 0 T2V28 T2V27 0 0 T2R28 T2R27 0 0 T2C28 T2C27 0 0 -- -- 0 0 -- -- 0 0 CHKSUM8 CHKSUM7 0 0 -- -- 0 0 -- T2C1 0 0 -- -- 0 0 -- EIR 0 0 -- FTF 0 0 -- WU 0 1 -- -- 0 0 IDFBH0 -- 1 0 -- SADDR7 0 0 -- SADEN7 0 0 6 -- 0 ICDB.6 0 ICDA6 0 ICDD6 0 T2OE0 0 T2H26 0 T2RH26 0 T2CH26 0 CK 0 SM1 0 SBUF6 0 T2OE1 0 T2V26 0 T2R26 0 T2C26 0 -- 0 OTE 0 CHKSUM6 0 -- 0 T2DIV2 0 -- 0 OFS 0 FRF 0 FP1 0 -- 0 -- 0 SADDR6 0 SADEN6 0 5 -- 0 ICDB.5 0 ICDA5 0 ICDD5 0 T2POL0 0 T2H25 0 T2RH25 0 T2CH25 0 FL5 0 SM2 0 SBUF5 0 T2POL1 0 T2V25 0 T2R25 0 T2C25 0 TFF 0 DME 0 CHKSUM5 0 -- 0 T2DIV1 0 -- 0 -- 0 TXFT1 0 FP0 0 -- 0 IDFBL5 0 SADDR5 0 SADEN5 0 4 -- 0 ICDB.4 0 ICDA4 0 ICDD4 0 TR2L 0 T2H24 0 T2RH24 0 T2CH24 0 FL4 0 REN 0 SBUF4 0 -- 0 T2V24 0 T2R24 0 T2C24 0 TFAE 0 CKE 0 CHKSUM4 0 -- 0 T2DIV0 0 -- 0 -- 0 TXFT0 0 INE 0 DMIS 0 IDFBL4 0 SADDR4 0 SADEN4 0 3 PSS1 0 ICDB.3 0 ICDA3 0 ICDD3 0 TR2 0 T2H23 0 T2RH23 0 T2CH23 0 FL3 0 TB8 0 SBUF3 0 TF2 0 T2V23 0 T2R23 0 T2C23 0 TFE 1 P1 0 CHKSUM3 0 ISVEC3 1 T2MD 0 -- 0 -- 0 RXFT1 0 AUT 1 PM 0 IDFBL3 0 SADDR3 0 SADEN3 0 2 PSS0 0 ICDB.2 0 ICDA2 0 ICDD2 0 CPRL2 0 T2H22 0 T2RH22 0 T2CH22 0 FL2 0 RB8 0 SBUF2 0 TF2L 0 T2V22 0 T2R22 0 T2C22 0 RFF 0 PIE 0 CHKSUM2 0 ISVEC2 1 CCF1 0 -- 0 IE 0 RXFT0 0 INIT 0 HDO 0 IDFBL2 0 SADDR2 0 SADEN2 0 1 SPE 0 ICDB.1 0 ICDA1 0 ICDD1 0 SS2 0 T2H21 0 T2RH21 0 T2CH21 0 FL1 0 TI 0 SBUF1 0 TCC2 0 T2V21 0 T2R21 0 T2C21 0 RFAF 0 P0 0 CHKSUM1 0 ISVEC1 1 CCF0 0 INP 0 SMOD 0 OE 0 LUN1 0 FBS 0 IDFBL1 0 SADDR1 0 SADEN1 0 0 TXC 0 ICDB.0 0 ICDA0 0 ICDD0 0 G2EN 0 T2H20 0 T2RH20 0 T2CH20 0 FL0 0 RI 0 SBUF0 0 TC2L 0 T2V20 0 T2R20 0 T2C20 0 RFE 1 POE 0 CHKSUM0 0 ISVEC0 1 C/T2 0 BUSY 0 FEDE 0 FEN 0 LUN0 0 BTH 0 IDFBL0 0 SADDR0 0 SADEN0 0 Table 4. Peripheral Register Bit Functions and Reset Values (continued) REGISTER ICDF ICDB ICDA ICDD T2CNA2 T2H2 T2RH2 T2CH2 CNT1 SCON SBUF T2CNB2 T2V2 T2R2 T2C2 FSTAT ERRR CHKSUM ISVEC T2CFG2 STA0 SMD FCON CNT0 CNT2 ______________________________________________________________________________________ IDFB SADDR SADEN 15 14 13 12 11 10 9 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 ICDA15 ICDA14 ICDA13 ICDA12 ICDA11 ICDA10 ICDA9 0 0 0 0 0 0 0 ICDD15 ICDD14 ICDD13 ICDD12 ICDD11 ICDD10 ICDD9 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 T2V215 T2V214 T2V213 T2V212 T2V211 T2V210 T2V29 0 0 0 0 0 0 0 T2R215 T2R214 T2R213 T2R212 T2R211 T2R210 T2R29 0 0 0 0 0 0 0 T2C215 T2C214 T2C213 T2C212 T2C211 T2C210 T2C29 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 CHKSUM15 CHKSUM14 CHKSUM13 CHKSUM12 CHKSUM11 CHKSUM10 CHKSUM9 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- IDFBH5 IDFBH4 IDFBH3 IDFBH2 IDFBH1 0 0 1 1 1 1 1 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 -- -- -- -- -- -- -- 0 0 0 0 0 0 0 Table 4. Peripheral Register Bit Functions and Reset Values (continued) REGISTER BT TMR BPH BTRN SARC RCVC PLLF AIE CMPC CMPT ASR SARD LPFC OSCC BPFI BPFO LPFD LPFF RSARE 0 BGE 0 LRIOPD 0 LRDPD 0 LRAPD 0 VDBE 0 15 BT15 0 TMR15 0 BSTT 0 BDIV3 1 -- 0 -- 0 -- 0 -- 0 CMPP 0 CMPT15 0 VIOLVL 0 -- 0 FFIL3 0 -- 0 BPFI15 0 BPFO15 0 LPFD15 0 LPFF15 VABE 0 SARE 0 PLLE 0 MDE 0 LNAE 0 BIASE 0 14 BT14 0 TMR14 0 BDS 0 BDIV2 0 -- 0 -- 0 -- 0 -- 0 CMPH14 0 CMPT14 0 DVLVL 0 -- 0 FFIL2 0 -- 0 BPFI14 0 BPFO14 0 LPFD14 0 LPFF14 13 BT13 0 TMR13 0 -- 0 BDIV1 0 -- 0 -- 0 -- 0 -- 0 CMPH13 0 CMPT13 0 AVLVL 0 -- 0 FFIL1 0 -- 0 BPFI13 0 BPFO13 0 LPFD13 0 LPFF13 12 BT12 0 TMR12 0 -- 0 BDIV0 1 -- 0 -- 0 -- 0 -- 0 CMPH12 0 CMPT12 0 CMPLVL 0 -- 0 FFIL0 0 -- 0 BPFI12 0 BPFO12 0 LPFD12 0 LPFF12 11 BT11 0 TMR11 0 -- 0 BPOL 0 SARMX2 0 -- 0 -- 0 -- 0 CMPH11 0 CMPT11 0 -- 0 SARD11 0 FFDP3 0 -- 0 BPFI11 0 BPFO11 0 LPFD11 0 LPFF11 10 BT10 0 TMR10 0 -- 0 BCKS 1 SARMX1 0 -- 0 PLLC1 0 -- 0 CMPH10 0 CMPT10 0 -- 0 SARD10 0 FFDP2 0 -- 0 BPFI10 0 BPFO10 0 LPFD10 0 LPFF10 9 BT9 0 TMR9 0 BPH9 0 BTRI 0 SARMX0 0 -- 0 PLLC0 0 -- 0 CMPH9 0 CMPT9 0 -- 0 SARD9 0 FFDP1 0 -- 0 BPFI9 0 BPFO9 0 LPFD9 0 LPFF9 6 BT6 0 TMR6 0 BPH6 0 BCTN6 0 SARDUL 0 LNAISEL0 0 PLLF6 0 VIBIE 0 CMPH6 0 CMPT6 0 VIBI 0 SARD6 0 -- 0 -- 0 BPFI6 0 BPFO6 0 LPFD6 0 LPFF6 5 BT5 0 TMR5 0 BPH5 0 BCTN5 0 SARRSEL 0 -- 0 PLLF5 0 VDBIE 0 CMPH5 0 CMPT5 0 VDBI 0 SARD5 0 -- 0 -- 0 BPFI5 0 BPFO5 0 LPFD5 0 LPFF5 4 BT4 0 TMR4 0 BPH4 0 BCTN4 0 SARASD 0 RCVGN4 0 PLLF4 0 VABIE 0 CMPH4 0 CMPT4 0 VABI 0 SARD4 0 -- 0 -- 0 BPFI4 0 BPFO4 0 LPFD4 0 LPFF4 3 BT3 0 TMR3 0 BPH3 0 BCTN3 0 SARBY 0 RCVGN3 0 PLLF3 0 CMPIE 0 CMPH3 0 CMPT3 0 CMPI 0 SARD3 0 FFLD 0 SARCD1 0 BPFI3 0 BPFO3 0 LPFD3 0 LPFF3 2 BT2 0 TMR2 0 BPH2 0 BCTN2 0 SARC2 0 RCVGN2 0 PLLF2 0 LFLIE 0 CMPH2 0 CMPT2 0 LPFFL 0 SARD2 0 FFLS2 1 SARCD0 0 BPFI2 0 BPFO2 0 LPFD2 0 LPFF2 1 BT1 0 TMR1 0 BPH1 0 BCTN1 0 SARC1 0 RCVGN1 0 PLLF1 0 LPFIE 0 CMPH1 0 CMPT1 0 LPFRDY 0 SARD1 0 FFLS1 1 XTE 0 BPFI1 0 BPFO1 0 LPFD1 0 LPFF1 0 BT0 0 TMR0 0 BPH0 0 BCTN0 0 SARC0 0 RCVGN0 0 PLLF0 0 SARIE 0 CMPH0 0 CMPT0 0 SARRDY 0 SARD0 0 FFLS0 1 RCE 0 BPFI0 0 BPFO0 0 LPFD0 0 LPFF0 MAXQ7667 ______________________________________________________________________________________ APE -- 0 RBUFE 0 REGISTER BIT 8 7 BT8 BT7 0 0 TMR8 TMR7 0 0 BPH8 BPH7 0 0 BGT BCTN7 0 0 SARDIF SARBIP 0 0 LNAOSEL LNAISEL1 0 0 PLLF8 PLLF7 1 0 -- XTIE 0 0 CMPH8 CMPH7 0 0 CMPT8 CMPT7 0 0 XTRDY XTI 0 0 SARD8 SARD7 0 0 FFDP0 FFOV 0 0 -- -- 0 0 BPFI8 BPFI7 0 0 BPFO8 BPFO7 0 0 LPFD8 LPFD7 0 0 LPFF8 LPFF7 NOT INITIALIZED VIBE VDPE 0 1 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 37 MAXQ7667 13 12 11 10 9 8 6 5 4 3 2 1 0 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System 38 REGISTER BIT 7 [15:0] 0x7B5C [15:0] 0x2492 [15:0] 0x5820 [15:0] 0x2410 [15:0] 0x30F4 [15:0] 0x3369 [15:0] 0x3A28 [15:0] 0xE20E [15:0] 0xE1E3 [15:0] 0xE559 Table 4. Peripheral Register Bit Functions and Reset Values (continued) REGISTER 15 14 FGAIN B1COEF B2COEF B3COEF A2A A2B A2D A3A A3B A3D Bits indicated by "ST" reflect the input signal state. Bits indicated by "P" are cleared to 00h on POR and then, if required, initialized to a value stored within the flash information block. Bits indicated by "DB" have read/write access only in background or debug mode. These bits are cleared after a POR. Bits indicated by "DW" are only written to in debug mode. These bits are cleared after a POR. ______________________________________________________________________________________ The OSCC register is cleared to 0002h after a POR and is not affected by other forms of reset. 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System Applications Information Development and Technical Support A variety of highly versatile, affordably priced development tools for this C are available from Maxim and third-party suppliers, including: - Compilers - Evaluation kit - Integrated development environments (IDEs) - JTAG-to-serial converters for programming and debugging A partial list of development tool vendors can be found at www.maxim-ic.com/MAXQ_tools. Technical support is available at https://support.maximic.com/micro. TOP VIEW AINO REFBG REF AGND AVDD AGND ECHOP ECHON AGND AVDD FILT RESET Pin Configuration MAXQ7667 36 35 34 33 32 31 30 29 28 27 26 25 AIN1 AIN2 AIN3 AIN4 N.C. DVDD DGND DVDDIO BURST P1.0/TDO P1.1/TMS P1.2/TDI 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 GATE5 REG3P3 REG2P5 XOUT XIN DVDD DGND DVDDIO PO.7/T2B PO.6/T2 PO.5/T1 PO.4/TOB MAXQ7667 Additional Documentation Designers must have the following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. The following documents can be downloaded from www.maxim-ic.com/microcontrollers. * This MAXQ7667 data sheet, which contains electrical/timing specifications and pin descriptions. * The MAXQ7667 revision-specific errata sheet (www.maxim-ic.com/errata). * The MAXQ7667 Family User's Guide, which contains detailed information on core features and operation, including programming. + 13 1 2 3 4 5 6 7 8 9 10 11 12 PROCESS: CMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 48 LQFP PACKAGE CODE C48+2 DOCUMENT NO. 21-0054 ______________________________________________________________________________________ P1.3/TCK P1.4/MOSI P1.5/MISO P1.6/SCLK P1.7/SYNC/SS DVDD DGND DVDDIO PO.O/URX PO.1/UTX PO.2/TXEN PO.3/TO/ADCCTL LQFP Chip Information Package Information 39 16-Bit, RISC, Microcontroller-Based, Ultrasonic Distance-Measuring System MAXQ7667 Revision History REVISION NUMBER 0 1 REVISION DATE 4/09 7/09 Initial release Updated Ordering Information to indicate automotive qualified part DESCRIPTION PAGES CHANGED -- 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 40 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. |
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