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M64895BGP
I2C BUS FREQUENCY SYNTHESIZER FOR TV/VTR
REJ03F0018-0100Z Rev.1.0 Aug.27.2003
Description
The M64895BGP is a semiconductor integrated circuit consisting of PLL frequency synthesizer for TV/VCR using I2C BUS control. It contains the prescaler with operating up to 1.3 GHz, 4 band drivers and tuning. amplifier for direct tuning.
Features
* * * * * * * * * 4 integrated PNP band drivers (Io = 40 mA, Vsat = 0.2 V typ@Vcc 1 to 13.2 V) Built in tuning Amplifier for direct tuning. Low power dissipation (Icc = 20 mA, Vcc = 5 V) Built-in prescaler with input amplifier (fax = 1.3 GHz) PLL lock/unlock status display output (Built-in pull up resistor) I2C bus control (write mode only) X 3type of tuning steps (Division ratio 1/512, 1/640, 1/1024) with 4 MHz X'tal Programmable chip address Small package (16 Pin SSOP)
Application
* TV, VCR tuners
Block Diagram
XIN
16
ADS
15
S DA
14
S CL
13
LD
12
Vcc3
11
V tu
10
V in
9
OSC
2
I 2 C BUS RELIEVER
DIV
10
M IN CO NTER A U
1/ 32,1/ 33
5
LOCK D TECTOR E
AMP
SW ALLO CO NTER W U
4
PHASE DETECTOR
CHARGE PUMP
1/ 8
AMP
P.O RESET
BIAS
BAND DRIVER
1
2
3
4
5
6
7
8
fIN
GND
V cc1
V cc2
B S4
B S3
B S2
B S1
Rev.1.0, Aug.27 2003, page 1 of 11
M64895BGP
Pin Configuration (TOP VIEW)
PRESCALER INPUT GND SUPPLY VOLTAGE 1 SUPPLY VOLTAGE 2 fin GND Vcc1 Vcc2 BS4 BAND SW ITCHING OUTPUTS BS2 BS1 BS3
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10
Xin ADS SDA SCL LD Vcc3 Vtu Vin
CRYSTAL OSCILLATOR CHIP ADDRESS INPUT DATAINPUT CLOCK INPUT Lock OUTPUT SUPPLY VOLTAGE 3 TUNING OUTPUT FILTER INPUT
9
OUTLINE 16P2Z
Pin Description
Symbol fin GND Vcc1 Vcc2 BS4 BS3 BS2 BS1 Vin Pin No. 1 2 3 4 5 6 7 8 9 Pin name Prescaler input GND Power supply voltage 1 Power supply voltage 2 Band switching outputs Function Input for the VCO frequency. Ground to 0 V Power supply voltage terminal. 5.0 V+/-0.5 V Power supply for band switching. Vcc1 to 13.2 V PNP open collector method is used. When the band switching data is "H", the output is "ON". When it is "L", the output is "OFF". This is the output terminal for the LPF input and charge pump output. When the phase of the programmable divider output (f1/N) is ahead compared to the reference frequency (fref), the "source" current state becomes active. If it is lag, the "sink" current becomes active. If the phases are the same, the high impedance state becomes active. This supplies the tuning voltage. Power supply voltage for tuning voltage 28 to 35 V Lock detector is output. Programmable freq. Divider output and reference freq. output is selected by the test mode. Data is read into the shift register when the clock signal falls. Input for band SW and programmable frequency. divider set falls. Chip address sets it up with the input condition of terminal. 4.0 MHz crystal oscillator connected.
Filter input (Charge pump output)
Vtu Vcc3 LD/ftest SCL SDA ADS X in
10 11 12 13 14 15 16
Tuning output Power supply voltage 3 Lock detect/Test port Clock input Data input Address switching input This is connected to theCrystal oscillator.
Rev.1.0, Aug.27 2003, page 2 of 11
M64895BGP
Method of setting DATA
The input information of chip address and data of 2 or 4 bytes are received in I2C bus receiver. It shows a de definition of bus protocol admitted in the following. 1_STA 2_STA 3_STA 4_STA CA CB BB STO CA D1 D2 STO CA CB BB D1 D2 STO CA D1 D2 CB BB STO STA: Start condition STO: Stop condition CA: Chip address CB: Control data byte BB: Band S.W. data byte D1: Divider data byte D2: Divider data byte
The information of 5 bytes required for circuit operation are chip address, control data and band S.W.data of 2 bytes and divider data of 2 bytes. After the chip address input, 2 or 4 bytes can be received. Function bit contained the first and the third data byte to distinguish between divider data and control data band S.W. data, and "0" goes ahead of divider data and "1" goes ahead of control data, band S.W. data, The timing reading data show in under figure. Divider data uses 15 bits is read in at the rise of the eighth bit clock signal of the second byte divider data (D2). Control data (CB) and band SW-data (BB) is each read in the rise of eighth bits clock signal.
SDA address D1 D2 CB BB
SCL STA
1
8 D1&D2
1
8
1
8
1
8 STO
Read into latch
Read into latch
Read into latch
Write mode format
Byte 1 2 3 4 5 Address Byte Divider Byte 1 Divider Byte 2 Control Byte 1 Band SW Byte MSB 1 0 N7 1 X 1 N14 N6 CP X 0 N13 N5 T2 X 0 N12 N4 T1 X 0 N11 N3 T0 BS4 MA1 N10 N2 RSa BS3 MA0 N9 N1 RSb BS2 0 N8 N0 OS BS1 LSB A A A A A
Rev.1.0, Aug.27 2003, page 3 of 11
M64895BGP
Mode data set up method
X: Random, 0 or 1. normal "0" MA1, MAO: programmable Address Bit
Address input voltage 0 to 0.1 *Vcc1 Always valid 0.4*Vcc1 to 0.6*Vcc1 0.9*Vcc1 to Vcc1 MA1 0 0 1 1 MA 0 1 0 1
N14 to NO: How to set dividing ratio of the programmable the divider
Dividing ratio N = N14 (214 = 16384) +... +N0 (20 = 1) Therefore, the rage of division N is 1,024 to 32,768 (Example) frvco = fref*8*N = 3.90625 * 8 * N = 31.25 * N (kHz)
CP: Setting up the charge pump current of the phase comparator
CP 0 1 Charge pump current 70A 270A Mode Test Normal
T2, T1, T0: Setting up for the test mode
T2 0 0 1 1 1 1 T1 0 1 1 1 0 0 T0 X X 0 1 0 1 Charge pump Normal operation High impedance Sink Source High impedance High impedance 12 pin condition Lock output Lock output Lock output Lock output fref output f1/N output Mode Normal operation Test Test Test Test Test
Rev.1.0, Aug.27 2003, page 4 of 11
M64895BGP RSa, RSb: Set up for the reference Frequency division ratio
RSa 1 0 X RSb 1 1 0 division ratio 1/512 1/1024 1/640
OS: Set up the tuning amplifier
OS 0 1 Tuning voltage output ON OFF Mode Normal Test
Power on rest operation (Initial state the power is turned ON) BS4 to BS1 Charge pump Tuning amplifier Charge pump current :OFF : High impedance : OFF : 270 A
Frequency division ratio : 1/1024
Lock detector :H
Rev.1.0, Aug.27 2003, page 5 of 11
M64895BGP
Timing diagram
[START]condition
SDA
tBUF CL
tLOW
tr
tf
tHDSTA
tHDSTA [STOP] condition
tHDDAT
tHIGH tSUDAT tSUSTA
tSUSTO [STOP] condition
[START]condition
Crystal oscillator connection diagram
16 Crystal oscillator characteristics Actual resistance :less than300 Load capacitance :20pF
18pF 4MHz
Rev.1.0, Aug.27 2003, page 6 of 11
M64895BGP
Absolute maximum ratings
(Ta = -20C to 75C unless otherwise noted)
Parameter Standby voltage1 Standby voltage2 Standby voltage3 Input voltage Output voltage Voltage applied when the band output current is OFF Band output current ON the time when the band output is ON Power dissipation Operating temperature Storage temperature Symbols Vcc1 Vcc2 Vcc3 VI Vo VBSOFF IBSON tBSON Pd Topr Tstg Max. ratings 6.0 14.4 36.0 6.0 6.0 14.4 50.0 10 350 -20 to +75 -40 to +125 Units V V V V V V mA sec mW C C Conditions Pin3 Pin4 Pin11 Not to exceed Vcc1 Pin 12
Per 1 band output circuit 50 mA per 1 band output circuit 3 circuits are pin at same time, Ta = 75C
Recommended operating conditions
(Ta = -20C to 75C unless otherwise noted)
Parameter Standby voltage1 Standby voltage2 Standby voltage3 Operating frequency (1) Operating frequency (2) Band output current 5 to 8 Symbols Vcc1 Vcc2 Vcc3 fopr1 fopr2 IBDL Ratings 4.5 to 5.5 5.0 to 13.2 30 to 35 4.0 80 to 1300 0 to 40 Units V V V MHz MHz mA Conditions
Crystal oscillation circuit Normally 1 circuit is on. 2 circuits on at the same time is max. It is prohibited to have 3 or more circuits turned on at the same time.
Rev.1.0, Aug.27 2003, page 7 of 11
M64895BGP
Electrical Characteristics
(Ta = -20C to 75C, Vcc1 = 5.0 V Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameters Input terminals "H" input voltage "L" input voltage "H" input current "L" input current SDA output "L" output voltage Leak current Band SW Output voltage Leak current Tuning output Output voltage "H" Output voltage "L" Charge pump "H" output current "L" output current Leak current Supply current 1 Supply current 2 4circuits OFF 1 circuits ON, Output open Output current 40 mA Supply current 3 Symbol Test pin Test conditions Limits Min VIH VIL IIH IIL VOL ILO VBS lOIK1 13 to 14 13 to 14 13 to 14 13/14 14 14 5 to 8 5 to 8 3.0 -- -- -- -- -- 11.6 -- Typ -- -- -- -4/-14 -- -- 11.8 -- Max Vcc1+0.3 1.5 10 -10/-30 0.4 10 -- -10 V V A A V V A Unit
Vcc1 = 5.5 V, Vi = 4.0 V Vcc1 = 5.5 V, Vi = 0.4 V Vcc1 = 5.5 V, lc = 3 mA Vcc1 = 5.5 V, lc = 5.5 V Vcc2 = 12 V, lo = -40 mA Vcc2 = 12 V, Band SW is OFF Vo = 0 V Vcc3 = 33 V Vcc3 = 33 V Vcc1 = 5.0 V, Vo = 2.5 V Vcc1 = 5.0 V, Vo = 2.5 V Vcc1 = 5.0 V, Vo = 2.5 V Vcc1 = 5.5 V Vcc2 = 12 V
VtoH VtoL IOH IOL IcpLK ICC1 ICC2A ICC2B ICC2C ICC3
10 10 9 9 9 3 4 4 4 11
32.5 -- -- -- -- -- --
-- 0.2
-- 0.4
V V A A nA mA mA mA mA mA
270 70
-- 20 -- 6.0 46.0 3.0
370 110 50
30 0.3 8.0 48.0 4.0
Vcc2 = 12 V Vcc2 = 12 V, lo = -40 mA Vcc2 = 33 V, Output ON
-- -- --
Note: The typical values are at Vcc1 = 5.0 V, Vcc 2 = 12 V, Vcc3 = 33 V, Ta = +25C
Rev.1.0, Aug.27 2003, page 8 of 11
M64895BGP
Switching characteristics
(Ta = -20C to 75C, Vcc1 = 5.0 V, Vcc = 12 V, Vcc3 = 33 V, unless otherwise noted)
Parameter Symbol Test pin 1 1 Test conditions Limits Min Prescaler operating frequency Operating input voltage fopr Vin Vcc1 = 4.5 to 5.5 V Vin = Vinmin to Vinmax Vcc1 = 4.5 to 5.5 V 80 to 100 MHz 100 to 200 MHz 200 to 800 MHz 800 to 1000 MHz 1000 to 1300 MHz Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V Vcc1 = 4.5 to 5.5 V 80 -24 -27 -30 -27 -18 0 4.7 4 4.7 4 4.7 0 250 -- -- 4 Typ -- -- -- -- -- -- -- -- -- -- -- Max 1300 4 4 4 4 4 100 -- -- -- -- -- -- -- 1000 300 -- MHz dBm Unit used
Clock pulse frequency Bus free time Data hold time SCL low hold time SCL high hold time Set up time Data hold time Data set up time Rise time Fall time Set up time
fSCL tBUF tHDSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tR tF tSUSTO
13 14 13 13 13 13, 14 13, 14 13, 14 13, 14 13, 14 13, 14
kHz
s s s s s s
ns ns ns
-- -- -- -- --
s
Rev.1.0, Aug.27 2003, page 9 of 11
M64895BGP
Application example
BUILT-IN PLL TUNER
+5 V Vcc1to 12 V UHF VHF
1nF
+ 10 -
3
Vcc1
15
ADS
Vcc2 BS4 BS3 BS2 BS1
+B
4 5 6
BS2 BS4
BS3
4-BAND TUNER
IF
IF
7 8
BS1
M 64895BGP
MCU
SDA
1nF 1nF 14 13
f in
1
1000 pF
Lo
SCL
0.1u
1.5n
AGC
AGC
Vin
12
VT
9 10
56K
56K
2.2n
AFT
LOCK
Vtu
* 100P
Xin
16 18p 4MHz
GND Vcc3
2 11
Note) Filter constant is for reference. *Touch a capacitance because Filter circuit is instability.
+33 V BT
Rev.1.0, Aug.27 2003, page 10 of 11
M64895BGP
16P2Z-A
JEDEC Code - e b2 Weight(g) 0.08 Lead Material Cu Alloy
MMP
Plastic 16pin 225mil SSOP
Package Dimensions
EIAJ Package Code SSOP16-P-225-0.65
16
9
HE
E
L1
c z Z1 Detail G Detail F
L
Rev.1.0, Aug.27 2003, page 11 of 11
e1
Recommended Mount Pad F A
G
1
8
Symbol
D
b
x
M
e y x
A2
A1
A A1 A2 b c D E e HE L L1 z Z1 x y b2 e1 I2
Dimension in Millimeters Min Nom Max 1.9 - - - - 0.05 - 1.5 - 0.32 0.22 0.17 0.2 0.15 0.13 5.2 5.0 4.8 4.6 4.4 4.2 - - 0.65 6.5 6.2 5.9 0.6 0.4 0.2 - - 0.9 - 0.225 - - - 0.375 - - 0.13 0.1 - - 0 0 - - - 0 35 - - 5.72 - - 1.27
I2
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