 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 14-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32D869 FEATURES: * * * * * * * * 1.8V Operation Designed to drive low impedance nets SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Center input architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) * Available in 150-pin CTBGA package APPLICATIONS: * Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs * Optimized for DDR2-400/533 [PC2-3200/4300] Raw card L The SSTU32D869 is a 14-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32D869 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The SSTU32D869 includes a parity checking function. The SSTU32D869 accepts parity bits from the memory controller at its input pins PARIN[1:2], compares it with the data received on the D-inputs, and indicates whether a parity error has occured on its open-drain PTYERR[1:2] pins (active low). When used as a single device, the C1 inputs are tied low. In this configuration, the partial-parity-out (PPO[1:2]) and PTYERR[1:2] signals are produced two clock cycles after the corresponding data output. When used in pairs, the C1 inputs of the first register are tied low and the C1 inputs of the second register are tied high. The PTYERR[1:2] outputs of the first SSTU32D869 is left floating and the valid error information is latched on the PTYERR[1:2] outputs of the second SSTU32D869 . DESCRIPTION: This device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs are forced low. The LVCMOS RESET and Cx inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the DDR2 DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of a reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SSTU32D869 must ensure that the outputs will remain low, thus ensuring no glitches on the outputs. The device monitors the DCS input and will gate the Qn outputs from changing states when DCS is high. If the DCS input is low, the Qn outputs will function normally. The RESET input has priority over the DCS control and will force the Qn outputs low and the PTYERR[1:2] outputs high. The EF[0:3] inputs control the driver strength and slew rate for both the A and B outputs independently. This device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will fate the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn and PPO outputs will function normally. Also, if the DCS and CSR are high, the device will gate the PTYERR[1:2] outputs from changing states. If the DCS and CSR are low, the PTYERR[1:2] will function normally. The RESET input has priority over the DCS and CSR control. When driven low, they will force the Qn and PPO outputs low and the PTYERR[1:2] outputs high. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case the setup-time requirement for the DCS would be the same as for the other D data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled up to VDD through a pullup resistor. COMMERCIAL TEMPERATURE RANGE 1 c 2005 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. JANUARY 2005 DSC 6746/7 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM (1:2) (CS Active) VREF 2 PARIN1, PARIN2 D Q 2 2 2 PARITY GENERATOR AND CHECKER 2 PPO1, PPO2 PTYERR1, PTYERR2 R Q1A D1 D Q Q1B R 11 Q14A(1) D14 (1) D Q Q14B (1) R QCSA DCS0 D Q QCSB CSR R QCKEA DCKE D Q QCKEB R QODTA DODT D Q QODTB R RESET CLK CLK NOTE: 1. This range does not include D1, D4, and D7, and their corresponding outputs. 2 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE PIN CONFIGURATION(1) 1 A NB 2 VDD 3 EF0 4 PPO2 5 GND 6 VREF 7 GND 8 PARIN2 9 EF1 10 VDD 11 PYTERR2 B VDD NB VDD GND GND GND GND GND VDD NB VDD C QCKEA VDD NB GND NB GND NB GND NB VDD QCKEB D Q2A VDD GND NB DCKE NB D2 NB GND VDD Q2B E Q3A VDD NB D3 NB NC NB DODT NB C1 Q3B F QODTA VDD GND NB NC NB NC NB GND VDD QODTB G Q5A VDD GND D5 NB CLK NB D6 GND VDD Q5B H Q6A NB GND NB NC NB NC NB GND NB Q6B J K QCSA VDD NB NC NB RST NB CSR NB VDD QCSB VDD VDD GND GND NB NB NB GND VDD VDD VDD L Q8A VDD NB DCS NB CLK NB D8 NB VDD Q8B M N Q9A NB GND NB NC NB NC NB GND NB Q9B Q10A VDD GND D9 NB NC NB D10 GND VDD Q10B P Q11A VDD GND NB NC NB NC NB GND VDD Q11B R Q12A C1 NB D11 NB NC NB D12 NB VDD Q12B T Q13A VDD GND NB D13 NB D14 NB GND VDD Q13B U V Q14A VDD NB GND NB GND NB GND NB VDD Q14B VDD NB VDD GND GND GND GND GND VDD NB VDD W PYTERR1 VDD EF2 PARIN1 GND VREF GND PPO1 EF3 VDD NB 150-BALL CTBGA TOP VIEW NOTE: 1. The symmetrical center input design allows the front and back register of a pair to share the same pinout. This keeps the component library simple. 3 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 150 BALL CTBGA PACKAGE ATTRIBUTES Top Marking 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W A B C D E F G H J K L M N P R T U V W TOP VIEW BOTTOM VIEW SIDE VIEW 4 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE FUNCTION TABLE (EACH FLIP-FLOP) (1) Inputs RESET H H H H H H H H H H H H L DCS L L L L L L H H H H H H X or Floating CSR L L L H H H L L L H H H X or Floating CLK L or H L or H L or H L or H X or Floating CLK L or H L or H L or H L or H X or Floating Dx, DODT, DCKE L H X L H X L H X L H X X or Floating Qx Outputs L H Q0(2) L H Q0(2) L H Q0(2) Q0(2) Q0 Q0 (2) (2) QCSx Output L L Q0(2) L L Q0(2) H H Q0(2) H H Q0 (2) QODTx, QCKEx Outputs L H Q0(2) L H Q0(2) L H Q0(2) L H Q0(2) L L L NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. Output level before the indicated steady-state conditions were established. PARITY AND STANDBY FUNCTION TABLE(1) Inputs RESET H H H H H H H H H H L DCS L L L L X X X X H X X or Floating CSR X X X X L L L L H X X or Floating CLK L or H X or Floating CLK L or H X or Floating of Inputs = H (D1 - D14)(2) Even Odd Even Odd Even Odd Even Odd X X X or Floating PAR_IN(3) L L H H L L H H X X X or Floating PPO(3,4) L H H L L H H L PPO 0 PPO 0 L Outputs PTYERR(3,5) H L L H H L L H PTYERR0 PTYERR0 H NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW to HIGH = HIGH to LOW 2. This range does not include D1, D4, and D7. 3. PARIN1 is used to generate PPO1 and PTYERR1. PARIN2 is used to generate PPO2 and PTYERR2. 4. PAR_IN arrives one clock cycle (C1 = 0), or two clock cycles (C1 = 1), after the data to which it applies. 5. This transition assumes PTYERR[1:2] is HIGH at the crossing of CLK going HIGH and CLK going LOW. If PTYERR[1:2] is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 5 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE REGISTER TIMING RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 (1) tPD CLK to Q Q1 - Q14 (1) tSU tH PAR_IN1, PAR_IN2 PPO1,(2) PPO2 (2) tPD CLK to PPO PTYERR1, PTYERR2 (2) tPD CLK to PTYERR tPD CLK to PTYERR Timing Diagram for the First SSTU32D869 Device, C1 = 0 NOTES: 1. This range does not include D1, D4, and D7, and their corresponding outputs. 2. PAR_IN1 is used to generate PPO1 and PTYERR1. PAR_IN2 is used to generate PPO2 and PTYERR2. 6 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE REGISTER TIMING RESET DCS CSR n n+1 n+2 n+3 n+4 CLK CLK tSU tH D1 - D14 (1) tPD CLK to Q Q1 - Q14 (1) tSU tH PAR_IN1, PAR_IN2 (2) (2) PPO1, PPO2 (not used) PTYERR1, PTYERR2 (2) tPD CLK to PPO tPD CLK to PTYERR tPD CLK to PTYERR Timing Diagram for the Second SSTU32D869 Device Used in a Pair; C1 = 1 NOTES: 1. This range does not include D1, D4, and D7, and their corresponding outputs. 2. PAR_IN1 is used to generate PPO1 and PTYERR1. PAR_IN2 is used to generate PPO2 and PTYERR2. 7 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE PARITY LOGIC DIAGRAM Dn 11 11 D Q QnA QnB D D LATCHING AND (1) RESET FUNCTION PTYERR1, PTYERR2 PPO1, PPO2 (2) PARIN1,(2) PARIN2 D CLOCK NOTES: 1. This function holds the error for two cycles. See REGISTER TIMING diagram. 2. PAR_IN1 is used to generate PTYERR1. PAR_IN2 is used to generate PTYERR2. 8 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS (1) Symbol VDD VI (2,3) MODE SELECT Unit V V V mA mA mA mA C C1 0 1 Single Device, Front Second Device in Pair, Back Device Mode Description Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current VI < 0 VI > VDD Max. -0.5 to 2.5 -0.5 to 2.5 -0.5 to VDD +0.5 50 50 50 100 -65 to +150 VO(2,3) IIK IOK IO VDD TSTG Output Clamp Current VO < 0 VO > VDD Continuous Output Current, VO = 0 to VDD Continuous Current through each VDD or GND Storage Temperature Range OUTPUT CONTROL EF0,(1) EF3 0 0 1 1 EF1,(1) EF2 0 1 0 1 Output Standard Drive, Higher Slew Standard Drive, Standard Slew Higher Drive, Higher Slew Higher Drive, Standard Slew NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative voltage ratings may be exceeded if the ratings of the I/P and O/P clamp current are observed. 3. This value is limited to 2.5V maximum. NOTE: 1. EF0 and EF2 control QA outputs; EF1 and EF3 control QB outputs. 9 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TERMINAL FUNCTIONS Signal Group Terminal Name D1:D14 DCS (1) Type SSTL_18 SSTL_18 SSTL_18 Description DRAM function pins not associated with Chip Select DRAM inputs, re-driven only when Chip Select is LOW DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be LOW when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSR HIGH) when at least one Chip Select input is LOW. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock Ungated Inputs Chip Select Gated Inputs Chip Select Inputs DCKE, DODT Re-Driven Outputs Q1A:Q14A(1) Q1B:Q14B(1) QCSA, B QCKEA, B QODTA, B PARIN1, PARIN2 PPO1, PPO2 PTYERR1, PTYERR2 SSTL_18 Parity Input Partial Parity Output Parity Error Output SSTL_18 SSTL_18 Open Drain Input parity is received on pin PARIN, and should maintain odd parity across the D1:D14 inputs, at the rising edge of the clock PPO1 of the front register is connected to PAR_IN1 of the back register, and PPO2 to PAR_IN2, respectively. When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Chip Select Gate Enable. When HIGH, the D1:D14 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D1:D14 inputs will be latched and redriven on every rising edge of the clock. Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CLK). Configuration Pins. When C1 is LOW, the register is used as a single register, or as the first register when used in pairs. When C1 is HIGH, the register is used as the second register in a pair. Output Control Asynchronous Reset Input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. Input reference voltage for SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. Program Inputs CSR SSTL_18 Clock Inputs CLK, CLK C1 SSTL_18 1.8V LVCMOS 1.8V LVCMOS 1.8V LVCMOS 0.9V nominal Miscellaneous Inputs EF0:EF3 RESET VREF NOTE: 1. This range does not include D1, D4, and D7, and their corresponding outputs. 10 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA = 25C (1,2) Symbol VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL TA Parameter Supply Voltage Reference Voltage Termination Voltage Input Voltage AC High-Level Input Voltage AC Low-Level Input Voltage DC High-Level Input Voltage DC Low-Level Input Voltage High-Level Input Voltage Low-Level Input Voltage Common Mode Input Voltage Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature Data Inputs Data Inputs Data Inputs Data Inputs RESET, Cx RESET, Cx CLK, CLK CLK, CLK Min. 1.7 0.49 * VDD VREF- 40mV 0 VREF+ 250mV -- VREF+ 125mV -- 0.65 * VDD -- 0.675 600 -- -- 0 Typ. -- 0.5 * VDD VREF -- -- -- -- -- -- -- -- -- -- -- -- Max. 1.9 0.51 * VDD VREF+ 40mV VDD -- VREF- 250mV -- VREF- 125mV -- 0.35 * VDD 1.125 -- -8 +8 70 Unit V V V V V V V V V V V mV mA mA C NOTES: 1. The RESET and Cx inputs of the device must be held at valid levels (not floating) to ensure proper device operation. 2. The differential inputs must not be floating unless RESET is LOW. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0C to +70C, VDD = 1.8V 0.1V Symbol VOH VOL II IDD IDDD All Inputs Static Standby Static Operating Dynamic Operating (Clock Only) Dynamic Operating (Per Each Data Input) Data Inputs DCSn / CSR CI CLK and CLK RESET Parity Inputs Parameter Test Conditions VDD = 1.7V to 1.9V, IOH = - 6 mA VDD = 1.7V to 1.9V, IOL = +6 mA VI = VDD or GND IO = 0, VDD = 1.9V, RESET = GND IO = 0, VDD = 1.9V, RESET = VDD, VI = VIH (AC) or VIL (AC) IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), CLK and CLK Switching 50% Duty Cycle. IO = 0, VDD = 1.8V, RESET = VDD, VI = VIH (AC) or VIL (AC), 1:2 Mode, CLK and CLK Switching at 50% Duty Cycle. One Data Input Switching at Half Clock Frequency, 50% Duty Cycle. VI = VREF 250mV VI = VREF 250mV VICR = 0.9V, VID = 600mV VI = VDD or GND VI = VREF 250mV 2.5 4 4 2 2 -- -- -- -- -- 4 6 6 6 3 pF -- -- -- Min. 1.2 -- -- -- -- -- Typ. -- -- -- -- -- -- Max. -- 0.5 5 200 80 -- Unit V V A A mA A/Clock MHz A/Clock MHz/Data Input 11 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING RANGE (UNLESS OTHERWISE NOTED) (1) VDD = 1.8V 0.1V Symbol fMAX tPDM(2) tLH tHL tPLH tPDMSS(2,3) tRPHL dV/dt_r dV/dt_f dV/dt_(4) Parameter Max Input Clock Frequency CLK and CLK to Q LOW to HIGH Delay, CLK and CLK to PTYERR HIGH to LOW Delay, CLK and CLK to PTYERR LOW to HIGH Propagation Delay, RESET to PTYERR CLK and CLK to Q (simultaneous switching) RESET to Q Output slew rate from 20% to 80% Output slew rate from 20% to 80% Output slew rate from 20% to 80% Min 340 1.41 1.2 1 -- -- -- 1 1 -- Max. -- 2.15 3 3 3 2.25 3 4 4 1 Unit MHz ns ns ns ns ns ns V/ns V/ns V/ns NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. 2. Includes 350ps of test load transmission line delay. 3. This parameter is not production tested. 4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate). TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE VDD = 1.8V 0.1V Symbol fCLOCK tw tACT(1,2) tINACT(1,3) tSU tH Parameter Clock Frequency Pulse Duration, CLK, CLK HIGH or LOW Differential Inputs Active Time Differential Inputs Inactive Time DCS before CLK, CLK, CSR HIGH Setup Time Hold Time DCS before CLK, CLK, CSR LOW DODT, CSR, Data, and DCKE before CLK, CLK Data, DCS, CSR, DCKE, and DODT after CLK, CLK Min. -- 1 -- -- 0.5 0.3 0.3 0.3 Max. 340 -- 10 15 -- -- -- -- ns ns Unit MHz ns ns ns NOTES: 1. This parameter is not production tested. 2. Data and VREF inputs must be low a minimum time of tACT max, after RESET is taken HIGH. 3. Data, VREF, and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESET is taken LOW. 12 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD DUT TL = 50 CLK Inputs CLK CLK Test Point RL = 100 Test Point LVCMOS RESET Input tINACT IDD (2) RL = 1K TL = 350ps, 50 Test Point CL = 30 pF (1) Out RL = 1K Load Circuit VDD VDD/2 VDD/2 0V tACT 90% CLK CLK tPLH Output VTT VICR VICR tPHL VOH VTT VOL VID 10% Voltage and Current Waveforms Inputs Active and Inactive Times tW Input VICR VICR VID Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Pulse Duration LVCMOS RESET Input VIH VDD/2 VIL tRPHL VOH Output CLK VICR CLK tSU Input VREF tH VIH VREF VIL VID VTT VOL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times NOTES: 1. CL includes probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDD/2 6. VIH = VREF + 250mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600mV. 9. tPLH and tPHL are the same as tPDM. 13 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD DUT Out RL = 50 Test Point CL = 10 pF (1) Load Circuit: High-to-Low Slew-Rate Output 80% VOH 20% dv_f dt_f VOL Voltage Waveforms: High-to-Low Slew-Rate DUT Out CL = 10 pF (1) Test Point RL = 50 Load Circuit: Low-to-High Slew-Rate dt_r dv_r 80% VOH 20% Output VOL Voltage Waveforms: Low-to-High Slew-Rate NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 14 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS (VDD = 1.8V 0.1V) VDD DUT Out RL = 1K Test Point CL = 10 pF (1) Load Circuit: PTYERR Output VDD RESET tPLH VOH Output Waveform 2 0.15V 0V VDD/2 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time CLK CLK VICR tHL VICR VI(PP) Output Waveform 1 VDD VDD/2 VOL Voltage Waveforms: Open Drain Output High-to-Low Transition Time CLK CLK VICR tHL VICR VI(PP) VOH Output Waveform 2 0.15V 0V Voltage Waveforms: Open Drain Output Low-to-High Transition Time (with Respect to Clock Inputs) NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified). 15 IDT74SSTU32D869 14-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT XX XXX XX SSTU32 Temp. Range Device Type Package BKG Thin Profile Fine Pitch, Ball Grid Array, Green D869 14-Bit 1:2 Registered Buffer with Parity 74 0C to +70C CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 16 |
Price & Availability of IDT74SSTU32D869
 |
|||||||||||
|
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |
