 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| EUA6205 1.25-W Mono Fully Differential Audio Power Amplifier with 1.8V Input Logic Thresholds DESCRIPTION The EUA6205 is a mono fully-differential audio amplifier, capable of delivering 1.25W of continuous average power to an 8 BTL load with less than 1% THD+N from a 5V power supply, and 630mW to an 8 load from a 3.6V power supply. The Shutdown pin is FEATURES Supply Voltage 2.5V to 5.5V 1.25W into 8 from a 5-V Supply at THD=1% (typ) Shutdown Pin has 1.8V Compatible Thresholds Low Supply Current: 3.4mA Typical Shutdown Current < 10A Only Five External Components - Improved PSRR (87dB) for Direct Battery Operation - Full Differential Design Reduces RF Rectification - Improved CMRR Eliminates Two Input Coupling Capacitors Available in 3mm*3mm TDFN-8 and Thermally Enhanced MSOP-8 Packages RoHS Compliant and 100% Lead (Pb)-Free fully compatible with 1.8V logic GPIO, such as are used on low power cellular chipsets. Features like 85-dB PSRR from 90 Hz to 5 kHz, improved RF-rectification immunity, and small PCB area makes the EUA6205 ideal for wireless handsets. APPLICATIONS Wireless Handsets, PDAs, and other mobile devices Typical Application Circuit DS6205 Ver 1.0 Mar. 2007 1 Pin Configurations Package Type Pin Configurations EUA6205 TDFN-8 MSOP-8 (FD) Pin Description PIN PIN DESCRIPTION Shutdown Bypass IN+ INVO+ VDD GND VO- 1 2 3 4 5 6 7 8 Shutdown terminal (active low logic) Mid-supply voltage. Adding a bypass capacitor improves PSRR Positive differential input Negative differential input Positive BTL output Supply voltage terminal High-current ground Negative BTL output DS6205 Ver 1.0 Mar. 2007 2 EUA6205 Ordering Information Order Number EUA6205JIR1 EUA6205MIR1 Package Type TDFN-8 MSOP-8 Marking xxxx 6205 xxxx 6205 Operating Temperature range -40C to 85C -40C to 85C EUA6205 1/4 1/4 1/4 1/4 Lead Free Code 1: Lead Free 0: Original Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: TDFN M: MSOP DS6205 Ver 1.0 Mar. 2007 3 Absolute Maximum Ratings u EUA6205 -0.3 V to 6V -0.3 V to VDD + 0.3V -65C to 85C Supply Voltage, VDD u ---------------------------------------------------------------------------------------- Input Voltage, VI u u ---------------------------------------------------------------------------- Storage Temperature rang, Tstg ------------------------------------------------------------------ESD Susceptibility u -------------------------------------------------------------------------------------------- 2kV -------------------------------------------------------------------------------------- -40C to 125C 56C/W 50C/W Junction Temperature u Thermal Resistance JA (MSOP-FD) JA (TDFN) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Recommended Operating Conditions MIN NOM MAX UNIT Supply Voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Common-mode input voltage, VIC Operating free-air temperature, TA 2.5 1.15 0.5 -40 5.5 0.5 VDD-0.8 85 V V V V C Electrical Characteristics, TA=25C Gain=1V/V Symbol |VOO| Parameter Output offset voltage (measured differentially) Conditions VI = 0V, VDD = 2.5V to 5.5V VDD = 2.5V to 5.5V VDD = 5.5V, VIC = 0.5V to VDD-0.8 VDD = 3.6V, VIC = 0.5V to VDD-0.8 VDD = 2.5V, VIC = 0.5V to VDD-0.8 VDD=5.5V RL = 8, VIN+ = VDD, VIN- = 0V or VIN+ = 0V, VDD=3.6V VIN- = VDD VDD=2.5V VDD=5.5V VIN+ = VDD, RL = 8, VIN- = 0V or VIN+ = 0V, VDD=3.6V VIN- = VDD VDD=2.5V VDD = 5.5V, VI = 5.8V VDD = 5.5V, VI = -0.3V VDD = 2.5V to 5.5V, no load, Shutdown = VIH Shutdown = VIL, VDD = 2.5V to 5.5V, No load Min EUA6205 Unit Typ Max. 9 -84 -79 -79 -66 0.29 0.21 0.17 5.1 3.3 2.25 -67 -57 -60 0.46 V 0.26 V 1.2 1.2 3.4 0.02 A A mA A mV dB dB PSRR Power supply rejection ratio CMRR Common range mode rejection VOL Low-level output voltage 4.8 2.1 VOH |IIH| |IIL| IDD IDD (SD) High-level output voltage High-level input current Low-level input current Supply current Supply current in shutdown mode DS6205 Ver 1.0 Mar. 2007 4 Operating Characteristics, TA=25C, Gain=1V/V, RL = 8 Symbol PO EUA6205 EUA6205 Unit Min Typ Max. VDD = 5.5V VDD = 3.6V VDD = 2.5V 1.25 0.63 0.3 0.067 0.065 0.077 -87.1 -86.5 -64 108 dB dB % W Parameter Output power Conditions THD + N = 1%, f = 1kHz VDD = 5V, PO = 1W, f = 1kHz VDD = 3.6V, PO = 0.5W, f = 1kHz VDD = 2.5V, PO = 200mW, f = 1kHz C(BYPASS) = 0.47F, VDD = 5.5V f = 217 Hz to 2 kHz CI = 2F C(BYPASS) = 0.47F, VDD = 3.6V f = 217 Hz to 2 kHz CI = 2F C(BYPASS) = 0.47F, VDD = 2.5V f = 217 Hz to 2 kHz CI = 2F VDD = 5V, PO = 1W No weighting f = 20 Hz to 20 kHz A weighting VDD = 5.5V,Gain = 4V/V, VICM = 200mVpp f = 20 Hz to 1 kHz f = 20 Hz to 1 kHz f = 20 Hz to 1 kHz Total harmonic THD+N distortion plus noise KSVR Supply ripple rejection ratio SNR Signal-to-noise ratio Output voltage noise 10 8 -71.6 -71.9 -60 2 M dB VRMS Vn CMRR Common mode rejection ratio VDD = 3.6V,Gain = 4V/V, VICM = 200mVpp VDD = 2.5V,Gain = 4V/V, VICM = 200mVpp ZI ZO Input impedance Output impedance Shutdown attenuation Shutdown mode f = 20 Hz to 20 kHz, RF = RI = 20 k >10k -79 dB DS6205 Ver 1.0 Mar. 2007 5 Typical Operating Characteristics EUA6205 OUTPUT POWER VS LOAD RESISTANCE 1.4 OUTPUT POWER VS SUPPLY VOLTAGE 1.8 RL=8 ohm 1.6 f=1 KHz Gain=1V/V 1.4 1.2 f=1 KHz THD+N=1% Gain=1V/V po-Output Power - W 1.2 1.0 0.8 THD+N=10% PO - Output Power - W 1.0 0.8 VDD=5V 0.6 THD+N=1% 0.6 0.4 0.2 VDD=3.6V 0.4 VDD=2.5V 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 8 12 16 20 24 28 32 VDD - Supply Voltage - V RL - Load Resistance - ohm Figure 1. Figure 2. OUTPUT POWR VS LOAD RESISTANCE 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 8 12 16 20 24 28 32 0.40 POWER DISSIPATION VS OUTPUT POWER VDD=3.6V 0.35 0.30 f=1KHz THD+N=10% Gain=1 V/V PD - Power Dissipation PO - Output Power - W RL= 8 ohm 0.25 0.20 VDD = 5V RL=16 ohm 0.15 0.10 0.05 0.00 0.0 VDD= 3.6V VDD= 2.5V 0.2 0.4 0.6 0.8 RL - Load Resistance - ohm Po - Output Power - W Figure 3. Figure 4. POWER DISSIPATION VS OUTPUT POWER 0.7 VDD=5V 0.6 RL= 8 ohm PD - Power Dissipation -W 0.5 0.4 0.3 0.2 RL= 16 ohm 0.1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Po - Output Power -W Figure 6. Figure 5. DS6205 Ver 1.0 Mar. 2007 6 EUA6205 Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. DS6205 Ver 1.0 Mar. 2007 7 EUA6205 Figure 13. Figure 14. SUPPLY VOLTAGE REJECTION RATIO VS COMMON MODE INPUT VOLTAGE -10 kSVR - Supply Voltage Rejection Ratio -dB f=217 Hz C(Bypass)=0.47uF RL= 8 ohm -30 Gain=1 V/V -20 -40 VDD=2.5V -50 VDD=3.6V -60 -70 VDD= 5V -80 -90 0 1 2 3 4 5 VIC - Common Mode Input Voltage - V Figure 15. Figure 16. Figure 17. Figure 18. DS6205 Ver 1.0 Mar. 2007 8 EUA6205 COMMON MODE REJECTION RATIO VS COMMON MODE INPUT VOLTAGE 0 CMRR - Common Mode Rejection Ratio - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 RL= 8 ohm Gain=1 V/V VDD=2.5V VDD=3.6V VDD=5V 1 2 3 4 5 VIC - Common Mode Input Voltage - V Figure 19. Figure 20. SUPPLY CURRENT VS SUPPLY VOLTAGE 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.0 IDD - Supply Current - mA 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD - Supply Voltage - V Figure 21. Figure 22. DS6205 Ver 1.0 Mar. 2007 9 EUA6205 Application Information Application Schematics Figure23 through Figure26 show application schematics for differential and single-ended inputs. Typical values are shown in Table1. Table1. Typical Component Value Component RI RF C(BYPASS) CS CI Value 10k 10k 0.22F 1F 0.22F Figure 25. Application Schematic With Summing Two Differential Inputs Figure 23. Differential Input Application Schematic Optimized With Input Capacitors Figure 26. Application Schematic With Summing Two Single-Ended Inputs Power Dissipation Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. Since the EUA6205 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. The maximum power dissipation for a given application can be derived from the power dissipation graphs of from equation1. PDMAX = 4 * (VDD ) 2 /(2 2 R L ) --------------------(1) It is critical that the maximum junction temperature TJMAX of 150C is not exceeded. TJMAX can be determine from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the Figure 24. Single-Ended Input Application Schematic DS6205 Ver 1.0 Mar. 2007 10 EUA6205 thermal resistance of the application can be reduced, resulting in higher PDMAX. Additional copper foil can be added to any of the leads connected to the EUA6205. If TJMAX still exceeds 150C, then additional changes must be made. These changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal power dissipation is a function of output power. Selection Components Resistors (RF and RI) The input (RI) and feedback resistors (RF) set the gain of the amplifier according to Equation 2. The value of CI is important to consider as it directly affects the bass (low frequency) performance of the circuit. Consider the example where RI is 10k and the specification calls for a flat bass response down to 100 Hz. Equation 2 is reconfigured as Equation 4. 1 C= I 2 R f IC Gain = R F /R I ----------------------------------------(2) RF and RI should range from 1k to 100k. Most graphs were taken with RF=RI=20 k. Resistor matching is very important in fully differential amplifiers. The balance of the output on the reference voltage depends on matched rations of resistors. CMRR, PSRR, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. Bypass Capacitor (CBYPASS) and Start-Up Time -------------------------------- (4) In this example, CI is 0.16F, so one would likely choose a value in the range of 0.22F to 0.47F. A further consideration for this capacitor is the leakage path from the input source through the input network (RI, CI) and the feedback resistor (RF) to the load. This leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at VDD/2, which is likely higher than the source dc level. It is important to confirm the capacitor polarity in the application. Decoupling Capacitor (CS) The EUA6205 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1F to 1 F, placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a 10-F or greater capacitor placed near the audio power amplifier also helps, but is not required in most applications because of the high PSRR of this device. The internal voltage divider at the BYPASS pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to VDD/2. Adding a capacitor to this pin filters any noise into this pin and increases the kSVR. C(BYPASS)also determines the rise time of VO+ and VO- when the device is taken out of shutdown. The larger the capacitor, the slower the rise time. Although the output rise time depends on the bypass capacitor value, the device passes audio 4 s after taken out of shutdown and the gain is slowly ramped up based on C(BYPASS). To minimize pops and clicks, design the circuit so the impedance (resistance and capacitance) detected by both inputs, IN+ and IN-, is equal. Input Capacitor (CI) The EUA6205 does not require input coupling capacitors if using a differential input source that is biased from 0.5 V to VDD - 0.8 V. Use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. In the single-ended input application an input capacitor, CI, is required to allow the amplifier to bias the input signal to the proper dc level. In this case, CI and RI form a high-pass filter with the corner frequency determined in Equation 3. f C = 1 2 R C II --------------------------------- (3) DS6205 Ver 1.0 Mar. 2007 11 EUA6205 Package Information TDFN-8 DETAIL A SYMBOLS A A1 b D D1 E E1 e L MILLIMETERS MIN. MAX. 0.70 0.80 0.00 0.05 0.20 0.40 2.90 3.10 2.30 2.90 3.10 1.50 0.65 0.25 0.45 INCHES MIN. 0.028 0.000 0.008 0.114 0.090 0.114 0.059 0.026 0.010 0.018 0.122 MAX. 0.031 0.002 0.016 0.122 DS6205 Ver 1.0 Mar. 2007 12 EUA6205 Package Information (continued) MSOP-8 (FD) DETAILA A SYMBOLS A A1 D E E1 D1 E2 L b e MILLIMETERS MIN. MAX. 1.10 0.00 0.15 3.00 4.70 5.10 3.00 1.70 1.70 0.40 0.80 0.22 0.38 0.65 INCHES MIN. 0.000 0.118 0.185 0.118 0.067 0.067 0.016 0.008 0.026 0.031 0.015 0.201 MAX. 0.043 0.006 DS6205 Ver 1.0 Mar. 2007 13 |
Price & Availability of EUA6205MIR1
 |
|
|
|
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |