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Freescale Semiconductor, Inc.
Semiconductor Products Sector Engineering Bulletin
Order this document by EB381/D
EB381
Migrating from the MC68HC811E2 to the MC68HC11F1
Freescale Semiconductor, Inc...
By Timothy J. Airaudi Applications Engineering Motorola Embedded Control Division Austin, Texas
Introduction
This engineering bulletin explains how existing users of the MC68HC811E2 could migrate to the MC68HC11F1. The last date that the MC68HC811E2 can be ordered from Motorola is June 30, 2001. However, beyond that date, parts may be available from Motorola distributors. The MC68HC811E2 is a versatile part used in many different types of applications. This document addresses applications that use the part in expanded mode only. Customers using single-chip mode should see Migrating from the MC68HC811E2 to the MC68HC711E9, Motorola document order number EB380/D.
(c) Motorola, Inc., 2001
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Freescale Semiconductor, Inc. Engineering Bulletin Migrating to the MC68HC11F1
For current MC68HC811E2 users with external memory systems (expanded mode operation), the MC68HC11F1 is a possible replacement part (see Table 1). The MC68HC11F1 can address 64 Kbytes of external memory in expanded mode and requires less glue logic than the MC68HC811E2. Other advantages of migrating to the MC68HC11F1 are:
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* * * * *
More RAM More expanded mode input/output (I/O) Non-multiplexed address/data bus 3-volt operation Ability to run at higher speeds
For complete information on the MC68HC811E2, see the M68HC11E Family Technical Data, Motorola document order number M68HC11E/D. For information on the MC68HC11F1, see the MC68HC11F1 Technical Data, Motorola document order number MC68H11CF1/D. Both can be found at http://motorola.com/semiconductor (the Motorola World Wide Web site).
Major Differences
The major differences between these two parts are: * * * * * Package options Memory map (memory, registers, etc.) EEPROM block protect CONFIG register External glue logic requirements
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Engineering Bulletin Migrating to the MC68HC11F1
Table 1. Comparison Chart
Device RAM (Bytes) EE (Bytes) Timer Input/Output (i/O) Expanded MC68HC811E2 256 2048 16-bit, 3-4 IC, 4-5 OC, RTI, pulse accumulator 22 SCI SPI 8-CH, 8-bit 5.0 2 C, V, M 52 PLCC (FN); 48 DIP (P) MC68HC811F1 1K 512 16-bit, 3-4 IC, 4-5 OC, RTI, pulse accumulator 30 SCI SPI 8-CH, 8-bit 3.0 5.0 3 5 C, V, M 68 PLCC (FN); 80 LQFP (FU) 64-K external address bus, 4-program chip select, non-mux address/data bus, 3-V, 3-MHz version (MC68L11F1) MC68HC811F1/D
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Serial Analog-to-Digital (A/D) Operating Voltage (V) Maximum Bus Frequency (MHz) Temperature Package Options
Comments
Secure device available, MC68SEC811E2; EEPROM block protect
Document Order Number
MC68HC11E/D
Difference: Package Options
The MC68HC811E2 is available in 52-pin PLCC (plastic leaded chip carrier) and 48-pin DIP (dual in-line pack) packages. The MC68HC11F1 is available in 68-pin PLCC and 80-pin LQFP (low-profile quad flat pack) packages. Case 1 Example: Issue: 52-pin PLCC Only 68-pin PLCC or 80-pin LQFP available
Change required: Re-layout application to allow use of the 68-pin PLCC or the 80-pin LQFP. See Figure 1 and Figure 2.
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Case 2 Example: Issue: 48-pin DIP Only 68-pin PLCC or 80-pin LQFP available
Change required: Re-layout application to allow use of the 68-pin PLCC or the 80-pin LQFP. See Figure 1 and Figure 2.
MODB/VSTBY
PC0/DATA0
MODA/LIR
PE7/AN7
PE3/AN3
PE6/AN6
PE2/AN2 63
PE5/AN5 62
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68
67
66
65
64
1
61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
9
8
7
6
5
4
3
2
PE1/AN1
4XOUT
EXTAL
XTAL
R/W
VRH
VSS
VRL
E
PC1/DATA1 PC2/DATA2 PC3/DATA3 PC4/DATA4 PC5/DATA5 PC6/DATA6 PC7/DATA7 RESET XIRQ IRQ PG7/CSPROG PG6/CSGEN PG5/CSIO1 PG4/CSIO2 PG3 PG2 PG1
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PE4/AN4 PE0/AN0 PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14
PA3/OC5/IC4/OC1
PA4/OC4/OC1
Figure 1. Pin Assignments for MC68HC11F1 68-Pin PLCC
PA6/OC2/OC1 PA5/OC3/OC1
PA7/PAI/OC1
PB7/ADDR15
PA2/IC1
PA1/IC2
PD2/MISO
PD3/MOSI
PD4/SCK
PD0/RxD
PD1/TxD
PA0/IC3
PGO
PD5/SS
VDD
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Engineering Bulletin Migrating to the MC68HC11F1
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PB7/ADDR15
PD2/MISO
PD3/MOSI
PD4/SCK
PD0/RxD
PD1/TxD
PA0/IC3
PA1/IC2
PA2/IC1
PD5/SS
PG0 62
VDD
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
NC NC PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2 PF1/ADDR1 PF0/ADDR0 PE0/AN0 PE4/AN4 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
NC
NC PG1 PG2 PG3 PG4/CSIO1 PG5/CSI02 PG6/CSGEN PG7/CSPROG IRQ XIRQ RESET PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 NC NC
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PE1/AN1
PE5/AN5
PE2/AN2
PE6/AN6
PE3/AN3
PE7/AN7
EXTAL
4XOUT
MODB/VSTBY
Figure 2. Pin Assignments for MC68HC11F1 80-Pin QFP Difference: Memory Map (Memory, Registers, etc.) The MC68HC811E2 has the same memory mapped locations for the normal mode interrupt vectors. The RAM, EEPROM, external addressing, and registers for these devices are different. See Figure 3 and Figure 4.
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PC0/DATA0
NC
NC
R/W
VSS
MODA/LIR
XTAL
VRH
VRL
NC
E
Freescale Semiconductor, Inc. Engineering Bulletin
Case 1 Example: Issue: RAM None
Change required: None. However, you may want to take advantage of the extra 768 bytes of RAM. This block of RAM is also relocatable on 4-K boundaries in the 64-Kbyte address space by writing an appropriate value into bits 4-7 in the INIT register.
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Case 2 Example: Issue: EPROM The MC68HC11F1 has less EEPROM (512 bytes vs. 2048 bytes), and it is located at a different starting address ($FE00 vs. $F800).
Change required: Change code to use new EEPROM block located from $FE00 to $FFDF. Case 3 Example: Issue: External address range External address range is different.
Change required: Change the external address range from $1040-$F7FF to $1060-$FDFF. Case 4 Example: Issue: Register block Register block is a different size and some register addresses have different meanings.
Change required: The register block on the MC68HC11F1 is 96 bytes instead of 64-bytes and is located at a default location of $1000-$105F. This block of RAM is also re-locatable on 4-K boundaries in the 64-Kbyte address space by writing to bits 0-3 in the INIT register. These register addresses also have different meanings: $1001, $1002, $1003, $1005, $1006, $1036, $1038, and $103E. $105C-$105F are additional registers.
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Engineering Bulletin Migrating to the MC68HC11F1
$0000 EXT $1000 EXT
0000 256 BYTES RAM 00FF 1000 103F 64-BYTE REGISTER BLOCK
EXT
EXT BF00 BOOT ROM BFFF BFC0 SPECIAL MODES INTERRUPT BFFF VECTORS
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2048 BYTES EEPROM $F800 F800 FFC0 FFFF NORMAL MODES INTERRUPT VECTORS
$FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST
FFFF
Figure 3. Memory Map for MC68HC811E2
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$0000
x000 1024 BYTES RAM(1) EXTERNAL EXTERNAL
$1000
x3FF y000 96-BYTE REGISTER BLOCK(2) yo5F
EXTERNAL
EXTERNAL
BF00 256 BYTES BOOTSTRAP ROM BFC0 SPECIAL MODE(3) INTERRUPT VECTORS
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BFFF zD00 zDFF zE00 $FE00 EXT $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST zFFF FFFF
256 BYTES RESERVED(4) SPECIAL TEST MODE ONLY 512 BYTES EEPROM(5) FFC0 NORMAL MODE INTERRUPT VECTORS
Notes: 1. RAM can be remapped to any 4-byte boundary ($x000). "x" represents the value contained in RAM [3:0] in the INIT register. 2. The register block can be remapped to any 4-byte boundary ($y000). "y" represents the value contained in REG[3:0] in the INIT register. 3. Special test mode vectors are externally addressed. 4. In special test mode the address locations $zD00-$zDFF are not externally addressable. "z" represents the value of bits EE[3:0] in the CONFIG register. 5. EEPROM can be remapped to any 4-byte boundary ($z000). "z" represents the value contained in EE[3:0] in the CONFIG register.
Figure 4. MC68HC11F1 Memory Map Difference: EEPROM Block Protect Since these two parts differ significantly regarding EEPROM size and location, the address range and block size that can be protected is different. See Figure 5, Table 2, and Table 3. Case 1 Example: Issue: EEPROM block protect EEPROM block protect addresses and sizes are different.
Change required: The BPRT bits in the BPROT register ($1035) must be changed to protect the address ranges and block sizes the user desires.
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Engineering Bulletin Migrating to the MC68HC11F1
Address:
$1035 Bit 7 6 5 4 PTCON 3 BPRT3 1 2 BPRT2 1 1 BPRT1 1 Bit 0 BPRT0 1
Read: Write: Reset: 0 0 0 1
= Unimplemented
Figure 5. Block Protect Register (BPROT)
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Table 2. EEPROM Block Protect in MC68HC811E2 MCUs
Bit Name BPRT0 BPRT1 BPRT2 BPRT3 Block Protected $xB00-$x9FF $xA00-$xBFF $xC00-$xDFF $xE00-$xFFF Block Size 512 bytes 512 bytes 512 bytes 512 bytes
Table 3. EEPROM Block Protection in MC68HC11F1 MCUs
Bit Name BPRT0 BPRT1 BPRT2 BPRT3 Block Protected $xE00-$xE1F $xE20-$xE5F $xE60-$xEDF $xEE0-$xFFF Block Size 32 bytes 64 bytes 128 bytes 288 bytes
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Difference: CONFIG Register The operation of the CONFIG register on the MC68HC811E2 differs from the MC68HC11F1. See Figure 6, Figure 7, Table 4, and Table 5. Case 1 Example: Issue: CONFIG register Some of the bits in the CONFIG register have different meaning.
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Change required: The bits in the CONFIG register ($103F) must be changed to meet the user's requirements. Bit 3 (NOSEC) is not used and bits 4-7 (EEPROM mapping) define different address ranges.
Address: $103F Bit 7 Read: Write: Single-chip reset: Bootstrap: Expanded: Test: 1 U U EE3 1 6 EE2 1 1 U U 5 EE1 1 1 U U 4 EE0 1 1 U U 3 NOSEC U U 1 1 2 NOCOP U U(L) U U(L) 1 1 1 1 1 Bit 0 EEON 1 1 U 0
= Unimplemented U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register.
Figure 6. MC68HC811E2 System Configuration Register (CONFIG)
Table 4. MC68HC811E2 EEPROM Mapping
EE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 EEPROM Location $0800-$0FFF $1800-$1FFF $2800-$2FFF $3800-$3FFF $4800-$4FFF $5800-$5FFF $6800-$6FFF $7800-$7FFF EE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 EEPROM Location $8800-$8FFF $9800-$9FFF $A800-$AFFF $B800-$BFFF $C800-$CFFF $D800-$DFFF $E800-$EFFF $F800-$FFFF
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Engineering Bulletin Migrating to the MC68HC11F1
Address:
$103F Bit 7 6 EE2 5 EE1 4 EE0 3 2 NOCOP 1 Bit 0 EEON
Read: Write: Reset states: Single chip Expanded Bootstrap Special test
EE3
1 1 P P
1 1 P P
1 1 P P
1 1 P P
1 1 1 1
P P(L) P P(L)
1 1 1 1
1 1 P 0
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= Unimplemented P= Previously programmed bit P(L) = P(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by DISR bit in TEST1 register.
Figure 7. M68HC11F1 System Configuration Register (CONFIG) Table 5. EEPROM Mapping
EE[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 EEPROM Position $0E00-$0FFF $1E00-$1FFF $2E00-$2FFF $3E00-$3FFF $4E00-$4FFF $5E00-$5FFF $6E00-$6FFF $7E00-$7FFF EE[3:0] 1000 1001 1010 1011 1100 1101 1110 1111 EEPROM Position $8E00-$8FFF $9E00-$9FFF $AE00-$AFFF $BE00-$BFFF $CE00-$CFFF $DE00-$DFFF $EE00-$EFFF $FE00-$FFFF
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Difference: External Glue Logic Requirements Case 1 Example: Issue: External glue logic Some of the external glue logic requirements are different.
Change required: The MC68HC11F1 has a non-multiplexed address/data bus and four programmable chip selects. This will eliminate the need for such external devices as a demultiplexer, a decoder, and a latch. See Figure 8 and Figure 9.
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WE
OE
R/W
E
ADDRESS/DATA
AS 68HC811E9
LE
D LATCH
DATA OE EPROM ADDRESS OE CE
DATA RAM ADDRESS
WE
OE Q
CE
DECODE
HIGH ADDRESS
Figure 8. MC68HC811E2 Multiplexed Bus Example
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Engineering Bulletin Migrating to the MC68HC11F1
WE
OE
R/W
E DATA
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DATA OE 68HC11F1 CSGPROG EPROM CE ADDRESS OE
DATA WE RAM CE ADDRESS
CSGEN ADDRESS
Figure 9. MC68HC11F1 Non-Multiplexed Bus Example Memory Map Example This example is for connecting an 8- or 16-Kbyte external RAM and a 32-Kbyte external EPROM. See Figure 10. * * * Leave internal RAM at default location ($0000-$03FF). Leave register block at default location ($1000-$105F). Relocate internal EEPROM to address $2E00-$2FFF. This is done by programming the EE0-EE3 bits in the CONFIG register ($103F) to %0010. You may also need to program the EEON bit to ensure that the EEPROM is present in the memory map (see Figure 7). CSPROG comes up enabled in expanded mode. You will need to program the PSIZA and PSIZB bits in the CSCTL register ($105D) to set an address range. In this example, PSIZA = 0 and PSIZB = 1 ($8000-$FFFF). The user may also want to clear the PSTHA and PSTHB bits in the CSSTRH register ($105C) to ensure no clock stretch is used. Another option with CSPROG is the priority regarding CSGEN. This can be programmed using the GCSPR bit in the CSCTL register.
*
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Freescale Semiconductor, Inc. Engineering Bulletin
* For the CSGEN chip select, the G1SZA-G1SZC bits in the CSGSIZ register ($105F) must be programmed to %011 for an 8Kbyte RAM or to %010 for a 16-Kbyte RAM. - Next, the starting address for this address must be programmed. This is done by programming bits GA13 and GA15 for the 8-Kbyte RAM or bits GA14 and GA15 for the 16-Kbyte RAM. Like the CSPROG, clear the GSTHA and GSTHB bits to disable the clock stretch. - The user should also set the GNPOL bit (bit 4) in the CSGSIZ register to a 0 to make sure chip select CSGEN is an active low. Normally, the chip select for an external RAM device is made active with respect to the E clock going high. In this example, the CSGEN chip select needs to be made active during the address valid time. This is done by setting the GAVLD bit (bit 3) in the CSGSIZ register to a 1. - The user should also check the other options available in the CSGSIZ register.
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Engineering Bulletin Summary
$0000 1024 BYTES OF INTERNAL RAM $03FF NOT USED $1000 96-BYTE REGISTER BLOCK $105F NOT USED $2E00 RELOCATE EEPROM TO THIS ADDRESS LEAVE REGISTER BLOCK IN DEFAULT LOCATION LEAVE INTERNAL RAM IN DEFAULT LOCATION
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512 BYTES OF INTERNAL EEPROM $2FFF NOT USED $4000 8 OR 16 KBYTES OF EXTERNAL RAM $5FFF OR $7FFF NOT USED WHEN 8-KBYTE RAM IS USED $8000
USE CSGEN CHIP SELECT
USE CSPROG CHIP SELECT
32 KBYTES OF EXTERNAL EPROM $FFFF
Figure 10. MC68HC11F1 Expanded Mode Memory Map Example
Summary
For those users using the MC68HC811E2 with external memory systems, the MC68HC11F1 is one possible migration path. Customers may also want to look at migrating to the MC68HC711E9 (see Migrating from the MC68HC811E2 to the MC68HC711E9, Motorola document order number EB380/D), or to the MC68HC812A4.
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AGREEMENT
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu, Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
(c) Motorola, Inc., 2001
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