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| ISL9N7030BLP3, ISL9N7030BLS3ST Data Sheet January2002 30V, 0.009 Ohm, 75A, N-Channel Logic Level UltraFET(R) Trench Power MOSFETs This device employs a new advanced trench MOSFET technology and features low gate charge while maintaining low on-resistance. Optimized for switching applications, this device improves the overall efficiency of DC/DC converters and allows operation to higher switching frequencies. PWM Optimized Features * * * * * * Fast Switching rDS(ON) = 0.0064 (Typ), VGS = 10V rDS(ON) = 0.010 (Typ), VGS = 4.5V Qg Total 24nC (Typ), VGS = 5V Qgd (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11nC CISS (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2600pF Packaging ISL9N7030BLS3ST JEDEC TO-263AB DRAIN (FLANGE) ISL9N7030BLP3 JEDEC TO-220AB SOURCE DRAIN GATE Symbol D G GATE SOURCE DRAIN (FLANGE) S Ordering Information PART NUMBER ISL9N7030BLP3 ISL9N7030BLS3ST PACKAGE TO-220AB TO-263AB (Tape and Reel) BRAND 7030BL 7030BL Absolute Maximum Ratings SYMBOL VDSS VDGR VGS ID ID ID IDM PD TJ, TSTG TL Tpkg RJC RJA RJA NOTE: 1. TJ = 25oC to 150oC. TC = 25oC, Unless Otherwise Specified PARAMETER ISL9N7030BLP3, ISL9N7030BLS3ST 30 30 20 75 48 15 Figure 4 100 0.67 -55 to 175 300 260 1.5 62 43 UNITS V V V A A A A W W/oC oC oC oC oC/W oC/W oC/W Drain to Source Voltage (Note 1) Drain to Gate Voltage (RGS = 20k) (Note 1) Gate to Source Voltage Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) Continuous (TC = 25oC, VGS = 10V, RJA = 43oC/W) Pulsed Drain Current Power Dissipation Derate Above 25oC Operating and Storage Temperature Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s Package Body for 10s, See Techbrief TB334 Thermal Resistance Junction to Case, TO-220, TO-263 Thermal Resistance Junction to Ambient, TO-220, TO-263 Thermal Resistance Junction to Ambient, TO-263, 1in 2 copper pad area THERMAL SPECIFICATIONS CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive products. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST Electrical Specifications PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 10) VDS = 25V, VGS = 0V VDS = 25V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 9 ID = 75A, VGS = 10V (Figures 7, 8) ID = 48A, VGS = 4.5V (Figure 7) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID = 15A VGS = 4.5V, RGS = 6.2 (Figures 13, 17, 18) 15 67 35 32 122 100 ns ns ns ns ns ns 1 0.007 0.010 3 0.009 0.012 V IGSS VGS = 20V 30 1 250 100 V A A nA TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge at 10V Total Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 15V, VGS = 0V, f = 1MHz (Figure 11) 2600 520 225 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID = 48A, Ig(REF) = 1.0mA (Figures 12, 15, 16) 45 24 2.6 7 8 68 37 4.0 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 15V, ID = 15A, VGS = 10V, RGS = 6.2, (Figures 14, 17, 18) 8 40 64 31 71 142 ns ns ns ns ns ns Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 48A ISD = 20A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 48A, dISD/dt = 100A/s ISD = 48A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 26 14 UNITS V V ns nC (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST Typical Performance Curves 1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 80 ID, DRAIN CURRENT (A) 60 VGS = 10V 40 VGS = 4.5V 20 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 0.1 PDM SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 t1 t2 101 10-5 10-4 FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 1000 TC = 25oC IDM , PEAK CURRENT (A) FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 10V VGS = 5V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 50 10-5 FIGURE 4. PEAK CURRENT CAPABILITY (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST Typical Performance Curves 150 125 100 75 50 25 0 1 2 3 4 5 VGS , GATE TO SOURCE VOLTAGE (V) TJ = 25oC PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V (Continued) 150 TC = 25oC ID, DRAIN CURRENT (A) 125 100 75 VGS = 3.5V 50 25 0 0 0.5 1.0 1.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 3V 2.0 VGS = 4.5V VGS = 10V ID , DRAIN CURRENT (A) TJ = 175oC TJ = -55oC VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. TRANSFER CHARACTERISTICS FIGURE 6. SATURATION CHARACTERISTICS 25 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) ID = 50A 20 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 2.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 1.5 15 ID = 14A 10 ID = 75A 1.0 VGS = 10V, ID = 75A 0.5 -80 -40 0 40 80 120 160 200 5 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.0 1.2 ID = 250A 1.1 0.8 1.0 0.6 0.4 -80 -40 0 40 80 120 160 200 0.9 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST Typical Performance Curves 4000 CISS = CGS + CGD C, CAPACITANCE (pF) COSS CDS + CGD 1000 CRSS = CGD (Continued) 10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 48A ID = 14A 0 10 20 30 Qg, GATE CHARGE (nC) 40 50 2 VGS = 0V, f = 1MHz 100 0.1 1 10 30 0 VDS , DRAIN TO SOURCE VOLTAGE (V) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 12. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 250 VGS = 4.5V, VDD = 15V, ID = 15A SWITCHING TIME (ns) 200 SWITCHING TIME (ns) tr 150 350 VGS = 10V, VDD = 15V, ID = 15A 300 250 td(OFF) 200 150 100 tr 50 td(ON) td(OFF) tf td(ON) 100 tf 50 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE () FIGURE 13. SWITCHING TIME vs GATE RESISTANCE FIGURE 14. SWITCHING TIME vs GATE RESISTANCE Test Circuits and Waveforms VDS RL VDD VDS VGS = 10V VGS + Qg(TOT) Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V DUT Ig(REF) FIGURE 15. GATE CHARGE TEST CIRCUIT FIGURE 16. GATE CHARGE WAVEFORMS (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST Test Circuits and Waveforms VDS (Continued) tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS VDD DUT 0 10% 90% 10% RGS VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. SWITCHING TIME WAVEFORM Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. ( T JM - TA ) P DM = -----------------------------Z JA can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . Thermal resistances corresponding to other copper areas can be obtained from Figure 19 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads. R 19.84 JA = 26.51 + --------------------------------------( 0.262 + Area ) (EQ. 2) (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 19 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications 80 RJA = 26.51+ 19.84/(0.262+Area) RJA (oC/W) 3. The use of external heat sinks. 60 40 20 0.1 1 AREA, TOP COPPER AREA (in2) 10 FIGURE 19. THERMAL RESISTANCE vs MOUNTING PAD AREA (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST PSPICE Electrical Model .SUBCKT ISL9N7030BL 2 1 3 ; CA 12 8 1.5e-9 CB 15 14 1.75e-9 CIN 6 8 2.35e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD 10 rev Dec2000 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50 RSLC2 5 51 ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.58e-9 LSOURCE 3 7 1.47e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 2.5e-3 RGATE 9 20 3.4 RLDRAIN 2 5 10 RLGATE 1 9 45.8 RLSOURCE 3 7 14.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 2.55e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD - - VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*200),5))} .MODEL DBODYMOD D (IS = 1.9e-11 N=1.075 RS = 4.2e-3 TRS1 = 9e-4 TRS2 = 1e-6 XTI=2.2 CJO = 1.1e-9 TT = 8e-11 M = 0.49) .MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6) .MODEL DPLCAPMOD D (CJO = 8.2e-1 0IS = 1e-3 0N = 10 M = 0.45) .MODEL MMEDMOD NMOS (VTO = 1.9 KP = 3 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.4) .MODEL MSTROMOD NMOS (VTO = 2.35KP = 90 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.6 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 34 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7) .MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1e-5) .MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.7e-3 TC2 = -1e-5) .MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -0.8) VON = -0.8 VOFF= -4.0) VON = -0.3 VOFF= 0.2) VON = 0.2 VOFF= -0.3) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. (c)2002 Fairchild Semiconductor Corporation + - EBREAK 11 7 17 18 32.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 RDRAIN 21 16 - VBAT + 8 22 RVTHRES ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST SABER Electrical Model REV Dec 2000 template ISL9N7030BL n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 1.9e-11, nl=1.075 , rs = 4.2e-3, trs1 = 9e-4, trs2 = 1e-6, xti=2.2, cjo = 1.1e-9, tt = 8e-11, m = 0.49,) dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6) dp..model dplcapmod = (cjo = 8.2e-10, isl=10e-30, nl=10, m=0.45) m..model mmedmod = (type=_n, vto = 1.9, kp=3, is=1e-30, tox=1) m..model mstrongmod = (type=_n, vto = 2.35, kp = 90, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.6, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8) DPLCAP 5 sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) 10 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) c.ca n12 n8 = 1.5e-9 c.cb n15 n14 = 1.75e-9 c.cin n6 n8 = 2.35e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 4.58e-9 l.lsource n3 n7 = 1.47e-9 GATE 1 RLGATE CIN LGATE RSLC1 51 RSLC2 ISCL LDRAIN DRAIN 2 RLDRAIN ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18 MSTRO 8 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 res.rdrain n50 n16 = 2.5e-3, tc1 = 7e-3, tc2 = 1e-5 res.rgate n9 n20 = 3.4 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 45.8 res.rlsource n3 n7 = 14.7 res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 2.55e-3, tc1 = 1e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = -1e-6 res.rvthres n22 n8 = 1, tc1 = -2.7e-3, tc2 = -1e-5 spe.ebreak n11 n7 n17 n18 = 32.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/200))** 5)) } } S1A 12 S1B CA 13 + EGS 6 8 13 8 S2A 14 13 S2B RSOURCE LSOURCE 7 RLSOURCE SOURCE 3 15 RBREAK 17 18 RVTEMP CB + EDS 5 8 19 14 IT VBAT + - - 8 RVTHRES 22 (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B ISL9N7030BLP3, ISL9N7030BLS3ST SPICE Thermal Model REV 23 Sept 2000 ISL9N7030BL CTHERM1 th 6 2.0e-4 CTHERM2 6 5 3.0e-3 CTHERM3 5 4 3.4e-3 CTHERM4 4 3 4.0e-3 CTHERM5 3 2 1.0e-2 CTHERM6 2 tl 5.0e-2 RTHERM1 th 6 1.5e-3 RTHERM2 6 5 5.5e-3 RTHERM3 5 4 5.2e-2 RTHERM4 4 3 3.5e-1 RTHERM5 3 2 3.8e-1 RTHERM6 2 tl 4.1e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model ISL9N7030BL template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.0e-4 ctherm.ctherm2 6 5 = 3.0e-3 ctherm.ctherm3 5 4 = 3.4e-3 ctherm.ctherm4 4 3 = 4.0e-3 ctherm.ctherm5 3 2 = 1.0e-2 ctherm.ctherm6 2 tl = 5.0e-2 rtherm.rtherm1 th 6 = 1.5e-3 rtherm.rtherm2 6 5 = 5.5e-3 rtherm.rtherm3 5 4 = 5.2e-2 rtherm.rtherm4 4 3 = 3.5e-1 rtherm.rtherm5 3 2 = 3.8e-1 rtherm.rtherm6 2 tl = 4.1e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE (c)2002 Fairchild Semiconductor Corporation ISL9N7030BLP3, ISL9N7030BLS3ST Rev. B TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM DISCLAIMER FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R) SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R) VCXTM STAR*POWER is used under license FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Preliminary First Production No Identification Needed Full Production Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4 |
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