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| Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Contents 1.0 2.0 3.0 Other Related Documents............................................................................................. 11 Pin Assignments and Signal Descriptions .................................................................. 12 Functional Description .................................................................................................. 31 3.1 3.2 Introduction.......................................................................................................... 31 Port Configuration ............................................................................................... 32 3.2.1 Auto-Negotiation..................................................................................... 32 3.2.2 Forced Operation ................................................................................... 33 3.2.3 Changing Port Speed - Forced............................................................... 33 3.2.4 Link Establishment and Port Connection ............................................... 33 3.2.5 MII Port Configuration ............................................................................ 33 Interface Descriptions.......................................................................................... 33 3.3.1 Twisted-Pair Interface ............................................................................ 33 3.3.2 Media Independent Interface.................................................................. 34 3.3.3 Serial Management Interface ................................................................. 34 3.3.4 Serial PROM Interface ........................................................................... 35 Repeater Operation............................................................................................. 35 3.4.1 100 Mbps Repeater Operation ............................................................... 35 3.4.2 10 Mbps Repeater Operation ................................................................. 36 Management Support.......................................................................................... 37 3.5.1 Configuration and Status........................................................................ 37 3.5.2 SNMP and RMON Support .................................................................... 37 3.5.3 Source Address Management................................................................ 37 Requirements ...................................................................................................... 37 3.6.1 Power ..................................................................................................... 37 3.6.2 Clock ...................................................................................................... 38 3.6.3 Bias Resistor .......................................................................................... 38 3.6.4 Reset ...................................................................................................... 38 3.6.5 PROM..................................................................................................... 38 3.6.6 Chip ID ................................................................................................... 38 3.6.7 Management Master I/O Link ................................................................. 38 3.6.8 IRB Bus Pull-ups .................................................................................... 38 LED Operation..................................................................................................... 39 3.7.1 LEDs at Start-up..................................................................................... 39 3.7.2 LED Event Stretching ............................................................................. 39 3.7.3 LED Blink Rates ..................................................................................... 39 3.7.4 Serial LED Interface ............................................................................... 40 3.7.4.1 Serial Shifting ............................................................................ 40 3.7.4.2 Serial LED Signals .................................................................... 40 3.7.4.3 Activity Graph LEDs .................................................................. 41 3.7.5 Direct Drive LEDs................................................................................... 42 3.7.6 LED Modes............................................................................................. 42 3.7.6.1 LED Mode 1 .............................................................................. 44 3.7.6.2 LED Mode 2 .............................................................................. 45 3.7.6.3 LED Mode 3 .............................................................................. 46 3.7.6.4 LED Mode 4 .............................................................................. 47 3.3 3.4 3.5 3.6 3.7 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 3 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.8 3.9 3.10 3.11 3.12 4.0 IRB Operation ..................................................................................................... 47 3.8.1 IRB Signal Types ................................................................................... 48 3.8.2 IRB Isolation ........................................................................................... 48 3.8.3 10 Mbps-Only Operation ........................................................................ 48 3.8.3.1 MAC IRB Access....................................................................... 48 3.8.3.2 Management Master Chain Arbitration...................................... 48 3.8.4 LXT98x/91x/98x0 Compatibility.............................................................. 48 MII Port Operation............................................................................................... 51 3.9.1 Preamble Handling................................................................................. 51 Serial Management I/F ........................................................................................ 52 3.10.1 SMI Signals ............................................................................................ 52 3.10.1.1Serial Clock ............................................................................... 53 3.10.1.2Serial Data I/O........................................................................... 53 3.10.2 Read and Write Operations.................................................................... 53 3.10.2.1SMI Collision Handling .............................................................. 53 3.10.2.2SMI Address Match Indication .................................................. 53 3.10.2.3SMI Frame Format .................................................................... 54 3.10.3 Address Assignment Methods ............................................................... 57 3.10.3.1Chain Arbitration Mechanism .................................................... 58 3.10.3.2PROM Arbitration Mechanism................................................... 58 3.10.3.3Address Re-Arbitration .............................................................. 59 3.10.4 Interrupt Functions ................................................................................. 59 Serial PROM Interface ........................................................................................ 59 Serial Configuration Interface.............................................................................. 60 Application Information ................................................................................................. 61 4.1 4.2 4.3 General Design Guidelines ................................................................................. 61 Typical Applications ............................................................................................ 62 Application Circuitry ............................................................................................ 63 4.3.1 Power and Ground ................................................................................. 63 4.3.1.1 Supply Filtering.......................................................................... 63 4.3.1.2 Ground Noise ............................................................................ 63 4.3.1.3 Power and Ground Plane Layout Considerations ..................... 63 4.3.1.4 Chassis Ground......................................................................... 64 4.3.1.5 The RBIAS Pin .......................................................................... 64 4.3.2 MII Terminations .................................................................................... 65 4.3.3 Twisted-Pair Interface ............................................................................ 65 4.3.3.1 Magnetics Information ............................................................... 66 4.3.4 Clock ...................................................................................................... 66 4.3.5 SMI and PROM Circuits ......................................................................... 68 4.3.6 LED Circuits ........................................................................................... 69 4.3.6.1 Direct Drive LEDs...................................................................... 69 4.3.6.2 LED Pins Multiplexed with Configuration Inputs........................ 69 4.3.6.3 Serial LEDs ............................................................................... 70 Inter-Repeater Backplane Compatibility.............................................................. 71 4.4.1 Local Backplane--3.3V Only ................................................................. 72 4.4.2 Stack Backplane--3.3V or 5V ................................................................ 72 4.4.2.1 3.3V and 5.0V Stacking Boards Cannot Be Mixed.................... 72 4.4 4 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 5.0 6.0 Test Specifications......................................................................................................... 75 Register Definitions ....................................................................................................... 87 6.1 6.2 Register Map ....................................................................................................... 87 Counter Registers ............................................................................................... 95 6.2.1 Port Counter Registers........................................................................... 95 6.2.2 RMON Counter Registers ...................................................................... 96 Ethernet Address Registers ................................................................................ 99 6.3.1 Port Address Registers .......................................................................... 99 6.3.2 Search Address Registers...................................................................... 99 Repeater Port Control Registers .......................................................................101 6.4.1 General Port Control Registers ............................................................101 6.4.2 Port Link Control Register ....................................................................101 6.4.3 Port Learn Enable Register ..................................................................102 Repeater Port Status Registers.........................................................................102 PHY Port Status Registers ................................................................................104 PHY Port Control Registers...............................................................................107 Repeater Port Control/Status Registers ............................................................108 6.8.1 Device/Revision Register .....................................................................111 6.8.2 LED Control Registers.......................................................................... 111 6.8.3 LED Global Control Register ................................................................ 111 6.8.4 Port LED Control Register....................................................................111 6.8.5 LED Timer Control Register .................................................................112 6.8.6 Repeater Reset Register......................................................................113 6.8.7 Software Reset Register ......................................................................113 6.8.8 Interrupt Registers................................................................................113 Serial Controller Registers ................................................................................115 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 Mechanical Specifications...........................................................................................117 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 5 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 LXT98x0 Block Diagram ..................................................................................... 11 LXT98x0 Pin Assignments .................................................................................. 12 Typical LXT988x Managed Repeater Architectures ........................................... 32 MII Interface ........................................................................................................ 34 LED Blink Rates .................................................................................................. 39 Serial LED Shift Loading .................................................................................... 40 Serial LED Port Signaling.................................................................................... 41 100 Mbps IRB Connection .................................................................................. 49 IRB Block Diagram ............................................................................................. 50 LXT9880 MII Operation....................................................................................... 52 Typical SMI Bus Architecture ............................................................................. 52 SMI Collision Handling ........................................................................................ 54 SMI Address Match Indication ............................................................................ 54 Serial Management Frame Format ..................................................................... 55 Address Arbitration Mechanisms ....................................................................... 58 Optional R/W Serial PROM Interface.................................................................. 60 Serial Configuration Interface.............................................................................. 61 Serial Configuration Interface Signaling.............................................................. 61 8-Port Managed 10/100 Stackable Repeater...................................................... 62 32-Port Managed 10/100 Repeater..................................................................... 62 Power and Ground Connections ......................................................................... 65 Typical Twisted-Pair Port Interface and Power Supply Filtering ........................ 67 Typical Serial Management Interface Connections............................................. 68 Serial Controller Connection Showing PAL......................................................... 68 Serial PROM Interface ........................................................................................ 69 Typical Reset Circuit .......................................................................................... 69 LED Circuits - Direct Drive & Multiplexed Configuration Inputs .......................... 70 Serial LED Circuit................................................................................................ 71 100 Mbps Backplane Connection between LXT98x and LXT98x0 ..................... 73 Typical 100 Mbps IRB Implementation ............................................................... 74 Typical 10 Mbps IRB Implementation ................................................................ 74 100 Mbps TP Port-to-Port Delay Timing ............................................................. 79 100BASE-TX MII-to-TP Port Timing ................................................................... 80 100BASE-TX TP-to-MII Timing ........................................................................... 81 10BASE-T MII-to-TP Timing ............................................................................... 82 10BASE-T TP-to-MII Timing ............................................................................... 83 100 Mbps TP-to-IRB Timing................................................................................ 84 10 Mbps TP-to-IRB Timing.................................................................................. 84 10 Mbps IRB-to-TP Port Timing .......................................................................... 85 Serial Management Interface Timing .................................................................. 86 PROM Interface Timing....................................................................................... 87 LXT98x0 Package Specifications for Commercial Temperature....................... 117 LXT98x0 Package Specifications for Extended Temperature........................... 118 6 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Signal Types........................................................................................................ 13 LXT98x0 Pins, Numeric Order ............................................................................ 13 MII #1 Signal Descriptions................................................................................... 20 MII #2 Signal Descriptions................................................................................... 21 Inter-Repeater Backplane Signal Descriptions.................................................... 22 Twisted-Pair Port Signal Descriptions ................................................................. 25 Serial Management Interface Signal Descriptions .............................................. 26 LED Signal Descriptions...................................................................................... 27 Power Supply and Indication Signal Descriptions ............................................... 28 PROM Interface Signal Descriptions................................................................... 29 Miscellaneous Signal Descriptions...................................................................... 30 Serial LED Port Bit Stream.................................................................................. 41 ACTGLED Display Modes................................................................................... 42 LED Terms .......................................................................................................... 43 LED Mode 1 Indications ...................................................................................... 44 LED Mode 2 Indications ...................................................................................... 45 LED Mode 3 Indications ...................................................................................... 46 LED Mode 4 Indications ...................................................................................... 47 Cascading and Stacking Connections................................................................. 50 IRB Signal Details ............................................................................................... 51 SMI Message Fields............................................................................................ 55 SMI Header Storage............................................................................................ 55 SMI Command Set .............................................................................................. 56 Typical Serial Management Packets ................................................................... 57 LXT98x0 Magnetics Specifications ..................................................................... 66 Oscillator Manufacturers ..................................................................................... 67 Absolute Maximum Ratings................................................................................. 75 Operating Conditions........................................................................................... 75 Input System Clock1 Requirements .................................................................... 75 I/O Electrical Characteristics ............................................................................... 76 100 Mbps IRB Electrical Characteristics ............................................................. 76 10 Mbps IRB Electrical Characteristics ............................................................... 77 100BASE-TX Transceiver Electrical Characteristics........................................... 78 10BASE-T Transceiver Electrical Characteristics ............................................... 78 100 Mbps TP Port-to-Port Delay Timing Parameters.......................................... 79 100BASE-TX MII-to-TP Port Timing Parameters ................................................ 80 100BASE-TX TP-to-MII Timing Parameters........................................................ 81 10BASE-T MII-to-TP Timing Parameters ............................................................ 82 10BASE-T TP-to-MII Timing Parameters ............................................................ 83 100 Mbps TP-to-IRB Timing Parameters1 ................................................................................84 10 Mbps TP-to-IRB Timing Parameters1...................................................................................85 10 Mbps IRB-to-TP Port Timing Parameters....................................................... 86 Serial Management Interface Timing Characteristics.......................................... 86 PROM Interface Timing Characteristics .............................................................. 87 Register Map ....................................................................................................... 88 Port Counter Registers........................................................................................ 95 RMON Counter Registers - 10 Mbps .................................................................. 97 RMON Counter Registers - 100 Mbps ................................................................ 98 Ethernet Address Register Bit Assignments ....................................................... 99 7 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Port Address Tracking Registers ........................................................................ 99 Search Address/Search Address Match Register ............................................. 100 Search Address Register Bit Assignments ....................................................... 100 Search Match Address Bit Assignments ........................................................... 100 Search Match Address Bit Definitions............................................................... 100 Port Control Register Bit Assignments .............................................................. 101 General Port Control Registers ......................................................................... 101 Port Link Control and Status Register Bit Assignments .................................... 101 Port Link Control Register ................................................................................. 102 Port Learn Enable Register............................................................................... 102 Port Learn Enable Register............................................................................... 102 Port Status Register Bit Assignments ............................................................... 103 Port Status Registers ........................................................................................ 103 MII Speed Status Bit Assignments .................................................................... 103 MII Status Bit Definitions ................................................................................... 103 Auto-Negotiation Registers ............................................................................... 104 Auto-Negotiate Link Partner Advertisement Bit Definitions............................... 104 Auto-Negotiate Expansion Bit Definitions ......................................................... 105 PHY Port Status Register Summary ................................................................. 105 PHY Port Status Register Bit Definitions........................................................... 106 Auto-Negotiation Advertisement Registers ....................................................... 107 Auto Negotiate Advertisement Bit Definitions ................................................... 107 PHY Port Control Register ................................................................................ 107 PHY Port Control Bit Definitions........................................................................ 108 Configuration Registers..................................................................................... 108 Repeater Configuration Register....................................................................... 109 Repeater Serial Configuration........................................................................... 110 Device/Revision Register Bit Assignment ......................................................... 111 Global Fault LED Bit Assignments .................................................................... 111 .......................................................................................................................... 111 LED Configuration............................................................................................. 112 Port LED1, 2, 3 Control Encodings ................................................................... 112 LED Timer Control Register Bit Assignments ................................................... 112 Repeater Reset ................................................................................................. 113 Software Reset.................................................................................................. 113 Interrupt Status/Mask Register.......................................................................... 113 Interrupt Status Register Bit Definitions ............................................................ 114 Interrupt Mask Bit Definitions ............................................................................ 115 Configuration Registers..................................................................................... 115 Assign Addr 1.................................................................................................... 115 Assign Addr 2.................................................................................................... 116 PROM Addr 1.................................................................................................... 116 PROM Addr 2.................................................................................................... 116 8 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Revision History Date August 2001 January 2001 Revision 003 002 Page 75 Title Page 13 38 38 65 Description Changed Absolute Maximum Ratings Supply Voltage value to 4.0V. Added extended temperature range to title page. Modified LXT98x0 Pins, Numeric Order table (Pins 10, 11, 17, 19, 20, 185. Modified clock requirements language. Replaced TBD with 3.15V under Reset. Under Twisted Pair Interface, 4th bullet: Replaced text containingTBDs with: A ferrite bead with a total maximum current rating of 1.5Amp is recommended. Modified Oscillator Manufacturers table. Modified Absolute Maximum Ratings table. Modified Operating Conditions table. Mechanical Specifications: Add part number LXT98x0AHC to LXT98x0 Package Specifications Commercial Temperature figure; Add page for LXT98x0 Package Specifications Extended Temperature figure. 67 75 75 117, 118 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 9 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 1. LXT98x0 Block Diagram 10M IRB 10 Mbps Backplane 100 Mbps Backplane 10BASE-T Repeater 100BASE-X Repeater 10/100 PHY 1 10/100 PHY 2 10/100 PHY 3 Port Switching Logic TX_I/O TX_I/O TX_I/O TX_I/O TX_I/O TX_I/O TX_I/O TX_I/O 100M IRB Mode Control Serial Mgmt 10/100 PHY 4 10/100 PHY 5 10/100 PHY 6 10/100 PHY 7 10/100 PHY 8 Serial Port Device Management RMON & SNMP Counters Port & Mgmt Status Indicators Serial LED Drivers MII 1 MII 2 MII_I/O MII_I/O 1.0 Other Related Documents... The LXT98x0 Design and Layout Guide (formerly Application Note 113) provides detailed design and layout guidelines. The IRB Design and Layout Guide (formerly Application Note 112) provides detailed guidelines design and layout of Intel's Inter-Repeater Backplane (IRB). The LXT98x-to-LXT98x0 Migration Guide (formerly Application Note 111) compares features and registers of the LXT98x and more recent LXT98x0 devices. The LXT9883/LXT9863 Data Sheet specifically details the unmanaged eight-port and six-port devices. The High-Speed Serial Management Interface (formerly Application Note 64) explains how to connect an SCC to Intel devices and how to implement management across a network system. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 11 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 2.0 Pin Assignments and Signal Descriptions Figure 2. LXT98x0 Pin Assignments 52 .......... NC 51 .......... NC 50 .......... IR100CLK 49 .......... IR100DAT4 48 .......... IR100DAT3 47 .......... VCC 46 .......... GND 45 .......... IR100DAT2 44 .......... IR100DAT1 43 .......... IR100DAT0 42 .......... IR100DV 41 .......... IR100DEN 40 .......... IR100COL 39 .......... COMP_SEL 38 .......... IR100SNGL 37 .......... IR100CFSBP 36 .......... IR100CFS 35 .......... MII1_RXD3 34 .......... MII1_RXD2 33 .......... CONFIG0/CFG_DT 32 ......... MII1_RXD1 31 .......... MII1_RXD0 30 .......... MII1_RXDV 29 .......... MII1_RXCLK 28 .......... VCC 27 .......... GND 26 .......... MII1_RXER 25 .......... CONFIG1/CFG_LD 24 .......... MII1_TXER 23 .......... MII1_TXCLK 22 .......... MII1_TXEN 21 .......... MII1_TXD0 20 .......... MII1_TXD1 19 .......... MII1_TXD2 18 .......... MII2_SPD 17 .......... MII1_TXD3 16 .......... VCC 15 .......... GND 14 .......... MII1_COL 13 .......... MII1_CRS 12 .......... IR10CLK 11 .......... IR10DAT 10 .......... IR10ENA 9 ............ MII1_SPD 8 ............ VCC 7 ............ GND 6 ............ IR10DEN 5 ............ IR10CFSBP 4 ............ IR10COLBP 3 ............ IR10COL 2 ............ IR10CFS 1 ............ GND RESET ....... 53 CLK25 ....... 54 IR10ISO ....... 55 IR100ISO ....... 56 RECONFIG ....... 57 SRX ....... 58 STX ....... 59 SERCLK ....... 60 VCC ....... 61 GND ....... 62 SER_MATCH ....... 63 MMSTROUT....... 64 ARBOUT....... 65 N/C ....... 66 MGR_PRES ....... 67 PROM_CLK ....... 68 PROM_CS ....... 69 PROM_DTOUT....... 70 PROM_DTIN ....... 71 CHIPID0 ....... 72 CHIPID1 ....... 73 VCC ....... 74 GND ....... 75 VCC ....... 76 VCC ....... 77 RPS_FAULT....... 78 RPS_PRES ....... 79 MACACTIVE ....... 80 HOLDCOL ....... 81 LEDCLK/CFG_CLK ...82 LEDDAT ....... 83 LEDLAT ....... 84 VCC ....... 85 GND ....... 86 PORT1_LED3 ....... 87 PORT1_LED2 ....... 88 PORT1_LED1 ....... 89 GND ....... 90 PORT2_LED3 ....... 91 PORT2_LED2 ....... 92 PORT2_LED1 ....... 93 GND ....... 94 PORT3_LED3 ....... 95 PORT3_LED2 ....... 96 PORT3_LED1 ....... 97 GND ....... 98 PORT4_LED3 ....... 99 PORT4_LED2 ....... 100 PORT4_LED1 ....... 101 RBIAS ....... 102 GND ....... 103 TPIP1 ....... 104 Part # LOT # FPO # LXT98x0 XX XXXXXX XXXXXXXX Rev # 208........MII2_RXD3 207........MII2_RXD2 206........MII2_RXD1 205........MII2_RXD0 204........MII2_RXDV 203........MII2_RXCLK 202........MII2_RXER 201........MMSTRIN 200........VCC 199........GND 198........ARBIN 197........MII2_TXER 196........MII2_TXCLK 195........MII2_TXEN 194........MII2_TXD0 193........MII2_TXD1 192........MII2_TXD2 191........MII2_TXD3 190........VCC 189........GND 188........MII2_COL 187........MII2_CRS 186........ARBSELECT/COL100_LED 185........LEDSEL1/COL10_LED 184........LEDSEL0/ACT100_LED 183........ AUTOBLINK/ACT10_LED 182........ IRQ 181........GND 180........VCC 179........GND 178........N/C 177........VCC 176........PORT8_LED1* 175........PORT8_LED2*/LEDABGSEL 174......... PORT8_LED3* 173........VCC 172........GND 171........PORT7_LED1* 170........PORT7_LED2* 169........PORT7_LED3* 168........GND 167........PORT6_LED1 166........PORT6_LED2 165........PORT6_LED3 164........GND 163........PORT5_LED1 162........PORT5_LED2 161........PORT5_LED3 160........TxSLEW_1 159........TxSLEW_0 158......... GND 157........*TPIP8 TPIN1 ....... 105 VCCR ....... 106 TPOP1 ....... 107 TPON1 ....... 108 GND ....... 109 TPON2 ....... 110 TPOP2 ....... 111 VCCT ....... 112 VCCR ....... 113 TPIN2 ....... 114 TPIP2 ....... 115 GND ....... 116 GND ....... 117 TPIP3 ....... 118 TPIN3 ....... 119 VCCR ....... 120 TPOP3 ....... 121 TPON3 ....... 122 GND ....... 123 TPON4 ....... 124 TPOP4 ....... 125 VCCT ....... 126 VCCR ....... 127 TPIN4 ....... 128 TPIP4 ....... 129 GND ....... 130 GND ....... 131 TPIP5 ....... 132 TPIN5 ....... 133 VCCR ....... 134 VCCT ....... 135 TPOP5 ....... 136 TPON5 ....... 137 GND ....... 138 TPON6 ....... 139 TPOP6 ....... 140 VCCR ....... 141 TPIN6 ....... 142 TPIP6 ....... 143 GND ....... 144 GND ....... 145 *TPIP7.......146 *TPIN7.......147 * Indicates LXT9880-only pins. TP Ports 7 and 8 are not available on LXT9860 devices. 12 *TPOP7.......150 *TPON7.......151 GND ....... 152 *TPON8.......153 *TPOP8.......154 VCCR ....... 155 *TPIN8.......156 VCCR ....... 148 VCCT ....... 149 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 1. Signal Types Type I O I/O A OD OS PD PU NC Name Input Output Bidirectional Analog Open Drain Open Source Pull Down Pull Up No Clamp Standard input-only signal. Standard output-only signal. Input and output signal. Current source signal. Output that will only drive the signal Low. Output that will only drive the signal High. Internal, weak pull down signal. Internal, weak pull up signal. Pad does not clamp input in the absence of power. Definition Table 2. LXT98x0 Pins, Numeric Order Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. GND IR10CFS IR10COL IR10COLBP IR10CFSBP IR10DEN GND VCC MII1_SPD IR10ENA IR10DAT IR10CLK MII1_CRS MII1_COL GND VCC MII1_TXD3 MII2_SPD MII1_TXD2 MII1_TXD1 MII1_TXD0 Symbol Type 1,2 A, I/O, OD I/O, OD, PU I/O, OD A I/O, OD O, OD I, PU O, O I/O O O I I I I I Reference for Full Description Table 9 on page 28 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 9 on page 28 Table 9 on page 28 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 5 on page 22 Table 3 on page 20 Table 3 on page 20 Table 9 on page 28 Table 9 on page 28 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 13 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 2. LXT98x0 Pins, Numeric Order Pin 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. Symbol MII1_TXEN MII1_TXCLK MII1_TXER CONFIG1/CF MII1RXER GND VCC MII1_RXCLK MII1_RXDV MII1_RXD0 MII1_RXD1 CONFIG/CFG_DT MII1_RXD2 MII1_RXD3 IR100CFS IR100CFSBP IR100SNGL COMP_SEL IR100COL IR100DEN IR100DV IR100DAT0 IR100DAT1 IR100DAT2 GND VCC IR100DAT3 IR100DAT4 IR100CLK NC NC RESET CLK25 IR10ISO Type1,2 I I I I/O I O O O O I O O A I/O A I/O I/O AI O O I/O I/O I/O I/O I/O I/O I/O I I O Reference for Full Description Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 11 on page 30 Table 3 on page 20 Table 9 on page 28 Table 9 on page 28 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 3 on page 20 Table 12 on page 41 Table 3 on page 20 Table 3 on page 20 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 9 on page 28 Table 9 on page 28 Table 5 on page 22 Table 5 on page 22 Table 5 on page 22 Table 11 on page 30 Table 11 on page 30 Table 11 on page 30 Table 11 on page 30 Table 5 on page 22 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. 14 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 2. LXT98x0 Pins, Numeric Order Pin 56. 57. 58. 59. 60. 61. 62. 63. 64. 65. 66. 67. 68. PROM_CLK 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. PROM_CS PROM_DTOUT PROM_DTIN CHIPID0 CHIPID1 VCC GND VCC VCC RPS_FAULT RPS_PRES MACACTIVE HOLDCOL LEDCLK CFG_CLK LEDDAT LEDLAT VCC Symbol IR100ISO RECONFIG SRX STX SERCLK VCC GND SER_MATCH MMSTROUT ARBOUT NC MGR_PRES O O O I PU I/O Tri-State PD O, Tri-State O, Tri-State I, PD I PD I PD I, PU I, PU I, PD I/O, PD O O O Type 1,2 O I, PD I, PD O, OD I/O, Tri-State, PD Reference for Full Description Table 5 on page 22 Table 7 on page 26 Table 7 on page 26 Table 7 on page 26 Table 7 on page 26 Table 9 on page 28 Table 9 on page 28 Table 7 on page 26 Table 5 on page 22 Table 7 on page 26 Table 11 on page 30 Table 7 on page 26 Table 10 on page 29 Table 10 on page 29 Table 10 on page 29 Table 10 on page 29 Table 11 on page 30 Table 11 on page 30 Table 9 on page 28 Table 9 on page 28 Table 9 on page 28 Table 9 on page 28 Table 9 on page 28 Table 9 on page 28 Table 5 on page 22 Table 5 on page 22 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 15 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 2. LXT98x0 Pins, Numeric Order Pin 86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. 105. 106. 107. 108. 109. 110. 111. 112. 113. 114. 115. 116. 117. 118. 119. GND PORT1_LED3 PORT1_LED2 PORT1_LED1 GND PORT2_LED3 PORT2_LED2 PORT2_LED1 GND PORT3_LED3 PORT3_LED2 PORT3_LED1 GND PORT4_LED3 PORT4_LED2 PORT4_LED1 RBIAS GND TPIP1 TPIN1 VCCR TPOP1 TPON1 GND TPON2 TPOP2 VCCT VCCR TPIN2 TPIP2 GND GND TPIP3 TPIN3 Symbol Type1,2 O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD A AI AI AO AO AO AO AI AI AI AI Reference for Full Description Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. 16 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 2. LXT98x0 Pins, Numeric Order Pin 120. 121. 122. 123. 124. 125. 126. 127. 128. 129. 130. 131. 132. 133. 134. 135. 136. 137. 138. 139. 140. 141. 142. 143. 144. 145. 146. 147. 148. 149. 150. 151. 152. 153. Symbol VCCR TPOP3 TPON3 GND TPON4 TPOP4 VCCT VCCR TPIN4 TPIP4 GND GND TPIP5 TPIN5 VCCR VCCT TPOP5 TPON5 GND TPON6 TPOP6 VCCR TPIN6 TPIP6 GND GND TPIP7 TPIN7 VCCR VCCT TPOP7 TPON7 GND TPON8 Type 1,2 AO AO AO AO AI AI AI AI AO AO AO AO AI AI AI AI AO AO AO Reference for Full Description Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 17 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 2. LXT98x0 Pins, Numeric Order Pin 154. 155. 156. 157. 158. 159. 160. 161. 162. 163. 164. 165. 166. 167. 168. 169. 170. 171. 172. 173. 174. 175. Symbol TPOP8 VCCR TPIN8 TPIP8 GND TxSLEW_0 TxSLEW_1 PORT5_LED3 PORT5_LED2 PORT5_LED1 GND PORT6_LED3 PORT6_LED2 PORT6_LED1 GND PORT7_LED3 PORT7_LED2 PORT7_LED1 GND VCC PORT8_LED3 PORT8_LED2 LEDABGSEL 176. 177. 178. 179. 180. 181. 182. 183. PORT8_LED1 VCC N/C GND VCC GND IRQ AUTOBLINK/ ACT10LED 184. LEDSEL0 ACT_100_LED 3 Type1,2 AO AI AI I, PD I, PD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD O, OD I , O-OD/OS O, OD O, OD I3, O-OD/OS I , O-OD/OS I , O-OD/OS I3, O-OD/OS 3 3 Reference for Full Description Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 9 on page 28 Table 6 on page 25 Table 6 on page 25 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 9 on page 28 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 9 on page 28 Table 11 on page 30 Table 9 on page 28 Table 9 on page 28 Table 9 on page 28 Table 11 on page 30 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 Table 8 on page 27 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. 18 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 2. LXT98x0 Pins, Numeric Order Pin 185. Symbol LEDSEL1 COL10_LED 186. ARBSELECT COL100_LED 187. 188. 189. 190. 191. 192. 193. 194. 195. 196. 197. 198. 199. 200. 201. 202. 203. 204. 205. 206. 207. 208. MII2_CRS MII2_COL GND VCC MII2_TXD3 MII2_TXD2 MII2_TXD1 MII2_TXD0 MII2_TXEN MII2_TXCLK MII2_TXER ARBIN GND VCC MMSTRIN MII2_RXER MII2_RXCLK MII2_RXDV MII2_RXD0 MII2_RXD1 MII2_RXD2 MII2_RXD3 Type 1,2 I3, O-OD/OS I3, O-OD/OS I , O-OD/OS I , O-OD/OS O O I I I I I O I I, PD I, PD O O O O O O O 3 3 Reference for Full Description Table 8 on page 27 Table 8 on page 27 Table 7 on page 26 Table 8 on page 27 Table 4 on page 21 Table 4 on page 21 Table 9 on page 28 Table 9 on page 28 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 7 on page 26 Table 9 on page 28 Table 9 on page 28 Table 5 on page 22 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 Table 4 on page 21 1. Refer to Table 1 for Signal Type definitions. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 19 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 3. MII #1 Signal Descriptions Pin Symbol MII1_SPD Type1, 2 I PU Description Speed Select - MII 1. This signal is sensed at power up, hardware reset, and software reset. Selects operating speed of the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. Receive Data - MII 1. The LXT98x0 transmits received data to the controller on these outputs. Data is driven on the falling edge of MII1_RXCLK. Receive Data Valid - MII 1. Active High signal, synchronous to MII1_RXCLK, indicates valid data on MII1_RXD<3:0>. Receive Clock - MII 1. MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived from the CLK25 input (refer to Table 11 on page 30). Receive Error - MII 1. Active High signal, synchronous to MII1_RXCLK, indicates invalid data on MII1_RXD<3:0>. Transmit Error - MII 1. MII1_TXER is a 100 Mbps-only signal. The MAC asserts this input when an error has occurred in the transmit data stream. The LXT98x0 responds by sending `Invalid Code Symbols' on the line. Transmit Clock - MII 1. This is a 2.5 or 25 MHz clock derived from the CLK25 input (refer to Table 11 on page 30). Transmit Enable - MII 1. External controllers drive this input High to indicate data is transmitted on the MII1_TXD<3:0> pins. Ground this input if unused. Transmit Data - MII 1. External controllers use these inputs to transmit data to the LXT98x0. The LXT98x0 samples MII1_TXD<3:0> on the rising edge of MII1_TXCLK, when MII1_TXEN is High. Collision - MII 1. The LXT98x0 drives this signal High to indicate a collision occurred. Carrier Sense - MII 1. Active High signal indicates LXT98x0 is transmitting or receiving. 9 31 32 34 35 30 MII1_RXD0 MII1_RXD1 MII1_RXD2 MII1_RXD3 MII1_RXDV O O 29 MII1_RXCLK O 26 MII1_RXER MII1_TXER O 24 I 23 MII1_TXCLK O 22 21 20 19 17 14 13 MII1_TXEN MII1_TXD0 MII1_TXD1 MII1_TXD2 MII1_TXD3 MII1_COL MII1_CRS I I O O 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 20 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 4. MII #2 Signal Descriptions Pin Symbol Type1, 2 I PU Description Speed Select - MII 2. This signal is sensed at power up, hardware reset, and software reset. Selects operating speed of the respective MII (MAC) interface. High = 100 Mbps. Low = 10 Mbps. Receive Data - MII 2. The LXT98x0 transmits received data to the controller on these outputs. Data is driven on the falling edge of MII2_RXCLK. Receive Data Valid - MII 2. Active High signal, synchronous to MII2_RXCLK, indicates valid data on MII2_RXD<3:0>. Receive Clock - MII 2. MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived from the CLK25 input (refer to Table 11 on page 30). Receive Error - MII 2. Active High signal, synchronous to MII2_RXCLK, indicates invalid data on MII2_RXD<3:0>. Transmit Error - MII 2. MII2_TXER is a 100 Mbps-only signal. The MAC asserts this input when errors occurs in the transmit data stream. The LXT98x0 sends `Invalid Code Symbols' on the line. Transmit Clock - MII 2. This is a 2.5 or 25 MHz clock derived from the CLK25 input (refer to Table 11 on page 30). Transmit Enable - MII 2. External controllers drive this input High to indicate data is transmitted on the MII2_TXD<3:0> pins. Ground this input if unused. Transmit Data - MII 2. External controllers use these inputs to transmit data to the LXT98x0. The LXT98x0 samples MII2_TXD<3:0> on the rising edge of MII2_TXCLK, when MII2_TXEN is High. 18 MII2_SPD 205 206 207 208 204 MII2_RXD0 MII2_RXD1 MII2_RXD2 MII2_RXD3 MII2_RXDV O O 203 MII2_RXCLK O 202 MII2_RXER MII2_TXER O 197 I 196 MII2_TXCLK MII2_TXEN O 195 194 193 192 191 188 I MII2_TXD0 MII2_TXD1 MII2_TXD2 MII2_TXD3 O MII2_COL O I Collision - MII 2. The LXT98x0 drives this signal High to indicate a collision occurred. Carrier Sense - MII 2. Active High signal indicates LXT98x0 is transmitting or receiving. 187 MII2_CRS 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 21 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 5. Inter-Repeater Backplane Signal Descriptions Pin Symbol Type 1, 2 Common IRB Signals Compatibility Mode Select. 3.3V on this pin causes the IRCFSBP signals to operate in 3.3V only mode. 5V on this pin causes the IR100CFSBP or IR10CFSBP signals to operate in 5V backwards compatibility mode with legacy LXT98x and LXT91x devices. 100 Mbps IRB Signals 100 Mbps IRB Collision Force Sense. A three-level signal that determines number of active ports on the "logical" repeater. High level (3.3V) indicates no ports active; Mid level (approx. 1.6V) indicates one port active; Low level (0V) indicates more than one port active, resulting in a collision. This signal requires a 215 pull-up resistor, and connects between ICs on the same board. 100 Mbps IRB Collision Force Sense - Backplane. This threelevel signal functions the same as IR100CFS; however, it connects between ICs with Chip ID = 00, on different boards. IR100CFSBP requires a single 91 pull-up resistor in each stack. This signal can be set in either 5V or 3.3V modes by the COMP_SEL pin. 100 Mbps Single Driver State. This active Low signal is asserted by the device with Chip ID = 00 when a packet is received from one or more ports. Do not connect this signal between boards. Description 39 COMP_SEL AI 36 IR100CFS3 A I/O OD 37 IR100CFSBP A I/O OD 38 IR100SNGL I/O Schmitt PU 40 IR100COL I/O Schmitt PU 100 Mbps Multiple Driver State. This active Low signal is asserted by the device with Chip ID = 00 when a packet is being received from more than one port (collision). Do not connect this signal between boards. 100 Mbps IRB Driver Enable. This output provides directional control for an external bidirectional transceiver (74LVT245) used to buffer the 100 Mbps IRB in multi-board applications. It must be pulled up by a 330 resistor. When there are multiple devices on one board, tie all IR100DEN outputs together. If IR100DEN is tied directly to the DIR pin on a 74LVT245, attach the on-board IR100DAT, IR100CLK, and IR100DV signals to the "B" side of the 74LVT245, and connect the off-board signals to the "A" side of the 74LVT245. 100 Mbps IRB Data Valid. This active Low signal indicates port activity on the repeater. IR100DV frames the clock and data of the packet on the backplane. This signal requires a 300 pull-up resistor. 41 IR100DEN O OD 42 IR100DV I/O Schmitt OD PU 1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. IR100CFS is not 5V tolerant. 4. IR10CFS is not 5V tolerant. 22 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 5. Inter-Repeater Backplane Signal Descriptions (Continued) Pin 43 44 45 48 49 Symbol IR100DAT0 IR100DAT1 IR100DAT2 IR100DAT3 IR100DAT4 I/O Tri-state Schmitt PD 100 Mbps IRB Clock. This bidirectional, non-continuous, 25 MHz clock is recovered from received network traffic. Schmitt triggering is used to increase noise immunity. This signal must be pulled to VCC when idle. One 1 k pull-up resistor on both sides of a 74LVT245 buffer is recommended. 100 Mbps Stack Backplane Isolate. This output allows one LXT98x0 per board the ability to enable or disable an external bidirectional transceiver (74LVT245). Attach the output to the Enable input of the 74LVT245. The output is driven High (disable) to isolate the 100 Mbps IRB. 10 Mbps IRB Signals I/O OD PD I/O Tri-state Schmitt PD 10 Mbps IRB Data. This bidirectional signal carries data on the 10 Mbps IRB. Data is driven and sampled on the rising edge of the corresponding IRCLK. This signal must be pulled High by a 330 resistor. Buffer this signal between boards. 10 Mbps10 Mbps IRB Clock. This bidirectional, non-continuous, 10 MHz clock is recovered from received network traffic. During idle periods, the output is high-impedance. Schmitt triggering is used to increase noise immunity. 10 Mbps IRB Driver Enable. This output provides directional control for an external bidirectional transceiver (74LVT245) used to buffer the IRBs in multi-board applications. It must be pulled up by a 330 resistor. When there are multiple devices on one board, tie all IR10DEN outputs together. If IR10DEN is tied directly to the DIR pin on a 74LVT245, attach the on-board IR10DAT, IR10CLK and IR10ENA signals to the "B" side of the 74LVT245, and connect the off-board signals to the "A" side of the 74LVT245. 10 Mbps IRB Enable. This active Low output indicates carrier presence on the IRB. A 330 pull-up resistor is required to pull the IR10ENA output High when the IRB is idle. When there are multiple devices, tie all IR10ENA outputs together. Buffer these signals between boards. 10 Mbps IRB Collision. This output is driven Low to indicate a collision occurred on the 10 Mbps segment. A 330 resistor is required on each board to pull this signal High when there is no collision. Do not connect between boards and do not buffer. Type1, 2 I/O Tri-state Schmitt PU Description 100 Mbps IRB Data. These bidirectional signals carry 5-bit data on the 100 Mbps IRB. Data is driven on the falling edge and sampled on the rising edge of IR100CLK. Buffer these signals between boards. 50 IR100CLK O 56 IR100ISO 11 IR10DAT 12 IR10CLK 6 IR10DEN O OD 10 IR10ENA I/O OD PU 3 IR10COL I/O OD PU 1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. IR100CFS is not 5V tolerant. 4. IR10CFS is not 5V tolerant. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 23 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 5. Inter-Repeater Backplane Signal Descriptions (Continued) Pin Symbol Type 1, 2 I/O OD Description 10 Mbps IRB Collision - Backplane. This active Low output has the same function as IR10COL, but is used between boards. Attach this signal only from the device with Chip ID = 00 to the backplane or connector, without buffering. The output must be pulled up by one 330 resistor per stack. 10 Mbps IRB Collision Force Sense. This three-state analog signal indicates transmit collision when driven Low. IR10CFS requires a 215, 1% pull-up resistor. Do not connect this signal between boards and do not buffer. 10 Mbps IRB Collision Force Sense - Backplane. Functions the same as IR10CFS, but connects between boards. Attach this signal only from the device with Chip ID = 0 to the backplane or connector, without buffering. This signal requires one 330, 1% pull-up resistor per stack. This signal can be set for 5V or 3.3V modes by the COMP_SEL pin. MAC Active. Active High input allows external ASICs to participate in 10 Mbps IRB. Driving data onto the IRB requires the external ASIC assert MACACTIVE High for one clock cycle, then assert IR10ENA Low. ASIC monitors IR10COL (active Low) for collision. By using MACACTIVE, the repeater--not the MAC-- drives the three-level IR10CFS pin. 10 Mbps IRB Isolate. By using IR10 ISO, one LXT98x0 per board can enable or disable an external bidirectional transceiver (74LVT245). Attach the output to the Enable input of the 74LVT245. Driven High (disable) to isolate the 10 Mbps IRB. Hold Collision for 10 Mbps mode. This active High signal is driven by the device with Chip ID = 00 to extend a non-local transmit collision to other devices on the same board. Do not attach the HOLDCOL signals from different boards together. Management Master Input. The Management Master (MM) daisy chain ensures collisions are counted correctly in multi-board applications. Attach the MMSTRIN input of each device to the MMSTROUT output of the previous device. Ground MMSTRIN of the first or only device. Management Master Output. MM daisy chain output. In hotswap applications, a 1 k - 3 k resistor can be used as a bypass between MMSTRIN and MMSTROUT. 4 IR10COLBP 2 IR10CFS4 A, I/O OD 5 IR10CFSBP A I/O OD 80 MACACTIVE I PD O 55 IR10ISO 81 HOLDCOL I/O PD 201 MMSTRIN I PD O 64 MMSTROUT 1. I = Input, O = Output, I/O = Input/Output, D = Digital, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. IR100CFS is not 5V tolerant. 4. IR10CFS is not 5V tolerant. 24 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 6. Twisted-Pair Port Signal Descriptions Pin 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 Symbol TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 TPOP4, TPON4 TPOP5, TPON5 TPOP6, TPON6 TPOP7, TPON7 TPOP8, TPON8 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 TPIP4, TPIN4 TPIP5, TPIN5 TPIP6, TPIN6 TPIP7, TPIN7 TPIP8, TPIN8 Tx Output Slew Controls 0 and 1. These pins select the TX output slew rate (rise and fall time) as follows: TxSLEW_1 160 159 TxSLEW_1 TxSLEW_0 I PD 0 0 1 1 TxSLEW_0 0 1 0 1 Slew Rate (Rise and Fall Time) 2.5 ns 3.1 ns 3.7 ns 4.3 ns AI Twisted-Pair Inputs - Ports 1 through 8. These pins are the positive and negative inputs to the respective ports' twistedpair receivers. For unused ports, tie together with 100 resistors and float. AO Twisted-Pair Outputs - Ports 1 through 8. These pins are the positive and negative outputs from the respective ports' twisted-pair line drivers. For unused ports, these pins can be left open. Type1 Description 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, AO = Analog Output, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 25 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 7. Serial Management Interface Signal Descriptions Pin Symbol Type1, 2, Description Reconfigure. This input determines whether SERCLK is an input or an output. When RECONFIG is High, the LXT98x0 drives SERCLK with a 625 kHz output. When RECONFIG is Low, SERCLK is an input to the LXT98x0. If the LXT98x0 detects a Low-to-High transition on RECONFIG, or if RECONFIG is High at power-up, it sends out a "Configuration Change" message (Start Flag with all 0s) on the bus. Serial Match. The LXT98x0 device with Chip ID = 00 asserts this active High output whenever it detects a message on the SMI matching the local Hub ID. See "Serial Management I/F" on page 52. Serial Receive. Receive data input for SMI. Must be tied to STX externally. SRX is sampled on the rising edge of SERCLK. Serial Transmit. Transmit data output for SMI. Must be tied to SRX externally. Data transmitted on STX is compared with data received on SRX. In the event of a mismatch, STX goes to a high impedance state. STX is driven on the falling edge of SERCLK. 57 RECONFIG I PD O 63 SER_MATCH 58 SRX I PD 59 STX O OD 60 SERCLK I/O Tri-state PD Serial Clock. Clock for SMI. Depending on RECONFIG, this pin is either a 625 kHz output or a 0 to 2 MHz input. 198 ARBIN I PD O 65 ARBOUT I3 O - OD/OS Arbitration In/Out. Used with Chain Arbitration. If used, tie ARBIN to ARBOUT of the previous device. ARBIN at the top of the daisy chain can be connected to ground or to ARBOUT of the SCC. If unused, tie ARBIN High. Arbitration Mode Select - Input. 0 = PROM based, 1 = chain based. This configuration pin also functions as the COL100 LED output (refer to Note 3 below and to Table 8). Manager Present. This signal is sensed at power up, hardware reset, and software reset. If the signal is High, it indicates no local manager is present, and the LXT98x0 enables all ports and sets all LEDs to operate in "hardware mode". If it is Low, indicating a manager is present, the LXT98x0 disables all ports, pending control of network manager. 186 ARBSELECT 67 MGR_PRES I PU 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static. Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. 26 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 8. LED Signal Descriptions Pin 184 185 Symbol LEDSEL0 LEDSEL1 Type1, 2 I3 O - OD/OS Description LED Mode Select - Input. See Note 3 in footer below. 00 = Mode 1, 01 = Mode 2, 10 = Mode 3, 11 = Mode 4 These pins are shared with the LEDACT100, LEDCOL10 outputs. I3 O - OD/OS LED Activity Bar Graph Mode Select - Input. See Note 2 in footer below. 0 = Base-10 Mode, 1 = Base-2 Mode Refer to "Activity Graph LEDs" on page 59. This pin is shared with the Port8_LED2 output. 183 AUTOBLINK I3 O - OD/OS O O LED Blink Mode Select - Input. See Note 3 in footer below. 0 = Auto blink on, 1 = Auto blink off This pin is shared with the LEDACT10 output. 83 84 LEDDAT LEDLAT LED Data. Serial data stream that is shifted into external Serialto-Parallel LED drivers. See "Serial LED Interface" on page 40. LED Latch. Parallel load clock for external Serial-to-Parallel LED drivers. See "Serial LED Interface" on page 40. LED Clock. Serial data stream clock for external Serial-toParallel LED drivers. See "Serial LED Interface" on page 40. Configuration Bus Clock. Refer to CFG_DT and CFG_LD pin description in Table 11 on page 30. CFG_CLK pulses whenever a read of the Serial Configuration Register occurs. See"Serial Configuration Interface" on page 60. LED Driver 1 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs" on page 42. Port8_LED1 must be pulled High via a 100-500k resistor if LED circuit not used. 175 LEDABGSEL 82 LEDCLK CFG_CLK O 176 171 167 163 101 97 93 89 175 170 166 162 100 96 92 88 174 169 165 161 99 95 91 87 PORT8_LED1 PORT7_LED1 PORT6_LED1 PORT5_LED1 PORT4_LED1 PORT3_LED1 PORT2_LED1 PORT1_LED1 PORT8_LED2 PORT7_LED2 PORT6_LED2 PORT5_LED2 PORT4_LED2 PORT3_LED2 PORT2_LED2 PORT1_LED2 PORT8_LED3 PORT7_LED3 PORT6_LED3 PORT5_LED3 PORT4_LED3 PORT3_LED3 PORT2_LED3 PORT1_LED3 O OD O OD LED Driver 2 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs" on page 42. The Port8_LED2 pin is shared with the LEDABGSEL configuration input. O OD LED Driver 3 - Ports 1 through 8. Programmable LED driver. Active Low. See "Direct Drive LEDs" on page 42. Port8_LED3 must be pulled High via a 100-500 k resistor if LED circuit not used. 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 27 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 8. LED Signal Descriptions (Continued) Pin 185 Symbol COL10_LED Type1, 2 I O - OD/OS Description 10 Mbps Collision LED Driver. Active output indicates collision on 10 Mbps segment. This pin is shared with the LEDSEL1 configuration input. 100 Mbps Collision LED Driver. Active output indicates collision on 100 Mbps segment. This pin is shared with the ARBSELECT configuration input (refer to Table 7 on page 26 and to Note 3 below). 10 Mbps Activity LED Driver. Active output indicates activity on 10 Mbps segment. This pin is shared with the AUTOBLINK configuration input (refer to Note 3 below). 100 Mbps Activity LED Driver. Active output indicates activity on 100 Mbps segment. This pin is shared with the LEDSEL0 configuration input (refer to Note 3 below). 186 COL100_LED I O - OD/OS 183 ACT10_LED I O - OD/OS I O - OD/OS 184 ACT100_LED 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. Even if the IRB is not used, required pull-up resistors must be installed as listed above. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3. Input must be static; Refer to "LED Pins Multiplexed with Configuration Inputs" on page 69 for information on pin use. Table 9. Power Supply and Indication Signal Descriptions Pin 8, 16, 28, 47, 61, 74, 76, 77, 85, 173, 177, 180, 190, 200 106, 113, 120, 127, 134, 141, 148, 155 112, 126, 135, 149 Symbol Type1, 2 Description Power Supply Inputs. Each of these pins must be connected to a common +3.3 VDC power supply. A de-coupling capacitor to digital ground should be supplied for every one of these pins. VCC - VCCR - Analog Supply Inputs - Receive. Each of these pins must be connected to a common +3.3 VDC power supply. A de-coupling capacitor to GND should be supplied for every one of these pins. Use ferrite beads to create a separate analog VCC plane. Analog Supply Inputs - Transmit. Each of these pins must be connected to a common +3.3 VDC power supply. A de-coupling capacitor to GND should be supplied for every one of these pins. Use ferrite beads to create a separate analog VCC plane. VCCT - 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 28 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 9. Power Supply and Indication Signal Descriptions (Continued) Pin 1, 7, 15, 27, 46, 62, 75, 86, 90, 94, 98, 103, 109, 116, 117, 123, 130, 131, 138, 144, 145, 152, 158, 164, 168, 172, 179, 181, 189, 199 102 Symbol Type1, 2 Description GND - Ground. Connect each of these pins to system ground plane. RBIAS A I PD I PU RBIAS. Used to provide bias current for internal circuitry. The 100 A bias current is provided through an external 22.1 k, 1% resistor to GND. Redundant Power Supply Present. Active High input indicates presence of redundant power supply. Tie Low if not used. Redundant Power Supply Fault. Active Low input indicates redundant power supply fault. The state of this input is reflected in the RPS_LED output (refer to LED section). Tie High if not used. 79 RPS_PRES 78 RPS_FAULT 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. Table 10. PROM Interface Signal Descriptions Pin Symbol Type1, 2 Description PROM Clock. 1 MHz clock for reading PROM data (Chip ID = 00). If a PROM is not used, this pin must be tied Low. All devices should be connected together. PROM_CLK is driven only by the device with ChipID = 00. (Sensed by other devices.) 68 PROM_CLK I/O Tri-State PD 69 PROM_CS O Tri-State PROM Chip Select. Selects PROM. Active High signal driven only when Chip ID = 00. PROM Data Output. Selects read instruction for PROM. Active High signal driven only when ChipID = 00. All devices should be connected together. PROM_CLK is driven only by the device with ChipID = 00. (Sensed by other devices.) PROM Data Input. If a PROM is not used, this input can be tied Low or High. 70 PROM_DTOUT O Tri-State 71 PROM_DTIN I PD 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 29 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 11. Miscellaneous Signal Descriptions Pin Symbol Type1, 2 Description Reset. This active Low input causes internal circuits, state machines and counters to reset (address tracking registers do not reset). On power-up, devices should not be brought out of reset until the power supply stabilizes to 3.3V. When there are multiple devices, it is recommended all be supplied by a common reset driven by an `LS14 or similar device. 25 MHz system clock. Refer to Table 29 on page 75 for clock requirements. Chip ID. These pins assign unique Chip IDs to as many as four devices on a single board. One device on each board must be assigned ChipID = 00. See "Serial Management I/F" on page 52. Configuration Register Input 0. The CONFIG[1:0] inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the Serial Configuration Register (hex address AC). This register may be read remotely through the Serial Management Interface (SMI). 33 CONFIG(0) / CFG_DT I PD Configuration Bus Data. Used in conjunction with CFG_CLK and CFG_LD, these pins provide an expansion capability for the functionality of CONFIG[1:0]. Using an external Parallel-to-Serial device, up to 8 Configuration inputs can be brought to the SMI for user access. The Configuration Mode Select bit (Bit 14) in the Repeater Configuration Register is used to choose between CONFIG[1:0] and CFG bus modes. (See Table 75 on page 109.) Configuration Register Input 1. The CONFIG[1:0] inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the Repeater Serial Configuration register. This register may be read remotely through the Serial Management Interface (SMI). 25 CONFIG(1) / CFG_LD I/O PD Configuration Bus Load (active Low). Used in conjunction with CFG_CLK and CFG_DT, this active Low pin provides an expansion capability for the functionality of CONFIG[1:0]. Using an external Parallel-to-Serial device, up to 8 Config. inputs can be brought to the SMI for user access. The Configuration Mode Select bit (Bit 14) in the Repeater Configuration Register is used to choose between CONFIG[1:0] and CFG bus modes. See Table 75 on page 109.) 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 53 RESET I Schmitt 54 CLK25 I Schmitt 72 73 CHIPID0 CHIPID1 I PD 30 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 11. Miscellaneous Signal Descriptions (Continued) Pin Symbol Type1, 2 Description Configuration Bus Clock. Refer to CFG_DT and CFG_LD pin description. CFG_CLK pulses whenever a read of the Serial Configuration Register occurs. Refer to "Serial Configuration Interface" on page 60. LED Clock. Serial data stream clock for external Serial-toParallel LED drivers. Refer to Table 8 for details. O OD Interrupt request. Active Low interrupt. Refer to register section for criteria and clearing options. Requires an external pull-up resistor. 51, 52, 66,178 CFG_CLK/ 82 LEDCLK O 182 IRQ NC - No Connects. Leave these pins unconnected. 1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input, A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up. NC = No Clamp. Pad does not clamp input in the absence of power. 2. Pins are 5V tolerant, unless indicated. 3.0 3.1 Functional Description Introduction As a fully integrated IEEE 802.3 compliant repeater capable of 10 Mbps and 100 Mbps operation, the LXT98x0 is a versatile device allowing great flexibility in Ethernet design solutions. Figure 3 shows a typical application. Refer to "Application Information" on page 61 for specific circuit implementations. This multi-port repeater provides six (LXT9860) or eight (LXT9880) 10BASE-T/100BASE-TX ports. In addition, each device also provides two Media Independent Interface (MII) expansion ports that may be connected to 10/100 MACs. The LXT98x0 provides two repeater state machines and two Inter-Repeater Backplanes (IRB) on a single chip--one for 10 Mbps and one for 100 Mbps operation. The 100 Mbps repeater meets IEEE 802.3 Class II requirements. Each port's operating speed may be selected independently. The autonegotiation capability of the LXT98x0 allows it to communicate with connected nodes and configure itself accordingly. The LXT98x0 supports RMON by providing on-chip counters and hardware assistance for a fully managed environment. The segmented backplane simplifies dual-speed operation, and allows multiple devices to be stacked and function as one logical Class II repeater. Up to 240 ports (192 TP ports and 48 MII ports) can be supported in a single stack. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 31 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 3. Typical LXT988x Managed Repeater Architectures 100M 10M Backplane Backplane LXT9880 IC Buffer 10M Backplane 10/100 10 Mbps 10BASE-T LXT9880 ICPHY Backplane 10/100 10 Mbps Repeater 10BASE-T LXT9880 IC PHY 10/100 Backplane Repeater 10/100 10Mbps 10BASE-TPHY 100BASEPHY 10/100 Backplane 100 Mbps X Repeater PHY 100BASE- 10/100 10/100 Backplane PHY 100 Mbps Repeater X PHY 10/100 Backplane 100BASE-X PHY 100Mbps Repeater 10/100 10/100 Backplane Device Repeater PHY 10/100 PHY Serial Management PHY 10/100 Device 10/100 Port Serial Management PHY PHY 10/100 Device Port Serial PHY 10/100 Management 10/100 PHY MII Port PHY 10/100 RMON & PHY 10/100 10/100 MII MII SNMP RMON & PHY PHY 10/100 MIIMII Counters SNMP 10/100 PHY LED RMON & Counters PHY 10/100 Drivers MII SNMP 10/100 PHY LED Counters PHY Drivers 10/100 LED PHY Drivers Buffer 100M Backplane Serial Management to SCC MII to MII Bridge 3.2 Port Configuration The LXT98x0 powers up in auto-negotiation mode for all twisted-pair ports. Software can monitor or change the configuration through the PHY Port Control Register. 3.2.1 Auto-Negotiation All TP ports on power up are configured to establish its link via auto-negotiation. The port and its link partner establish link conditions by exchanging Fast Link Pulse (FLP) bursts. Each FLP burst contains 16 bits of data advertising the port's capabilities. The FLP bursts sent by the port are maintained in its auto-negotiation advertisement register (Table 71 on page 107). The link partner's abilities are stored in the auto-negotiation link partner register (Table 66 on page 104). Status can be observed in the respective auto-negotiation status register (Table 65 on page 104). Each port has its own advertisement, link partner advertisement, auto-negotiation expansion, auto-negotiation status registers, and control register. The advertisement register is read-only, except for bits 5, 7, and 13. The LXT98x0 can advertise 100 Mbps half-duplex and/or 10 Mbps half-duplex; it never advertises full duplex. If the link partner does not support auto-negotiation, the LXT98x0 determines link state by listening for 100 Mbps IDLE symbols or 10 Mbps link pulses. If it detects either of these signals, it configures the port and updates the status registers appropriately. 32 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 3.2.2 Forced Operation A port can be directly configured to operate in either 100BASE-TX or 10BASE-T. When a port is configured for forced operation, it immediately operates in the selected mode. All links are established as half-duplex only. As a repeater, the LXT98x0 cannot support full-duplex operation. 3.2.3 Changing Port Speed - Forced To force a port speed change while operating, the following sequence is required: * Disable the port(s) to be changed. * Set PHY Port Control Register to desired speed. * Perform a Repeater Reset (at Register 144; see Table 83 on page 113. The LXT98x0 does not read hardware configuration pins). * Re-enable the port(s). Note: Forcing a speed change on any port requires a Repeater Reset. 3.2.4 Link Establishment and Port Connection Once a port establishes link, the LXT98x0 automatically connects it to the appropriate repeater state machine. If link loss is detected, the port returns to the auto-negotiation state. 3.2.5 MII Port Configuration These ports can be set via hardware tie ups/downs to be either 10 Mbps or 100 Mbps. The statistics for these ports are the same as for the other 10/100 ports, except Isolation, Partition, and Symbol Error. 3.3 Interface Descriptions The LXT9880 and LXT9860 devices provide eight and six network interface ports, respectively. Each port provides a twisted-pair interface. The twisted-pair interface directly supports 100BASETX and 10BASE-T. Ethernet applications and fully complies with IEEE 802.3 standards. A common termination circuit is used. 3.3.1 Twisted-Pair Interface The LXT98x0 pinout is optimized for dual-height RJ-45 connectors. The twisted-pair interface for each port consists of two differential signal pairs -- one for transmit and one for receive. The transmit signal pair is TPOP/TPON, the receive signal pair is TPIP/TPIN. The transmitter requires magnetics with 1:1 turns ratio. The center tap of the primary side of the transmit winding must be tied to a quiet VCC for proper operation. When the twisted-pair interface is disabled, the transmitter outputs are tri-stated. The receiver requires magnetics with a 1:1 turns ratio, and a load of 100 . When the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8V. When the twisted-pair interface is disabled, no biasing is provided. A 4 k load is always present across the TPIP/TPIN pair. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 33 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management When used in 100BASE-TX applications, the LXT98x0 sends and receives a continuous, scrambled 125Mbaud MLT-3 waveform on this interface. In the absence of data, IDLE symbols are sent and received in order to maintain the link. When used in 10BASE-T applications, the LXT98x0 sends and receives a non-continuous, 10 Mbaud Manchester-encoded waveform. To maintain link during idle periods, the LXT98x0 sends link pulses every 16 ms, and expects to receive them every 10 to 20ms. Each 10BASE-T port automatically detects and sends link pulses, and disables its transmitter if link pulses are not detected. Each receiver can also be configured to ignore link pulses, and leave its transmitter enabled all the time (link pulse transmission cannot be disabled). Each 10BASE-T port can detect and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T interface provides integrated filters using Intel's patented filter technology. These filters facilitate low-cost stack designs to meet EMI requirements. 3.3.2 Media Independent Interface The LXT98x0 has two identical MII interfaces. The MII has been designed to allow expansion to a Media Access Controller (MAC) as shown in Figure 4. This interface is not MDIO/MDC capable. Management is provided via a serial controller interface. These MII ports can be set via hardware tie ups/downs to be either 10 Mbps or 100 Mbps100 Mbps. The statistics kept for these ports are the same as for the other 10/100 ports, except Isolation, Partition, and Symbol Error. These ports are not the full MII drive strength and are intended only for point-to-point links. Serial terminations are recommended. Figure 4. MII Interface TXD(3:0) TXEN TXER TXCLK RXCLK MAC RXD(3:0) RX_DV RX_ER CRS COL LXT98x0 3.3.3 Serial Management Interface The Serial Management Interface (SMI) provides system access to the status, control and statistic gathering abilities of the LXT98x0. This interface allows multiple devices to be managed from a common line, and uses the minimum number of signals (2) for ease of stack design. The interface itself consists of two digital NRZ signals -- clock and data. Refer to Table 7 on page 26 for SMI pin assignments and signal descriptions. Data is framed into HDLC-like packets, with a start/stop flag, header and CRC field for error checking. Zero-bit insertion/removal is used. The interface can operate at any speed from 0 to 2 MHz. ("0 MHz" means the clock need not be continuous. It can be started, stopped, or restarted, provided sixteen 1s in a row are allowed between management packets.) 34 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. Refer to "Serial Management I/F" on page 52. 3.3.4 Serial PROM Interface The serial PROM interface allows the loading of optional information unique to each board. Items such as serial number or date of manufacture can be placed in the serial PROM, which is also used in the address arbitration process. See "Serial PROM Interface" on page 59. 3.4 Repeater Operation The LXT98x0 contains two internal repeater state machines -- one operating at 10 Mbps and the other at 100 Mbps. The LXT98x0 automatically switches each port to the correct repeater, once the operational state of that port has been determined. Each repeater connects all ports configured to the same speed (including the MII), and the corresponding Inter-Repeater Backplane. Both repeaters perform the standard jabber and partition functions. 3.4.1 100 Mbps Repeater Operation The LXT98x0 contains a complete 100 Mbps Repeater State Machine (100RSM) that is fully IEEE 802.3 Class II compliant. Any port configured for 100 Mbps operation is automatically connected to the 100 Mbps Repeater. This includes any of the eight media and two MII ports configured for 100 Mbps operation. The 100 Mbps RSM has its own Inter-Repeater Backplane (100IRB). Multiple LXT98x0s can be cascaded on the 100IRB and operate as one repeater segment. Data from any port is forwarded to all other ports in the cascade. The 100IRB is a 5-bit symbol-mode interface. It is designed to be stackable. The LXT98x0 maintains a complete set of statistics for its local 100 Mbps repeater segment. These are accessible through the high-speed serial management interface. The LXT98x0 performs the following 100 Mbps repeater functions: * Signal amplification, wave-shape restoration, and data-frame forwarding. * SOP, SOJ, EOP, EOJ delay < 46BT; class II compliant. * Collision Enforcement. During a 100 Mbps collision, the LXT98x0 drives a 0101 jam signal (encoded as Data 5 on TX links) to all ports until the collision ends. There is no minimum enforcement time. * Partition. The LXT98x0 partitions any port that participates in excess of 60 consecutive collisions or one long collision approximately 575.2 s long. Once partitioned, the LXT98x0 monitors and transmits to the port, but does not repeat data received from the port until it unpartitions. * Un-partition. The LXT98x0 supports two un-partition algorithms: -- The alternative un-partition algorithm (default), which complies with IEEE specification 802.3aa un-partitions a port on either transmit or receive of at least 450-560 bits without collision. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 35 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management -- The normal algorithm, which complies with the IEEE specification 802.3u, is available through the management interface. This algorithm un-partitions a port only when data is transmitted to the port for 450-560 bit times without a collision. * Isolate. The LXT98x0 isolates any port receiving more than two successive false carrier events. A false carrier event is a packet that does not start with a /J/K symbol pair. Note: this is not the same function as the 100IRB isolate function, which involves isolating the backplane. * Un-isolate. The LXT98x0 un-isolates a port that remains in the IDLE state for 33000 +/- 25% BT or that receives a valid frame at least 450-500 BT in length. * /T/R generation. The LXT98x0 can insert a /T/R symbol pair (End-of-Stream Delimiter) on any incoming packet that does not include one. This feature is optional, and is enabled through the management interface. * Jabber. The LXT98x0 ignores any receiver remaining active for more than 57,500 bit times. The LXT98x0 exits this state when either one of the following conditions is met: -- On power-up reset -- When carrier is no longer detected Note: The Isolate, Partition, and Symbol Error functions do not apply to MII ports. 3.4.2 10 Mbps Repeater Operation The LXT98x0 contains a complete 10 Mbps Repeater State Machine (10RSM) that is fully IEEE 802.3 compliant. Any port configured for 10 Mbps operation is automatically connected to the 10 Mbps Repeater. This includes any of the media and MII ports configured for 10 Mbps operation. The 10RSM has its own Inter-Repeater Backplane (10IRB). Multiple LXT98x0s can be cascaded on the 10IRB and operate as one repeater segment. Data from any port is forwarded to all other ports in the cascade. The LXT98x0 maintains a complete set of statistics on its 10 Mbps repeater segment. These are accessible through the high-speed serial management interface. The LXT98x0 performs the following 10 Mbps repeater functions: * * * * Signal amplification, wave-shape restoration, and data-frame forwarding. Preamble regeneration. All outgoing packets have a minimum 56-bit preamble and 8-bit SFD. SOP, SOJ, EOP, EOJ delays meet IEEE 802.3 section 9.5.5 and 9.5.6 requirements. Collision Enforcement. During a 10 Mbps collision, the LXT98x0 drives a jam signal ("1010") to all ports for a minimum of 96 bit times until the collision ends. partitioned, the LXT98x0 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. (Also partitions for excessive length of a collision.) * Partition. The LXT98x0 partitions any port in excess of 31 consecutive collisions. Once * Un-partition. The algorithm, which complies with the IEEE 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. * Jabber. The LXT98x0 asserts a minimum-IFG idle period when a port transmits for longer than 40,000 to 75,000 bit times. 36 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 3.5 3.5.1 Management Support Configuration and Status The LXT98x0 provides management control and visibility of the following functions: * * * * * * * 3.5.2 Counter Reset and Zeroing Auto-negotiation (Control, Status, Advertisement, Link Partner, and Expansion) Device and Board Configuration LED Functions Source Address Tracking (per port) Source Address Matching (per chip) Device/Revision ID SNMP and RMON Support The LXT98x0 provides SNMP and RMON support through its statistics gathering function. Statistics are gathered on all packets flowing through the device for each of the ports, including the MII. The LXT98x0 maintains statistics for both the entire 10 Mbps and 100 Mbps repeaters, independent of the speed setting of the MII ports. All statistics are stored in 32- or 64-bit registers. Per-port counters include: Readable Frames Alignment Errors Runts VeryLongEvents Broadcast Isolates Readable Octets FramesTooLong Collisions DataRateMismatch Multicast Symbol Errors FCS Errors ShortEvents LateEvents AutoPartitions SA Changes 3.5.3 Source Address Management The LXT98x0 provides two source address management functions per port: source address tracking and source address matching. These functions allow a network manager to track source addresses at each port, or to identify any port sourcing a particular address. 3.6 3.6.1 Requirements Power The LXT98x0 has four types of +3.3V power supply input pins: two digital (VCC, GND) and two analog (VCCR, VCCT). These inputs may be supplied from a single source. Ferrite beads should be used to separate the analog and digital planes. These supplies should be as clean as possible. Each supply input should be decoupled to ground. Refer to Table 9 on page 28 for power and ground pin assignments, and to the "General Design Guidelines" on page 61. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 37 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.6.2 Clock A stable, external 25 MHz reference clock source (TTL) is required to the CLK25 pin. The reference clock is used to generate transmit signals and recover receive signals. A crystal-based clock is recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to Table 26 on page 67 for a list of recommended oscillators and to Table 29 on page 75 for clock timing requirements. 3.6.3 Bias Resistor The RBIAS input requires a 22.1 k, 1% resistor connected to ground. 3.6.4 Reset At power-up, the reset input must be held Low until VCC reaches at least 3.15V. A buffer should be used to drive reset if there are multiple LXT98x0 devices. The clock must be active. Software and hardware resets are identical. Refer to Table 74 on page 108 and Table 84 on page 113 for Software Reset details. 3.6.5 PROM Although not required, an external, auto-incrementing 48-bit PROM can be used for two purposes: * Support the PROM-based address arbitration scheme on the Serial Management Interface (See "PROM Arbitration Mechanism" on page 58.) * Assign a unique ID and upload configuration data to all LXT98x0s on a board Multiple devices on the same board can share a single common PROM. The LXT98x0 with ChipID = 00 actively reads the PROM at power-up; all other LXT98x0s "listen in". If PROM arbitration is not used, the PROM data input signal must be tied either High or Low. (See "Serial PROM Interface" on page 59.) 3.6.6 Chip ID Each cascaded LXT98x0 requires a unique 2-bit Chip ID value. The Serial Management Interface (SMI) identifies each IC by ChipID. One LXT98x0 on each board must be assigned ChipID = 00. In the Header Field, the Chip Address is defined by three bits. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. Refer to "Serial Management I/F" on page 52. 3.6.7 Management Master I/O Link In multiple device applications, the Management Master daisy chain (MMSTRIN/MMSTROUT) ensures that collisions are counted correctly. Connect the MMSTRIN input to the MMSTROUT output of the previous device when cascading and stacking. Ground the MMSTRIN input of the first or only device. In hot-swap applications, resistive bypassing can be used with a 1 - 3 k value. 3.6.8 IRB Bus Pull-ups Even when the LXT98x0 is used in a stand-alone configuration, pull-up resistors are required on the IRB signals listed. See Figure 30 on page 74 and Figure 31 on page 74 for sample circuits. 38 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 100 Mbps IRB IR100CFS IR100CFSBP IR100DV IR100CLK 10 Mbps IRB IR10DAT IR10ENA IR10COL IR10CFS IR10COLBP IR10CFSBP 3.7 LED Operation The LXT98x0 drives the most commonly used LEDs directly (see "Direct Drive LEDs" on page 42). The less frequently used LEDs are optionally driven via a serial bus to inexpensive Serial-to-Parallel devices (see "Serial LEDs" on this page). 3.7.1 LEDs at Start-up For approximately 2 seconds after the LXT98x0 is reset, all LEDs are driven to the ON state. This start-up routine is an LED check. 3.7.2 LED Event Stretching Short lived LED status events are stretched so they may be observed by the human eye. Refer to the LED1, 2, 3 Modes section for stretching specifics. 3.7.3 LED Blink Rates Two programmable blink rates are provided. The default period for the slow blink rate is 1.6s. The default period is 0.4s for the fast blink rate. These rates may be changed via the LED Timer Control Register. The slow blink rate is defined by the upper 8 bits and the fast blink rate is defined by the lower 8 bits of the LED Timer Control Register. Refer to "LED Timer Control Register" on page 112 for details. Figure 5. LED Blink Rates Time On Solid Slow Blink Fast Blink Off Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 39 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.7.4 Serial LED Interface The LXT98x0 provides a serial interface to drive additional LEDs via external 8-bit Serial-toParallel converters. A maximum of 30 LEDs can be driven, using four S/P devices. Collision10/ 100, Activity10/100 status indications are output on multiplexed configuration pins and are duplicated on the Serial Port. (See "LED Pins Multiplexed with Configuration Inputs" on page 69.) 3.7.4.1 Serial Shifting Figure 6 shows the Serial LED shift loading. Figure 6. Serial LED Shift Loading 74X164 74X164 74X164 74X164 1 2 34 5 6 78 LXT98xx MII MII 1, 2, 3 MII1 LED1 MII1 LED2 MII1 LED3 MII2 LED1 MII2 LED2 MI2 LED3 Not Used Not Used Misc Misc Collision 10 Mbps Collision 100 Mbps Manager Present Activity 10 Mbps Activity 100 Mbps Global Fault Not Used RPS Fault ACT10 Activity 10 Mbps ACTG8 ACTG7 ACTG6 ACTG5 ACTG4 ACTG3 ACTG2 ACTG1 30 LEDs ACT100 Activity 100 Mbps ACTG8 ACTG7 ACTG6 ACTG5 ACTG4 ACTG3 ACTG2 ACTG1 Shift Order 8 7 6 5 4 3 2 1 3.7.4.2 Serial LED Signals The LED serial interface bus consists of three LXT98x0 outputs: clock (LEDCLK), parallel load clock (LEDLAT), and output data (LEDDAT). Refer to Table 8 on page 27 for signal descriptions and to Figure 28 on page 71 for an illustration of the LED serial interface circuit. Refer to Figure 7 and Table 12 for details on the LED serial bit stream. 40 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 7. Serial LED Port Signaling 122 s LEDDAT LEDLAT LEDCLK Time LEDDAT LEDLAT MII PORTS-LED1,2,3 Misc. LEDs ACTGLED10 ACTGLED100 LEDDAT b0 100 ns / 10 MHz b1 b2 b3 b4 b5 b6 b7 LEDCLK Qa'-Qh' (`595) Qa-Qh (`164) b7-b0 LEDLAT Qa-Qh (`595) b7-b0 b7-b0 b0, b7-b1 b1, b0, b7-b2 b2-b0, b7-b3 b3-b0, b7-b4 b4-b0, b7-b5 b5-b0, b7-b6 b6-b0, b7 b7-b0 Table 12. Serial LED Port Bit Stream Bit 7 6 5 4 3 2 1 0 MII Ports-LED1, 2, 3 MII Port 1 - LED1 MII Port 1 - LED2 MII Port 1 - LED3 MII Port 2 - LED1 MII Port 2 - LED2 MII Port 2 - LED3 Not Used Not Used Misc. Collision - 10M 1 1 ACTGLED10 ACTG8 ACTG7 ACTG6 ACTG5 ACTGLED100 ACTG8 ACTG7 ACTG6 ACTG5 ACTG4 ACTG3 ACTG2 ACTG1 Collision - 100M Manager Present Activity - 10M1 Activity - 100M Global Fault Not Used RPS Fault 1 ACTG4 ACTG3 ACTG2 ACTG1 1. These LEDs are multiplexed with Configuration Inputs. 3.7.4.3 Activity Graph LEDs The ACTGLED10 and ACTGLED100 LEDs are for activity bar graphing. The activity information is integrated and updated over a period of 328.125 ms, which has the effect of smoothing out the activity. LEDs are provided for both the 10 Mbps and 100 Mbps segments. There are two display modes for the activity bar graphs, Base-2 and Base-10. The modes are selected via the LEDABGSEL pin. Refer to Table 13 for details. Each step LED on the bar graph is lit when the percent activity value associated with that step is met or exceeded. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 41 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 13. ACTGLED Display Modes LED ACTG 8 ACTG 7 ACTG 6 ACTG 5 ACTG 4 ACTG 3 ACTG 2 ACTG 1 LEDABGSEL = 0 (Base-10) 60+% Activity 50% Activity 40% Activity 30% Activity 20% Activity 10% Activity 5% Activity 1% Activity LEDABGSEL = 1 (Base-2) 80+% Activity 64% Activity 32% Activity 16% Activity 8% Activity 4% Activity 2% Activity 1% Activity 3.7.5 Direct Drive LEDs The LXT98x0 provides three direct drive LEDs for each port (PORTn_LED1:3), excluding the two MII ports. Four additional segment LEDs indicate Collision 10/100 and Activity 10/100. The perport LEDs are updated simultaneously to illustrate clear, non-overlapping status. The following device pins are multifunctional (input = configuration; output = LED driver): COL10_LED (185), COL100_LED (186), ACT10_LED (183), ACT100_LED (184), and, PORT8_LED2 (175) . The LED drive level is determined by the particular input configuration function of the respective pin. Collision and Activity indications for both 10 Mbps and 100 Mbps segments are available in both serial and direct drive. Direct Drive LED outputs can be overridden by software control. Two bits per port configure the LEDs to one of four states: * * * * 3.7.6 LED Off LED On LED Fast Blink LED Under Hardware Control LED Modes The four available LED modes are described in Table 15 - Table 18. Hardware pins provide global LED mode control. Refer to Table 8 on page 27 for pin assignments and signal descriptions. Software can configure each port individually to operate in any mode. Refer to "Port LED Control Register" on page 111. "LED Global Control Register" on page 111 outlines how the Global LEDs are similarly controlled. Table 14 defines terms used to describe LED operation. 42 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 14. LED Terms Term Port_Enabled Link_Enabled Link_OK Port_Partitioned Port_Is_TP RPS_Present RPS_Fault Port_Ctl_HW Port_Ctl_Off Port_Ctl_On Port_Ctl_Fast Rcv_Activity Mgr_Present Definition True if port is enabled. (see Table 60 on page 102). True if link detection is enabled (see Table 58 on page 102.) True if link is enabled and link is detected or if link detection is disabled. Always true for MII port. True if port has been auto partitioned (10Mb mode). True if port has been auto partitioned or isolated (100Mb mode). True if port is a twisted-pair port. True if redundant power supply is switched in. True if redundant power supply has a fault. True if configuration bits are set to hardware control. True if configuration bits are set to turn off the LED. True if configuration bits are set to turn on the LED solid. True if configuration bits are set to fast blink the LED. True if twisted-pair port on this device is receiving a packet. True if MGR_PRES signal is active. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 43 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.7.6.1 LED Mode 1 Mode 1 operations are described in Table 15. Table 15. LED Mode 1 Indications Hardware Control1 LED Operating Mode On 10 Mbps operation PORTnLED1 100 Mbps operation 10 Mbps operation PORTnLED2 100 Mbps operation Autonegotiate enabled PORTnLED3 AUTOBLINK active AUTOBLINK inactive Link_OK, not Port_Partitioned N/A Link_OK, Port_Partitioned Not Link_OK (Fast Blink) N/A 100 Mbps mode selected Link_Enabled 10 Mbps mode selected Link_Enabled Off via port LED Control Register Any other state Blink Off Software Control 100 Mbps Link_OK 10 Mbps Link_OK Auto-negotiate disabled N/A The collision and activity LEDs are on a Per Segment basis. Pulse stretchers are used to extend the ontime for the LEDs. For every on- cycle of the stretched LEDs, an off-cycle, with the same period as the on-cycle, always follows. Collision and Activity LEDs Any The collision LEDs turn on for approximately 120 s when the LXT98x0 detects a collision on the segments. During the time that the LED is on, any additional collisions are ignored by the collision LED logic. The activity LEDs turn on for approximately 4 ms when the LXT98x0 detects any activity on the segments. During the time that the LED is on any additional activity is ignored by the activity LED logic. Any Port_Partitioned or RPS_Fault and RPS_Present RPS_Present, RPS_Fault Global Fault Any N/A Any other state RPS Fault Manager Present Any Any N/A Mgr_Present N/A Not Mgr_Present 1. Refer to Table 13: LED Terms, which defines all key terms used in this section. 44 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 3.7.6.2 LED Mode 2 Mode 2 operations are described in Table 16. Table 16. LED Mode 2 Indications LED Operating Mode Hardware Control1 On 10 Mbps: Port_Enabled, Link_OK, not Port_Partitioned Any 100 Mbps: Port_Enabled, Link_OK, not Port_Partitioned Rcv_Activity (20 ms pulse)2 Autonegotiate enabled PORTnLED3 AUTOBLINK active AUTOBLINK inactive 100 Mbps Link_OK 100 Mbps mode selected (Link_Enabled) Blink 10 Mbps: Port_Enabled, Link_OK, and Port_Partitioned (slow blink) 100 Mbps: Port_Enabled, Port_Partitioned (Slow Blink) N/A No Link_OK (Fast Blink) Any other state Off Software Control PORTnLED1 Any other state On, Off or Fast Blink via Port LED Control Register PORTnLED2 N/A 10 Mbps Link_OK 10 Mbps mode selected (Link_Enabled) N/A Off via Port LED Control Register Auto-negotiate disabled The collision and activity LEDs are on a Per Segment basis. Pulse stretchers are used to extend the ontime for the LEDs. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the oncycle, always follows. Collision and Activity LEDs Any The collision LEDs turn on for approximately 120 s when the LXT98x0 detects a collision on the segments. During the time that the LED is on, any additional collisions are ignored by the collision LED logic. The activity LEDs turn on for approximately 4 ms when the LXT98x0 detects any activity on the segments. During the time that the LED is on, any additional activity is ignored by the activity LED logic. Manager Present RPS Any Global FAULT N/A RPS_Present, no RPS_Fault N/A RPS_Present, RPS_Fault (Slow Blink) Any Port_Partitioned, any Port Isolated or RPS_Fault and RPS_Present (Slow Blink) Always Off Not RPS_Present N/A N/A N/A N/A Any other state On, off, or slow blink via global LED Control Register 1. Refer to Table 14: LED Terms, which defines all key terms used in this section. 2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the on-cycle, always follows. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 45 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.7.6.3 LED Mode 3 Mode 3 operations are described in Table 17. Table 17. LED Mode 3 Indications Hardware Control LED Operating Mode On 10 Mbps operation PORTnLED1 100 Mbps operation PORTnLED2 10 Mbps or 100 Mbps ops AUTOBLINK active AUTOBLINK inactive Link_OK, not Port_Partitioned Rcv_Activity (20 ms pulse)2 100 Mbps Link_OK 100 Mbps mode selected (Link_Enabled) N/A Blink Off Any other state Software Control Off via port LED Control Register N/A N/A No Link_OK (Fast Blink) Any other state 10 Mbps Link_OK 10 Mbps mode selected (Link_Enabled) PORTnLED3 Autonegotiate enabled N/A Off via port LED Control Register Auto-negotiate disabled The collision and activity LEDs are on a Per Segment basis. Pulse stretchers are used to extend the on-time for the LEDs. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the on-cycle, always follows. Collision and Activity LEDs Any The collision LEDs turn on for approximately 120 s when the LXT98x0 detects a collision on the segments. During the time that the LED is on, any additional collisions is ignored by the collision LED logic. The activity LEDs turn on for approximately 4 ms when the LXT98x0 detects any activity on the segments. During the time that the LED is on, any additional activity is ignored by the activity LED logic. Any Port_Partitioned Global Fault Any RPS Fault Manager Present or RPS_Fault and RPS_Present RPS_Present, RPS_Fault Mgr_Present N/A Not Mgr_Present N/A Any other state Off via global LED Control Register N/A N/A N/A 1. Refer to Table Table 14: LED Terms, which defines all key terms used in this section. 2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the on-cycle, always follows. 46 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 3.7.6.4 LED Mode 4 Mode 4 operations are described in Table 18. Table 18. LED Mode 4 Indications Hardware Control1 LED Operating Mode On 10 Mbps operation PORTnLED1 100 Mbps operation 10 Mbps operation PORTnLED2 100 Mbps operation Autoneg enabled PORTnLED3 AUTOBLINK active 100 Mbps Link_OK AUTOBLINK inactive 100 Mbps Mode selected (Link_Enabled) N/A 10 Mbps Link_Enabled Link_OK, not Port_Partitioned Link_OK, Port_Partitioned Blink 20 ms Blink indicates Rcv_Activity2 N/A No Link_OK (Fast Blink)) Off Any other state Any other state Any other state Off via port LED Control Register Software Control 10 Mbps Link_OK Auto-neg disabled The collision and activity LEDs are on a Per Segment basis. Pulse stretchers are used to extend the on-time for the LEDs. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the oncycle, always follows. Collision and Activity LEDs Any The collision LEDs turn on for approximately 120 s when the LXT98x0 detects a collision on the segments. During the time that the LED is on, any additional collisions are ignored by the collision LED logic. The activity LEDs turns on for approximately 4 ms when the LXT98x0 detects any activity on the segments. During the time that the LED is on, any additional activity is ignored by the activity LED logic. Global Fault Any RPS Fault Manager Present Any port partitioned or RPS_Fault and RPS_ Present RPS_Fault and RPS_ Present N/A Mgr_Present N/A Not Mgr_Present Off via global LED Control Register N/A N/A Any other state 1. Refer to Table 14: LED Terms, which defines all key terms used in this section. 2. Receive activity is stretched to a 20 ms wide pulse. For every on-cycle of the stretched LEDs, an off-cycle, with the same period as the on-cycle, always follows. 3.8 IRB Operation The Inter-Repeater Backplane (IRB) allows multiple devices to operate as a single logical repeater, exchanging data and collision status information. Each segment on the LXT98x0 has its own complete, independent IRB. The backplanes use a combination of digital and analog signals as shown in Figure 9 on page 50. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 47 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 3.8.1 IRB Signal Types IRB signals can be characterized by the following connection types (For Stacking and Cascading connections, see Table 19 on page 50): * Local--connected between devices on the same board * Stack--connected between boards * Full--connected between devices in the same board and between boards. 3.8.2 IRB Isolation The ISOLATE outputs (IR10ISO and IR100ISO) are provided to control the enable pins of external bidirectional transceivers. In stacking applications, they can be used to isolate one board from the rest of the stack. Only one device can control these signals. The output states of these pins are controlled by the Isolate bits in the Repeater Configuration Register. 3.8.3 10 Mbps-Only Operation 3.8.3.1 MAC IRB Access The MACACTIVE pin allows an external MAC or other digital ASIC to interface directly to the 10 Mbps IRB. When the MACACTIVE pin is asserted, the LXT98x0 drives the IR10CFS and IR10CFSBP signals on behalf of the external device, allowing it to participate in collision detection functions. 3.8.3.2 Management Master Chain Arbitration This daisy chain is provided for correct statistics gathering in 10 Mbps cascaded configurations. In stacked applications, this daisy chain must be maintained through cascades. In stand-alone applications, or for the first device in a chain, the MMSTRIN input must be pulled Low for the management counters to work correctly. 3.8.4 LXT98x/91x/98x0 Compatibility The LXT98x0 devices feature low-power 3.3V design. The LXT98x and LXT91x devices operate at 5V and are incompatible with the LXT98x0 devices in cascades. The LXT98x0 devices, however, are backwards stackable with LXT98x and LXT91x repeaters. Note: Refer to "Inter-Repeater Backplane Compatibility" on page 71. 48 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 8. 100 Mbps IRB Connection IR100DEN 74LVT245 IR100DEN 74LVT245 IR100CLK IR100DV IR100DAT(4:0) IR100CLK IR100DV IR100DAT(4:0) LXT98x0 IR100COL IR100SNGL IR100CFS LXT98x0 (00) LXT98x0 (00) IR100CFSBP IR100COL IR100SNGL IR100CFS LXT98x0 HUB #1 Cascade HUB #2 Stack Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 49 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 9. IRB Block Diagram Digital IRB Signals Hub Board 1 MMSTR IN Analog IRB Signals MMSTR OUT / IN MMSTR OUT / IN MMSTR OUT '245 9880 ChipID = 0 9880 ChipID = 1 9880 ChipID = n ISOLATE HOLDCOL IRDEN MMSTR OUT Digital IRB Signals Analog IRB Signals MMSTR OUT / IN MMSTR OUT / IN 9880 ChipID = 1 HOLDCOL IRDEN 9880 ChipID = n MMSTR OUT MMSTR IN Hub Board 2 '245 ISOLATE 988 ChipID = 0 MMSTR OUT Digital IRB Signals Analog IRB Signals MMSTR OUT / IN MMSTR OUT / IN 9880 ChipID = 1 HOLDCOL IRDEN MMSTR OUT / IN 9880 ChipID = n MMSTR OUT MMSTR IN Hub Board n '245 9880 ChipID = 0 ISOLATE This diagram shows a single IRB. The LXT98xx actually has two independent IRBs, one per speed/segment. Digital IRB signals include IRnDAT, IRnCOL, IR10COLBP, IRnENA and IRnCLK. Local Analog IRB signal: IRnCFS. Inter-Board Analog IRB signal: IRnCFSBP. HOLDCOL, MMSTRIN, and MMSTROUT are used on the 10M IRB Only. Table 19. Cascading and Stacking Connections Signal Type Local Stack Full Special (xxISO) Connections Between Devices (Cascading) Connect all. For devices with ChipID 00, pull-up at each device and do not interconnect. Connect all. For devices with ChipID 00, leave open. For device with ChipID = 00, connect to buffer enable. Connections Between Boards (Stacking) Do not connect. Connect devices with ChipID = 00 between boards. Use one pull-up resistor per stack. Connect using buffers. Do not connect. 50 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 20. IRB Signal Details Name Pad Type Buffer 100 Mbps IRB Signals IR100DAT<4:0> IR100CLK IR100DV IR100CFS IR100CFSBP IR100COL IR100SNGL IR100DEN IR100ISO Digital Digital Digital, Open Drain Analog Analog Digital Digital Digital, Open Drain Digital Yes Yes Yes No No No No N/A1 N/A1 10 Mbps IRB Signals IR10DAT IR10CLK IR10ENA IR10CFS IR10CFSBP IR10COL IR10COLBP IR10DEN IR10ISO Digital, Open Drain Digital Digital, Open Drain Analog Analog Digital Digital Digital, Open Drain Digital Yes Yes Yes No No No No N/A N/A 1 1 Pull-up Connection Type No 1K 300 215, 1% 91, 1% No No 330 No Full Full Full Local Stack Local Local Local Special 330 No 330 215, 1% 330, 1% 330, 1% 330, 1% 330 No Full Full Full Local Stack Local Stack Local Special 1. Isolate and Driver Enable signals are provided to control an external bidirectional transceiver. 3.9 MII Port Operation The LXT98x0 MII ports allow direct connection with a MAC. The MII ports can operate at either 10 Mbps or 100 Mbps. Speed control is provided via MIIn_SPD. For 100 Mbps operation, set MIIn_SPD = 1. For 10 Mbps operation, set MIIn_SPD = 0. The LXT98x0 maintains the same statistics for the MIIs as it does for the 10/100 ports (except for isolate, partition, and illegal symbols). The LXT98x0 does not provide MDIO/MDC capability, as this is provided via the Serial Management Interface (SMI). 3.9.1 Preamble Handling When operating at 100 Mbps, the LXT98x0 passes the full 56 bits of preamble through before sending the SFD. When operating at 10 Mbps, the LXT98x0 sends data across the MII starting with the 8-bit SFD (no preamble bits). Note: MII Ports do not count partition, isolation, or symbol errors. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 51 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 10. LXT9880 MII Operation The two LXT98x0 MII ports act as the PHY side of the MII. An external MAC sends TX Data to the LXT98x0 to be repeated to the network. The LXT98x0 repeats network data to the MAC via the RX Data lines. LXT98x0 TP Ports Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 MII Ports Ports 1, 2 MIIn_TXD<3:0> MIIn_TXEN MIIn_TXER MIIn_TXCLK MIIn_RXCLK MIIn_RXD<3:0> MIIn_RXDV MIIn_RXER MIIn_CRS MIIn_COL 10/100 MAC 3.10 Serial Management I/F The high-speed Serial Management Interface (SMI) provides access to repeater MIB variables, RMON Statistics attributes and status and control information. A network manager accesses the interface through a simple serial communications controller such as an 8530 SCC. The SMI allows multiple LXT98x0 devices to be managed from one common bus. 3.10.1 SMI Signals The interface consists of a data input line (SRX), data output line (STX), and a clock (SERCLK). The interface operates on a simple command response model, with the network manager as the master and the LXT98x0 devices as slaves. Figure 11 is a simplified view of typical serial management interface architecture. Refer to Figure 23 on page 68 for circuit details. Note: Refer to Application Note 64, High-Speed Serial Management Interface, for additional information. Figure 11. Typical SMI Bus Architecture Network Management Serial Controller User Definable Partitioning LXT9880 LXT918 LXT918 RMON & Repeater MIB Support 52 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 3.10.1.1 Serial Clock SERCLK is a bidirectional pin; direction control is provided by the RECONFIG input. If RECONFIG is High, the LXT98x0 drives SERCLK at 625 kHz. If RECONFIG is Low, SERCLK is an input, between 0 and 2 MHz. The clock can be stopped after each operation, as long as an idle (at least 12 ones in a row) is transmitted first. 3.10.1.2 Serial Data I/O The serial data pins, SRX and STX, should be "logically" tied together using open-collector buffers. See Figure 23 on page 68. The SRX input is compared with the STX output. If a mismatch occurs, STX goes to a high impedance. STX is driven on the falling edge of SERCLK. SRX is sampled on the rising edge. 3.10.2 Read and Write Operations Data can be read or written in blocks. The LXT98x0 can read the full length field of consecutive counters with a single access. Block writes are limited to 2 long words. Normally the network manager directs read and write operations to a specific LXT98x0 device using a two-part address consisting of HubID and Chip Address. Note: In the Header Field, the Chip Address is defined by three bits. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. The LXT98x0 responds to an operation within 12 serial controller bit times. In the case of an error during a transfer, the LXT98x0 does not implement the requested command. 3.10.2.1 SMI Collision Handling Upon colliding with another packet, the LXT98x0 ceases transmission, based on the bit pattern of the colliding packets as shown in Figure 12. In the case of a collision, the driver who is sourcing a 0 wins. The LXT98x0 does not retry a response, unless it was an address arbitration packet. In addition, if an address arbitration packet jumps in during a request/response sequence, before the addressed LXT98x0 has responded, the addressed LXT98x0 aborts the requested operation. Note: The minimum time between packets must be at least 12 bit times with the data set to all ones. 3.10.2.2 SMI Address Match Indication The LXT98x0 SER_MATCH pin (see Figure 13) indicates detection of a serial command matching the device Hub ID. Broadcast commands also trigger the SER_MATCH output. Note that the initial HubID upon power-up or reset is the Broadcast (all ones) address. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 53 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 12. SMI Collision Handling Clk Data Data Data 1. Simultaneous Transmissions, Pkt 1 completes Transmit om falling CLK edge, sample on rising CLK edge. Pkt 1-Succeeds Pkt 2-Ceases, due to collision Pkt 3-Ceases, due to collision Figure 13. SMI Address Match Indication SERCLK SER_MATCH HUB ID CHIP ID, etc. SRX/STX 1. SER_MATCH can also occur at the end of a packet if a Start Flag is not seen but a Stop Flag is. This can occur only during unit installation or removal. 3.10.2.3 SMI Frame Format The SMI uses a simple frame format, shown in Figure 14. Table 21 describes the individual fields. Table 22 shows how the bits for the header field are stored in memory, assuming that they are transmitted LSB to MSB, low address to high address. Table 23 lists the command set and Table 24 provides a variety of typical packets. All frames begin and end with a simple flag consisting of "01111110". Multiple flags cause the LXT98x0 to ignore the packet. All fields are transmitted LSB first. Zero-bit stuffing is required if more than five 1s in a row appear in the header, data or CRC fields. In addition, all operations directed to the device must be followed by an idle (at least 12 ones in a row), and the first operation must be preceded with an idle. Note: The LXT98x0 uses the CCITT method of CRC (X16 + X12 + X5 +1). 54 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 21. SMI Message Fields Message Start or Stop Flag Hub ID Chip ID Command Length Address Description "01111110". Protocol requires zero insertion after any five consecutive "1"s in the data stream. Identifies board or sub-system. Assigned by one of two arbitration mechanisms at powerup. Identifies one of eight devices on a system. Assigned by 2 external pins on each device. The Most Significant Bit (MSB) = 0; the value of the other two bits is set by pins. Identifies the particular operation being performed (see Table 23) Specifies number of registers to be transferred (1 to 127). Maximum is 2 per write, 127 per read. Specifies address of register or register block to be transferred. Figure 14. Serial Management Frame Format Idle Start Flag Header Data (0-508 bytes) CRC (2 bytes) Stop Flag Idle Header Content: Hub ID 5 bits Chip Add 3 bits Cmd 5 bits Length 7 bits Address 12 bits Table 22. SMI Header Storage MSB Addr 11 Increasing Address Addr 3 Length 2 Chip Address Bit 2 (set to 0) Addr 10 Addr 2 Length 1 Chip Address Bit 1 Addr 9 Addr 1 Length 0 Chip Address Bit 0 Addr 8 Addr 0 CMD 4 Addr 7 Length 6 Cmd 3 Addr 6 Length 5 Cmd 2 Addr 5 Length 4 Cmd 1 LSB Addr 4 Length 3 Cmd 0 HubID 4 HubID 3 HubID 2 HubID 1 HubID 0 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 55 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 23. SMI Command Set Command Value Name Usage Normally Sent By Description Used to set a register or group of registers. The minimum write size is 1 long word. The maximum block write is 2 long words. This size was chosen so that software may write an entire Ethernet address in one serial packet. Used to get complete sets of counter information for either a port or a segment. The minimum read size is 32 bits (one long word). The maximum block read is 127 long words. The acknowledge for this instruction is the actual returned data. For Hub ID (Arb Method 1): The LXT98x0 repeats this command periodically until it is assigned a Hub ID. Once assigned, the command is discontinued. Notifies system of configuration change (hot swap). Requests new arbitration phase. Re-starts arbitration. Assigns all new addresses. Assigns Hub ID to device with ARBIN = 0 and ARBOUT = 1 Used to determine stacking order or assign address. Commands specific device to set ARBOUT= 1. This command can apply to either a single LXT98x0 (via direct addressing), or every LXT98x0 through the use of the broadcast address. Used to determine stacking order or assign address. Commands specific device to set ARBOUT = 0. This command can apply to either a single LXT98x0 (via direct addressing), or every LXT98x0 through the use of the broadcast address. Asks device to send contents of device revision register. This command applies to only a single LXT98x0 at a time. When given, the command causes the chip to retrieve its type and revision code data (hard coded for a given device) and provide it to the serial controller for transmission back to the requesting manager. The acknowledge for this type of packet is the actual returned data. This command can also be used for `ping' operations. 18 (Hex) Write Normal Ops Network Mgr 04 (Hex) Read Normal Ops Network Mgr 08 (Hex) Request ID Arbitration LXT98x0 00 (Hex) 10 (Hex) 14 (Hex) ConfigChg Re-arbitrate Assign HubID Arbitration Arbitration Chain Arbitration LXT98x0 Network Mgr Network Mgr 0C (Hex) Set Arbout to 1 Chain Arbitration Network Mgr 1C (Hex) Set Arbout to 0 Chain Arbitration Network Mgr 02 (Hex) DevID Config Network Mgr 56 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 24. Typical Serial Management Packets Contents of Fields in Serial Management Packet Message Hub ID Write 1, 2 Read Request 1, 3, 4 3 Chip Address 5 User defined User defined 000 Command 18 Hex 04 Hex 04 Hex Length 01 or 02 Hex 01 to 7F Hex 01 to 7F Hex Address User defined User defined User defined Data User defined Null Data values Formatted per Table 89 on page 115 and Table 90 on page 116 Hub ID (LSB) and 27 0s Null Null PROM ID Null PROM ID Null Device type/ revision User defined User defined 00000 Read Response Assign Hub ID (Arb Method 1) 11111 011 18 Hex 02 Hex 188 Hex Assign Hub ID (Arb Method 2) Set Arbout to 0 Set Arbout to 1 Arb Request Resend Arbitration Resend Arbitration Response Device type/ Revision code Device/Revision Response 11111 User defined User defined 00000 11111 00000 User defined 00000 011 User defined User defined 000 011 000 User defined 000 14 Hex 1C Hex 0C Hex 08 Hex 10 Hex 08 Hex 02 Hex 02 Hex 01 Hex 00 Hex 00 Hex 02 Hex 00 Hex 02 Hex 01 Hex 01 Hex 000 Hex 000 Hex 000 Hex 190 Hex 000 Hex 190 Hex 000 Hex 13C Hex 1. Other than checking that the top 3 bits of the address equals 000, the LXT98x0 does not check if the user writes or reads past the highest location. There are no adverse effects for writing or reading locations above the specified range. 2. If the user performs a write operation of length 1 or 2 and does not send a data field, the LXT98x0 writes junk into the specified registers. This constitutes an invalid command. 3. If the user reads past the highest location of the LXT98x0, all those locations reads back 0s. 4. If a read operation is performed with a length of 0, the LXT98x0 does not respond. 5. ChipID is defined by 3 bits, with the MSB = 0; value of the other two bits is set by pins. 3.10.3 Address Assignment Methods Each device has a two part address, consisting of a HubID and a Chip Address (See Figure 14 on page 55). The Chip Address is assigned by the input pins CHIPID<1:0>. (The Most Significant Bit [MSB] = 0.) The manager assigns the HubID. Each LXT98x0 on a particular board has the same HubID. The HubID is assigned through one of two arbitration mechanisms as shown in Figure 15. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 57 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 15. Address Arbitration Mechanisms Network Manager SRX/STX EPROM Mechanism for Address Arbitration Network Manager SRX/STX ARBOUT Chain Mechanism for Address Arbitration PROMDTI/O LXT98x0 SRX/STX PROMDTI/O LXT98x0 SRX/STX Serial EPROM LXT98x0 0 ARBIN ARBOUT 1 SRX/STX LXT98x0 ARBIN 0 ARBOUT SRX/STX Hub Board 1 Hub Board 1 Hub Board 2 SRX/STX LXT980 PROMDTI/O SRX/STX LXT980 PROMDTI/O Serial EPROM 0 SRX/STX ARBIN ARBOUT 1 LXT98x0 SRX/STX ARBIN ARBOUT 1 LXT98x0 Hub Board 2 Serial I/F to Next Module Serial I/F to Next Module ARBI/O Chain to Next Module 3.10.3.1 Chain Arbitration Mechanism The chain method is the easiest and requires no serial PROM. The ARBSELECT pin on all devices must be set to 1. When constructing the stack, the designer creates a daisy chain by tying the ARBOUT pin of each LXT98x0 to the ARBIN pin of the following LXT98x0. The manager is at the top of the stack and controls the ARBIN for the first LXT98x0. The manager progressively assigns Hub IDs using the Assign Hub ID (Arb Method 2) and Set ARBOUT to ZERO commands. The manager initially sets its ARBOUT (first LXT98x0's ARBIN) to zero. Since the Assign Hub ID (Arb Method 2) command only works on the LXT98x0 with ARBIN of 0 and an ARBOUT of 1, the first LXT98x0 can be assigned an address. After the first LXT98x0 has been assigned an address, it can uniquely be told to switch its ARBOUT to zero. This creates the (01) condition on the next LXT98x0 in the line. This LXT98x0 is then assigned an address and the process continues until all chips have been assigned a unique address. Note: It is recommended that HubIDs match in any given hub. The manager can verify that a hub is still present by performing DEVICE ID commands. If a change of configuration is detected, the manager can perform a broadcast write to return each hub's ARBOUT to 1, and then re-perform the address assignment process. When using the chain arbitration method, set up the daisy chain so the device with ChipID = 00 is the first device in the board that the chain passes through. When assigning IDs, the `1st in Chain' bit in the device revision register (refer to Table 77 on page 111) can be used to determine when a new board has been encountered. 3.10.3.2 PROM Arbitration Mechanism This mechanism requires one serial PROM with a unique 48-bit ID in each board. This ID can consist of serial number, date/week/year of manufacture, etc. The ARBSELECT pin must be set to 0. At power-up, the device with ChipID = 00 reads a 48-bit ID from the PROM. All other devices 58 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 on the board listen in and record the ID. The device with ChipID = 00 then transmits Arbitration Request messages on the SMI every 2-3 ms. The request messages from two boards may collide. If this happens, a resolution scheme ensures that only one message is transmitted. The network manager must respond to each request with a message that includes the 48-bit ID and the HubID. All devices hear this message, but only those matching the 48-bit ID receive the HubID as their own. Once a HubID is assigned to a hub, that hub ceases requesting a HubID. This process continues until all hubs are assigned an ID. Should a hub power off and back on, the hub rerequests an ID, which the manager provides. An address arbitration packet is selected over normal requests. 3.10.3.3 Address Re-Arbitration There are two mechanisms for address re-arbitration following a configuration change, such as a hot-swap of a board: * Manual Re-arbitration. If the LXT98x0 detects a Low-to-High transition on RECONFIG, or if RECONFIG is High at power-up, it sends out a "Configuration Change" message (Start Flag with all 0s) on the bus. The network manager can use this message to detect that re-arbitration is required. * Network Manager. The network manager can detect or re-start arbitration at any time by sending the "Re-arbitrate" command. 3.10.4 Interrupt Functions The LXT98x0 provides a single open-collector pin for external interrupt signalling. Several different interrupt conditions may be reported. The Interrupt Status Register (see Table 86) identifies the specific interrupt condition. The Interrupt Mask Register (see Table 87 on page 115) allows specific interrupts to be masked. Interrupts may be cleared in two ways, depending on the status of bit 11 in the repeater configuration register. 3.11 Serial PROM Interface The serial PROM interface allows the vendor to load in optional information unique to each board. Items such as serial number or manufacture date can be placed in the serial PROM which can also be used in the address arbitration process. Each board must contain a unique set of information. Additionally, only 1 serial PROM is required per board, they are not required per chip. The LXT98x0 reads in the first 48 bits (three 16-bit words) from the PROM and stores them in a register. This read occurs only on power-up. Only the LXT98x0 with a ChipID of 00 drives the serial PROM control lines; all other LXT98x0s "listen" to the data and clock lines. The first bit into the LXT98x0 from this interface corresponds to bit 47. The serial PROM shifts out the most significant bit (15) of the word first (the PROM must be auto-incrementing). Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 59 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 16. Optional R/W Serial PROM Interface CLK DTOUT CS The LXT98x0 drives outgoing data on the falling clock edge. The LXT98x0 samples incoming data on the rising clock edge. 3.12 Serial Configuration Interface The Serial Configuration Interface allows the user to load system-specific information (board type, plug-in cards, status, etc.) into the Repeater Configuration Register (see Table 75 on page 109). This register may be read remotely through the Serial Management Interface (SMI). The Serial Configuration Interface mode (Repeater Configuration Register bit 14 = 1) allows the collection of up to 8 bits of board data, compared to the CONFIG[1:0] 2-bit mode (bit 14 = 0). See Table 75 on page 109. For Serial Configuration Interface mode = 1, an external `165 device is used to perform a parallelto-serial conversion of the board data (see Figure 17). These board data bits are shifted into the LXT98x0 each time the Repeater Serial Configuration register is read. CFG_DT is clocked into the LXT98x0 relative to the rising edge of CFG_CLK as shown in Figure 18. Also note the register bit positions versus the `165 parallel input positions. The CFG_CLK pin is shared with LED_CLK. For reading the Repeater Serial Configuration Register, the configuration bits are reloaded into the LXT98x0. The shared functionality of the clock (configuration and serial LED), causes an unscheduled serial LED update. All 32 clock cycles occur with only the first 8 bits clocked into the Repeater Serial Configuration Register. See Table 76 on page 110. 60 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 17. Serial Configuration Interface Parallel Config. Data ABCDEFGH SER QH SH/LD CLK `165 CFG_DT CFG_LD CFG_CLK LXT98x0 Figure 18. Serial Configuration Interface Signaling CFG_LD CFG_CLK 100 ns / 10 MHz CFG_DT H = b0 G = b1 F = b2 E= b3 D = b4 C = b5 B = b6 A = b7 4.0 4.1 Application Information General Design Guidelines Following generally accepted design practices is essential to minimize noise levels on power and ground planes. Up to 50 mV of noise is considered acceptable. 50 to 80 mV of noise is considered marginal. High-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: * Fill in unused areas of the signal planes with solid copper. Attach them with vias to a VCC or ground plane that is not located adjacent to the signal layer. * Use ample bulk and decoupling capacitors throughout the design (a .01 F value is recommended for decoupling caps). * * * * * Provide ample power and ground planes. Provide termination on all high-speed switching signals and clock lines. Provide impedance matching on long traces to prevent reflections. Route high-speed signals next to a continuous, unbroken ground plane. Filter and shield DC-DC converters, oscillators, etc. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 61 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management * Do not route any digital signals between the LXT98x0 and the RJ-45 connectors at the edge of the board. * Do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. Use this area for chassis ground, or leave it void. 4.2 Typical Applications Figure 19 and Figure 20 are simplified block diagrams showing typical applications. Figure 21 through Figure 26 show application circuitry details. Figure 19. 8-Port Managed 10/100 Stackable Repeater Serial Comm Controller 74LVT245 Bridge 10M MAC 100M MAC 74LVT245 MII 1 Serial Port MII 2 10M IRB TP Ports 100M IRB 8 10/100 Ports Figure 20. 32-Port Managed 10/100 Repeater Serial Comm Controller RMON (Optional 10M or 100M MAC 74LVT245 Bridge 10M MAC 100M MAC MII 1 Serial Port MII 2 10M IRB TP Ports 100M IRB MII 1 Serial Port MII 2 10M IRB TP Ports 100M IRB MII 1 Serial Port MII 2 10M IRB TP Ports 100M IRB 74LVT245 MII 1 Serial Port MII 2 10M IRB TP Ports 100M IRB 32 10/100 Ports 62 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 4.3 4.3.1 Application Circuitry Power and Ground 4.3.1.1 Supply Filtering Power supply ripple and digital switching noise on the VCC plane causes EMI and degrades line performance. Predicting a design's performance is difficult, although certain factors greatly increase the risks: * Poorly-regulated or over-burdened power supplies. * Wide data busses (>32-bits) running at a high clock rate. * DC-to-DC converters. Many of these issues can be improved by following good general design guidelines. In addition, Intel recommends filtering between the power supply and the analog VCC pins of the LXT98x0. Filtering has two benefits. First, it keeps digital switching noise out of the analog circuitry inside the LXT98x0, which helps line performance. Second, if the VCC planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing EMI. The VCC plane should be divided into two sections. The digital section supplies power to the digital VCC pins and to the external components. The analog section supplies power to VCCR and VCCT pins of the LXT98x0. The break between the two planes should run under the device. In designs with more than one LXT98x0, use a single continuous analog VCC plane to supply them all. The digital and analog VCC planes should be joined at one or more points by ferrite beads. The beads should produce at least a 100 impedance at 100 MHz. The beads should be placed so current flows evenly. The maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. Each LXT98x0 draws a maximum of 1000mA from the analog supply so beads rated at 1500mA maximum should be used. A bulk cap (2.2 -10 F) should be placed on each side of each ferrite bead to ground to stop switching noise from traveling through the ferrite. In addition, a high-frequency bypass cap (.01f) should be placed near each analog VCC pin to ground. 4.3.1.2 Ground Noise The best approach to minimize ground noise is strict use of good general design guidelines and by filtering the VCC plane. 4.3.1.3 Power and Ground Plane Layout Considerations The power and ground planes should be laid out carefully. The following guidelines are recommended: * Follow the guidelines in the Application Note 113 (LXT98x0 Design and Layout Guide) for locating the split between the digital and analog VCC planes. * Keep the digital VCC plane away from the TPOP/N and TPIP/N signals, magnetics, and RJ-45 connectors. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 63 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management * Place the layers so the TPOP/N and TPIP/N signals are routed near or next to the ground plane. For EMI, it is more important to shield TPOP/N than TPIP/N. 4.3.1.4 Chassis Ground For ESD protection, create a separate chassis ground. For isolation, encircle the board and place a "moat" around the signal ground plane to separate signal ground from chassis ground. Chassis ground should extend from the RJ-45 connectors to the magnetics, and can be used to terminate unused signal pairs (`Bob Smith' termination). In single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kV isolation capacitor. In multipoint grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kV isolation to the Bob Smith termination. 4.3.1.5 The RBIAS Pin The LXT98x0 requires a 22.1 k, 1% resistor directly connected between the RBIAS pin and ground. Place the RBIAS resistor as close to the RBIAS pin as possible. Run an etch directly from the pin to the resistor, sink the other side of the resistor, and surround the RBIAS trace with a filtered ground. Do not run high-speed signals next to RBIAS. 64 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 21. Power and Ground Connections To Output Magnetics Centertap LXT9880 VCCT .1F .01F GND VCC .1F .01F GND 22.1 k 1% RBIAS GND VCCR .1F .01F 10F GND Analog Supply Plane + Ferrite Beads Digital Supply Plane 10F VCC 0.1F +3.3V GND 4.3.2 MII Terminations The LXT98x0 MIIs have high output impedance (250-350). To minimize reflections, serial termination resistors are recommended on all MII signals, especially with designs with long traces (>3 inches). Place the resistor as close to the device as possible. Use a software trace termination package to select an optimal resistance value for the specific trace. Proper value = nominal trace impedance minus 13. If a software package cannot be used and nominal trace impedance is not known, use 55. 4.3.3 Twisted-Pair Interface The LXT98x0 transmitter uses standard 1:1 magnetics for both receive and transmit. Nonetheless, system designers should take precautions to minimize parasitic shunt capacitance and meet return loss specifications. These steps include: Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 65 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management * Place magnetics as close as possible to the LXT98x0. * Keep transmit pair traces short. * Do not route transmit pair adjacent to a ground plane. Eliminate planes under the transmit traces completely. Otherwise, keep planes 3-4 layers away. * Improve EMI performance by filtering the output center tap supply. A single ferrite bead may be used in the center tap supply to all ports. A ferrite bead with a total maximum current rating of 1.5Amp is recommended. * Place 270pF 5% capacitors at TPIP and TPIN to improve signal-to-noise immunity at the receiver, especially for long line lengths. In addition, follow all the standard guidelines for a twisted-pair interface: * * * * * Route the signal pairs differentially, close together. Allow nothing to come between them. Keep distances as short as possible; both traces should have the same length. Avoid vias and layer changes. Keep the transmit and receive pairs apart to avoid cross-talk. To provide maximum isolation, place entire receive termination network on one side and transmit on the other side of the PCB. capacitors. * Bypass common-mode noise to ground on the in-board side of the magnetics using 0.01F * Keep termination circuits grouped closely together and on the same side of the board. * Always put termination circuits close to the source end of any circuit. 4.3.3.1 Magnetics Information The LXT98x0 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. The transformer isolation voltage should be rated at 2 kV to protect the circuitry from static voltages across the connectors and cables. Refer to Table 25 for magnetics specifications. Table 25. LXT98x0 Magnetics Specifications Parameter Rx turns ratio Tx turns ratio Insertion loss Primary inductance Transformer isolation Differential to common mode rejection Min - - 0.0 350 - -40 -35 -16 Return Loss - standard -10 - dB 80 MHz Nom 1:1 1:1 - - 2 - - - Max - - 1.1 - - Units - - dB H kV dB dB dB .1 to 60 MHz 60 to 100 MHz 30 MHz 80 MHz Test Condition 4.3.4 Clock A stable, external 25 MHz system clock source (CMOS) is required. See Table 26. 66 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 26. Oscillator Manufacturers Manufacturer CTS Epson America Part Number MXO45 / 45LV SG-636 Series 25 MHz 25 MHz Frequency Figure 22. Typical Twisted-Pair Port Interface and Power Supply Filtering LXT98x3 270 pF 5% 50 1% TPFIP TPIP 0.01 F 5% 1:1 RJ45 1 2 3 50 1% TPIN 270 pF 5% 50 1:1 50 4 TPOP 50 5 6 50 .01 F 7 50 0.001F 2kV 0.001F 2kV 0.001F 2kV 50 8 TPON VCCT 0.1F .01F GND Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 To Twisted-Pair Network 67 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 4.3.5 SMI and PROM Circuits Figure 23. Typical Serial Management Interface Connections SRX 74xx05 VCC STX 1. When not transmitting STX goes to 1, hence open collector and no drive. Figure 24. Serial Controller Connection Showing PAL CLK RxDA TxDA RTxCA CTSA RTSA PAL OC Driver Serial Line 8530 1. PAL is used to detect collisions and gate (cease) transmission. The PAL notifies the 8530 to abort the current transmission via the CTS bit, which is then cleared by the RTS bit. 68 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 25. Serial PROM Interface 93CS46 PROM_DTOUT PROM_DTIN PROM_CLK PROM_CS PROM_DTIN PROM_CLK LXT98x0 (ID = 00) LXT98x0 (ID 00) Figure 26. Typical Reset Circuit VCC R2 D C '14 R1 1. t(CR1 > Power Supply Ramp Up Time. R2 discharges C when supply goes away. The `14 is needed for multiple LXT98x0 devices. 4.3.6 LED Circuits 4.3.6.1 Direct Drive LEDs Each Direct Drive LED has a corresponding open-drain pin. The LEDs are connected, via a current limiting resistor, to a positive voltage rail. The LEDs are turned on when the output pin drives Low. The open-drain LED pins are 5V tolerant, allowing use of either a 3.3V or 5V rail. A 5V rail eases LED component selection by allowing more common, high forward voltage LEDs to be used. Refer to Figure 27 for a circuit illustration. 4.3.6.2 LED Pins Multiplexed with Configuration Inputs Some static configuration inputs are multiplexed with LED pins to reduce the LXT98x0 pin count. These LED pins are configured by current sinking (open- drain output) and sourcing (open-source output). If the LED pin sinks the LED current, the configuration value is `1'. If LED pin sources Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 69 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management the current, the configuration value is a `0'. The LXT98x0 detects the configuration value following reset and then selects the appropriate output drive circuit (open drain or source). If the LED function of a multiplexed configuration pin is not used, tie the pin to Ground or Vcc via a 100-500 k resistor to set the configuration value. Multiple LED configuration pins can be tied off with a single resistor to set them all to the same value. Refer to Figure 27 for a circuit illustration. For configuration values of `1', a 3.3V or a 5V rail can be used to drive the LEDs (to ease LED selection as with Direct Drive LEDs). For configuration values of `0', external buffering is used when 5V LED driving is desired. (This buffering could be as simple as a single transistor.) As an alternative, use the copies of the multiplexed LED data found on the LED serial interface. If a 5V tolerant serial-to-parallel device is used for the LED serial interface, 5V LED driving is achieved (see "Serial LEDs" on page 70). Figure 27. LED Circuits - Direct Drive & Multiplexed Configuration Inputs VLED VLED R VLED R R Vcc R Vcc Rb 100k Inside Outside IC IC Inside Outside IC IC Inside Outside IC IC Inside Outside IC IC Direct Drive Vcc = 3.3 Volts +/- 5% VLED = 3.3 to 5 Volts +/- 5% Multiplexed Configuration = `1' Multiplexed Configuration = `0' Multiplexed with Transistor Buffer Configuration = `0' 4.3.6.3 Serial LEDs The LXT98x0 provides a serial interface to support additional LED options. Standard shift registers, either 74X595s (8-bit Serial-to-Parallel with Output Registers) or 74X164s (8-bit S/P without registers) can be used to drive these additional LEDs. Collision10/100 and Activity10/100 status indications are provided on multiplexed configuration pins and duplicated on the serial port. The LED serial interface consists of three outputs: clock (LEDCLK), parallel latch clock (LEDLAT), and output data (LEDDAT). The parallel latch clock is used only with the 74X595 implementation. Refer to Figure 28 for an illustration of the LED serial interface circuit. Potentially, 30 LEDs can be driven by the LED serial interface via 4 S/P devices. The S/P serial output is connected to the serial input of the first serial input device. To expand the chain, connect the last serial output to serial input of next serial interface device. Serial LED data is output in the anticipated priority order, from least likely to most likely to be used: * Unused `595/`164 parallel outputs * MII Ports - LED1, 2, 3 70 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 * Miscellaneous LEDs (Repeat of Collision10/100, Manager Present, Repeat of Activity10/100, Global Fault, RPS Fault) * ACTGLED10 * ACTGLED100 This allows the user to leave off devices in the serial-to-parallel chain if the LEDs associated with that condition aren't desired. Refer to Figure 7 on page 41 which illustrates the LED serial interface port signalling and Table 12 on page 41 which documents the Serial LED Stream. If the 8 bit serial bus Configuration Mode is selected (See "Serial Configuration Interface" on page 60.), unscheduled (less than 122 s apart) LED Serial Port cycles occur each time the Repeater Serial Configuration register is read. If the 74x164 buffer is used, flicker is minimized by design so that it is not noticeable to the eye. The LED outputs may change momentarily. Figure 28. Serial LED Circuit LXT98x0 74X595 LEDDAT LEDLAT LEDCLK SER RCLK SRCLK Qa Qb . . . Qh Qh` LED cct. LED cct. . . . LXT98x0 VLED 74X164 ACTGLED100 LEDDAT LEDCLK A B CLK Qa Qb . . . Qh LED cct. LED cct. . . . VLED ACTGLED100 LED cct. LED cct. 74X595 SER RCLK SRCLK Qa Qb . . . Qh Qh` ACTGLED10 LED cct. LED cct. . . . 74X164 . . . ACTGLED10 A B CLK Qa Qb . . . Qh LED cct. LED cct. VLED side R LED cct. LED cct. . . . Up to 2 more `595s/8xLEDs Up to 2 more `164s/8xLEDs . . . LED cct. VLED = 3.3 to 5 Volts +/- 5% 4.4 Inter-Repeater Backplane Compatibility The Inter-repeater Backplane (IRB) comprises two parts: * Local--the backplane between cascaded devices on the same board. * Stack--the backplane between multiple boards. Each of these backplanes consists of both analog and digital signals. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 71 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 4.4.1 Local Backplane--3.3V Only The LXT98x0 local backplane operates at 3.3V only. LXT98x and LXT91x devices operate at 5V. LXT98x0 devices are, therefore, not cascadable with LXT98x and LXT91x devices. Note: Do not mix LXT98x0 with either LXT98x or LXT91x devices on the local backplanes. 4.4.2 Stack Backplane--3.3V or 5V The LXT98x0 stack backplanes can be configured to be either 3.3V or 5V. COMP_SEL (Pin 39), a special input pin, selects between the two voltage modes, depending on whether 3.3V or 5V is applied. 3.3V-Only Stacks For 5V Backwards Stackability Apply 3.3V to COMP_SEL, IR100CFSBP, IR10CFSBP, and IR10COLBP for LXT98x0 backplane operation Apply 5V to COMP_SEL, IR100CFSBP, IR10CFSBP, and IR10COLBP for LXT98x and LXT91x backplane operation. With either mode (3.3V or 5V), COMP_SEL draws less than 3 mA. Note: 1. The external pull-up resistor values remain the same, regardless of 3.3V or 5V backplane operation. 2. The recommended digital signal external buffer has been changed to 74LVT245 for the LXT98x0. 4.4.2.1 3.3V and 5.0V Stacking Boards Cannot Be Mixed 3.3V Operation Boards designed for 3.3V backplane operation should only be stacked with other 3.3V boards. Existing LXT98x or LXT91x based designs cannot operate in 3.3V. Incompatible Stacking Configurations The following stacking configurations are incompatible: * A LXT98x0-based board configured for 3.3V backplane operation and LXT98x or LXT91x based boards (5V only). * A LXT98x0-based board configured for 3.3V backplane operation and a LXT98x0-based board configured for 5V backplane operation. Note: Stacking boards designed for 3.3V backplane operation with boards designed for 5V backplane operation causes network errors. 5V Operation Boards designed for 5V backplane operation should only be stacked with other 5V boards: * LXT98x or LXT91x-based designs. * LXT98x0 designs configured for 5V backplane operation. 72 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 The configuration input must be connected to 5V for compatibility with LXT98x or LXT91x-based designs. The 5V can be supplied from the stacking cable, or a 5V source must exist within the board itself. Note: Stacking boards designed for 5V backplane operation with boards designed for 3.3V backplane operation causes network errors. Figure 29. 100 Mbps Backplane Connection between LXT98x and LXT98x0 IR100DEN IR100DEN Buffer IR100COL Buffer IR100CLK IR100DV IR100DAT(4:0) IR100CLK IR100DV IR100DAT(4:0) IR100COL 98x 5V IR100SNGL IR100CFS 98x (000) 98x0 (00) IR100CFSBP IR100SNGL IR100CFS 98x0 5V HUB #1 HUB #2 1. The LXT98x and LXT98x0 devices can share the same Inter-Repeater Backplane so long as the proper backplane buffers are used. Configuration is set to 5V. 2. For LXT98x, LXT91x: The buffer should be the 74ABT245. For LXT98x0: In the 5V tolerant backplane, the buffer can be either 74ABT245 or 74LVT245 3. Layout follows the same pattern for 10 Mbps operation. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 73 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 30. Typical 100 Mbps IRB Implementation Stack or Segment Connector IR100CLKBP IR100DATBP IR100DVBP\ 91 1%* '245 A +3.3V +3.3V +3.3V 215 1% 300 IR100DAT <4:0> IR100DV\ IR100DEN\ IR100COL\ IR100CFS\ IR100SNGL IR100CFSBP\ +3.3V 91 91 2 IR100CLK B IR100DAT IR100DV\ DIR ISOLATE ENA IR100DEN\ 330 1 1 IR100CFSBP\ COMP_SEL LXT98x0 Chip ID 00 LXT98x0 Chip ID 01 LXT98x0 Chip ID 10 1. In stacked configurations, all devices with ChipID = 00 are tied together at IR100CFSBP. The entire stack must be pulled up by only one resistor per signal. Pull-up resistor is installed on one board only. (Board selection is application specific.) 2. All devices with ChipID 00 require individual pull-up resistors at IR100CFSBP. Figure 31. Typical 10 Mbps IRB Implementation Stack or Segment Connector IR10CLKBP IR10DATBP IR10ENABP\ 330 1% '245 A IR10CLK B IR10DAT IR10ENA\ +3.3V 330 215 1% +3.3V 330 IR10CLK IR10DAT IR10ENA\ IR10DEN\ IR10COL\ IR10CFS\ HOLDCOL 330 330 2 +3.3V 330 330 IR10COLBP\ IR10CFSBP\ IR10DEN\ DIR 330 ISOLATE ENA 1% IR10COLBP\ IR10CFSBP\ 1 COMP_SEL LXT98xx Chip ID 00 LXT98xx Chip ID 01 LXT98xx Chip ID 10 1. In stacked configurations, all devices with ChipID = 00 are tied together at IR100CFSBP. The entire stack must be pulled up by only one resistor per signal. Pull-up resistor is installed on one board only. (Board selection is application specific. 2. All devices with ChipID 00 require individual pull-up resistors at IR100CFSBP. 74 IR10COLBP\ IR10CFSBP\ IR100CFSBP\ Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 5.0 Note: Test Specifications Table 27 through Table 44 and Figure 32 through Figure 41 represent the target specifications of the LXT98x0 and are subject to change. Final values will be guaranteed by test except, where noted, by design. The minimum and maximum values listed in Table 29 through Table 44 will be guaranteed over the recommended operating conditions specified in Table 28. Table 27. Absolute Maximum Ratings Parameter Supply voltage Storage temperature Symbol VCC TST Min -0.3 -65 Max 4.0 +150 Units V C Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 28. Operating Conditions Parameter Sym VCC Recommended supply voltage VCCR VCCT Recommended operating temperature Ambient Commercial Temperature Range Case Ambient Extended Temperature Range Case Power consumption 8 ports active 6 ports active TOPC PC PC -18 - - - - - +120 3.03 2.50 C W W TOPC TOPA 0 -40 - - 115 +85 C C TOPA 0 - 70 C Min 3.15 3.15 3.15 Typ1 3.3 3.3 3.3 Max 3.45 3.45 3.45 Units V V V 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. Table 29. Input System Clock1 Requirements Parameter2 Frequency Frequency Tolerance Duty Cycle Sym - - - Min - - 40 Typ3 25 - - Max - 100 60 Units MHz PPM % - - - Test Conditions 1. The system clock is CLK25 (Pin 54). 2. These requirements apply to the external clock supplied to the LXT98x0, not to LXT98x0 test specifications. 3. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 75 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 30. I/O Electrical Characteristics Parameter Sym Min - Input Low voltage VIL - - 2.0 Input High voltage VIH 70 VCC - 1.0 Hysteresis voltage Output Low voltage Output Low voltage (LED) Output High voltage Input Low current Input High current Output rise / fall time - VOL VOLL VOH IIL IIH TRF 1.0 - - 2.2 -100 - - Typ1 - - - - - - - - - - - - 3 Max 0.8 30 1.0 - - - - 0.4 1.0 - - 100 10 V % VCC V V V V V A A ns Units V % VCC Test Conditions TTL inputs CMOS inputs 2 Schmitt triggers 3 TTL inputs CMOS inputs 2 Schmitt triggers 3 Schmitt triggers 3 IOL = 1.6 mA IOLL = 10 mA IOH = 40 A - - CL = 15 pF 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Does not apply to IRB pins. Refer to Table 31 and Table 32 for IRB I/O characteristics. 3. Applies to RESET, CLK25, IR100SNGL, IR100COL, IR100DATn, IR100CLK, and IR10CLK pins. Table 31. 100 Mbps IRB Electrical Characteristics Parameter Output Low voltage Output rise or fall time Input High voltage Sym VOL TRF VIH VCC - 1.0 - Input Low voltage Hysteresis voltage 3.3V Operation single drive IR100CFS current collision single drive IR100CFSBP current collision IR100CFS/BP voltage 5.0V Operation 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 resistors provide greater noise immunity. Systems using 91 resistors are backwards stackable with systems using 100 resistors. single drive collision - - - - - - 31.8 1.83 0.4 - - - mA V V - - - - 13.5 16.1 - - mA mA - - 6.8 - mA RL = 215 RL = 215 RL = 91 2 RL = 91 2 - - VIL - - 1.0 - - 1.0 - V IR100CLK (Schmitt trigger) IR100CLK (Schmitt trigger) - - - 2.0 V V IR100CLK (Schmitt trigger) CMOS inputs Min - - VCC - 2.0 Typ1 .3 4 - Max .7 10 - Units V ns V Test Conditions RL = 330 CL = 15 pF CMOS inputs 76 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 31. 100 Mbps IRB Electrical Characteristics (Continued) Parameter single drive IR100CFS current collision single drive IR100CFSBP current collision single drive IR100CFS/BP voltage collision - - 0.6 - V - 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 resistors provide greater noise immunity. Systems using 91 resistors are backwards stackable with systems using 100 resistors. - - - - 42 2.8 - - mA V - - - - N/A 24.2 - - mA mA Sym - Min - Typ1 N/A Max - Units mA Test Conditions RL = 215 RL = 215 RL = 91 2 RL = 91 2 - Table 32. 10 Mbps IRB Electrical Characteristics Parameter Output Low voltage Output rise or fall time Input High voltage Sym VOL TRF VIH VCC - 2.0 - Input Low voltage Hysteresis voltage 3.3V Operation single drive IR10CFS current collision single drive IR10CFSBP current collision single drive IR10CFS/BP voltage collision 5.0V Operation single drive IR10CFS current collision single drive IR10CFSBP current collision single drive IR10CFS/BP voltage collision - 0.4 0.6 0.8 V - 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. - - - 1.9 13.5 2.8 - 3.2 mA V - - - - N/A 7.0 - - mA mA - - N/A - mA RL = 215 RL = 215 RL = 330 RL = 330 - - 0.2 0.4 0.6 V - - - - - - - - 1.3 13.5 4.5 8.8 1.83 - - - 2.4 mA mA mA V - - 6.8 - mA RL = 215 RL = 215 RL = 330 RL = 330 - VIL - - 0.5 - - 1.0 - V V IR10CLK (Schmitt trigger) IR10CLK (Schmitt trigger) - - - 2.0 V V IR10CLK (Schmitt trigger) CMOS inputs Min 0 - VCC - 2.0 Typ1 .1 4 - Max .4 10 - Units V ns V Test Conditions RL = 330 CL = 15 pF CMOS inputs Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 77 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 33. 100BASE-TX Transceiver Electrical Characteristics Parameter Peak differential output voltage (single ended) Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Sym VP - Trf Trfs - Vo Min 0.95 98 3.0 - - - Typ1 1.0 - - - - - Max 1.05 102 5.0 0.5 +/- 0.5 5 Units V % ns ns ns % Test Conditions Note 2 Note 2 Note 2 Note 2 Offset from 8 ns pulse width at 50% of pulse peak, - 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Measured at line side of transformer, line replaced by 100 (1%) resistor. Table 34. 10BASE-T Transceiver Electrical Characteristics Parameter Sym Min Typ1 Max Units Test Conditions Transmitter Peak differential output voltage Transmit timing jitter addition2 Transmit timing jitter added by the MAU and PLS sections2, 3 VP 2.2 2.5 2.8 V Measured at line side of transformer, line replaced by 100 ( .1%) resistor 0 line length for internal MAU After line model specified by IEEE 802.3 for 10BASE-T internal MAU - 8 - 24 ms - 0 - Receiver 11 ns Receive input impedance Differential Squelch Threshold ZIN VDS - - 20 390 - - k mV Between TPIP/TPIN 5 MHz square wave input, 750 mVpp 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter additions at 1.5 ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. 78 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 32. 100 Mbps TP Port-to-Port Delay Timing Normal Propagation TP Input t1A TP Output t1B Collision Jamming P Input #1 TP Input #2 t1C TP Output Jam Table 35. 100 Mbps TP Port-to-Port Delay Timing Parameters Parameter TPIP/N to TPOP/N, start of transmission TPIP/N to TPOP/N, end of transmission TPIP/N collision to TPOP/N, start of jam TPIP/N idle to TPOP/N, end of jam Sym Min - - - - Typ1 - - - - Max 46 46 46 46 Units2 BT BT BT BT - - - - t1D Test Conditions t1A t1B t1C t1D 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T = 10-8 s or 10 ns. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 79 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 33. 100BASE-TX MII-to-TP Port Timing TX_CLK t2A TXD, TX_EN, TX_ER t2B t2C t2D CRS t2E TPOP/N Table 36. 100BASE-TX MII-to-TP Port Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted TX_EN sampled to CRS deasserted TX_EN sampled to TPOP/N active (Tx latency) Sym Min 10 5 0 0 - Typ1 - - - - - Max - - 4 16 46 Units2 ns ns BT BT BT - - - - - Test Condition t2A t2B t2C t2D t2E 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T = 10-8 s or 10 ns. 80 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 34. 100BASE-TX TP-to-MII Timing TPIP/N t3A CRS RXD, RX_DV, RX_ER t3B t3C t3D t3E RX_CLK COL t3F t3G Table 37. 100BASE-TX TP-to-MII Timing Parameters Parameter TPIP/N in to CRS asserted TPIP/N quiet to CRS de-asserted CRS asserted to RXD, RX_DV, RX_ER CRS de-asserted to RXD, RX_DV, RX_ER de-asserted RX_CLK falling edge to RXD, RX_DV, RX_ER valid TPIP/N in to COL asserted TPIP/N quiet to COL de-asserted Sym Min - - 1 - - - - Typ1 - - - - - - - Max 46 46 4 3 10 46 46 Units2 BT BT BT BT ns BT BT - - - - - - - Test Conditions t3A t3B t3C t3D t3E t3F t3G 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T = 10-8 s or 10 ns. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 81 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 35. 10BASE-T MII-to-TP Timing TX_CLK t10A TXD, TX_EN, TX_ER t10B t10C CRS Table 38. 10BASE-T MII-to-TP Timing Parameters Parameter TXD, TX_EN, TX_ER Setup to TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled to CRS asserted Sym Min 10 5 0 Typ1 - - .9 Max - - 2 Units2 ns ns BT - - - Test Conditions t10A t10B t10C 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T = 10-7 s or 100 ns. 82 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 36. 10BASE-T TP-to-MII Timing TPIP/N t11A CRS RXD, RX_DV, RX_ER t11B t11C RX_CLK COL t11D Table 39. 10BASE-T TP-to-MII Timing Parameters Parameter TPIP/N in to CRS asserted CRS asserted to RXD, RX_DV, RX_ER RX_CLK falling edge to RXD, RX_DV, RX_ER valid TPIP/N in to COL asserted Sym Min 5 70 - 6 Typ1 6.6 76 - 7.4 Max 8 84 10 9 Units2 BT BT ns BT - - - - Test Conditions t11A t11B t11C t11D 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T = 10-7s or 100 ns. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 83 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 37. 100 Mbps TP-to-IRB Timing TPIP/N t12A IR100DV IR100CFS 1R100COL IR100DAT<4:0> t12B IR100CLK t12C Table 40. 100 Mbps TP-to-IRB Timing Parameters1 Parameter TPIP/N to IR100DV Low IR100DAT to IR100CLK setup time. IR100DAT to IR100CLK hold time. Sym Min 17 - - Typ2 24 4 0 Max 30 - - Units3 BT ns ns - - - Test Conditions t12A t12B t12C 1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are output timings. 2. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 3. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 100BASE-T = 10-8 s or 10 ns. Figure 38. 10 Mbps TP-to-IRB Timing TPIP/N t13A IR10ENA t13B IR10DAT t13C See Table 41, Note 3 IR10CLK 84 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 41. 10 Mbps TP-to-IRB Timing Parameters1 Parameter2 TPIP/N to IR10ENA Low IR10CLK rising edge to IR10DAT rising edge. IR10CLK rising edge to IR10DAT falling edge. Sym Min 3 25 5 Typ3 5.1 Max 7 55 25 Units4 BT ns ns - 330 pull-up, 150 pF load on IR10DAT. 1 k pull-up, 150 pF load on IRCLK. Test Conditions t13A t13B t13C 1. This table contains propagation delays from the TP ports to the IRB for normal repeater operation. All values in this table are output timings. 2. There is a delay of approximately 13 to 16 bit times between the assertion of IR10ENA and the assertion of IR10CLK and IR10DAT. This delay does not affect repeater operation because downstream devices begin generating preamble as soon as IR10ENA is asserted. 3. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 4. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T = 10-7 s or 100 ns. Figure 39. 10 Mbps IRB-to-TP Port Timing MACACTIVE t14A IR10ENA IR10DAT t14C t14B IR10CLK TPOP/N t14D Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 85 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 42. 10 Mbps IRB-to-TP Port Timing Parameters Parameter MACACTIVE to IR10ENA assertion delay 3 IR10DAT (input) to IR10CLK setup time IR10CLK to IR10DAT (input) hold time IR10ENA asserted to TPOP/N active Sym Min - - - 4 Typ1 100 20 0 5.1 Max - - - 6 Units2 ns ns ns BT Test Conditions MACACTIVE High to IR10ENA Low. 4 IR10DAT valid to IR10CLK rising edge.4 IR10CLK rising edge to IR10DAT change.4 - t14A t14B t14C t14D 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 2. Bit Time (BT) is the duration of one bit as transferred to/from the MAC and is the reciprocal of bit rate. BT for 10BASE-T = 10-7 s or 100 ns. 3. External devices should allow at least one 10 MHz clock cycle (10 ns) between assertion of MACACTIVE and IR10ENA. 4. Input. Figure 40. Serial Management Interface Timing t15A t15B SERCLK SRX t15C STX Table 43. Serial Management Interface Timing Characteristics Parameter SERCLK input frequency SERCLK output frequency Data to clock setup time Clock to data hold time Data propagation delay Sym - - t15A t15B t15C 0 200 - Min - Typ1 - 625 - - - Max 2.0 - - - 200 Units MHz kHz ns ns ns Test Conditions Depending on RECONFIG, this is either an input or output. SRX valid to SERCLK rising edge. 2 SERCLK rising edge to SRX change. 2 SERCLK falling edge to STX valid. 3 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 2. Input. 3. Output. 86 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Figure 41. PROM Interface Timing PROM_CLK t16A PROM_CS t16B PROM_DTOUT t16C t16D PROM_DTIN Table 44. PROM Interface Timing Characteristics Parameter PROM_CLK CLK to PROM_CS delay CLK to PROM_DTOUT delay PROM_DTIN to CLK setup time PROM_DTIN to CLK hold time Sym - t16A t16B t16C t16D Min - - - 20 20 Typ1 Max 1.0 200 20 - - Units MHz ns ns ns ns Test Conditions PROM_CLK frequency. CLK falling edge to PROM_CS. CLK falling edge to PROM_DTOUT. PROM_DTIN to CLK rising edge. PROM_DTIN to CLK rising edge. 1. Typical values are at 25 C and are for design aid only; they are not guaranteed and not subject to production testing. 6.0 6.1 Register Definitions Register Map The LXT98x0 register set is composed of multiple 32-bit registers as mapped in Table 45. All register addresses are hexadecimal. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 87 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 45. Register Map Class Register rptrMonitorPortReadableFrames rptrMonitorPortReadableOctets(Lower/Upper) rptrMonitorPortFrameCheckSequence rptrMonitorPortAlignmentErrors Port Counters: TP and MII ports formula: ((N-1)*16) + offset N = port number. 0 < N < 11 rptrMonitorPortFramesTooLong rptrMonitorPortShortEvents rptrMonitorPortRunts rptrMonitorPortCollisions rptrMonitorPortLateEvents rptrMonitorPortVeryLongEvents rptrMonitorPortDataRateMismatches rptrMonitorPortAutoPartitions rptrTrackSourceAddrChanges rptrMonitorPortBroadcastPkts rptrMonitorPortMulticastPkts Size (Bits) 32 64 32 32 32 32 32 32 32 32 32 32 32 32 32 Access 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 1,2 3 4 5 6 7 8 9 A B C D E F Offset (Hex) Page Ref. 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) 88 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 45. Register Map (Continued) Class Register rptrMonitorPortIsolates - port 1 rptrMonitorPortIsolates - port 2 rptrMonitorPortIsolates - port 3 rptrMonitorPortIsolates - port 4 rptrMonitorPortIsolates - port 5 rptrMonitorPortIsolates - port 6 rptrMonitorPortIsolates - port 7 rptrMonitorPortIsolates - port 8 rptrMonitorPortIsolates-MII Port 1 Additional Counters: (100 only) rptrMonitorPortIsolates-MII Port 2 rptrMonitorSymbolErrorDuringPacket - port 1 rptrMonitorSymbolErrorDuringPacket - port 2 rptrMonitorSymbolErrorDuringPacket - port 3 rptrMonitorSymbolErrorDuringPacket - port 4 rptrMonitorSymbolErrorDuringPacket - port 5 rptrMonitorSymbolErrorDuringPacket - port 6 rptrMonitorSymbolErrorDuringPacket - port 7 rptrMonitorSymbolErrorDuringPacket - port 8 Reserved Reserved Size (Bits) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Access1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Offset (Hex) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 Page Ref. 95 95 95 95 95 95 95 95 95 95 96 96 96 96 96 96 96 96 96 96 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 89 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 45. Register Map (Continued) Class etherStatsOctets etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts etherStatsCRCAlignErrors etherStatsUndersizePkts etherStatsOversizePkts etherStatsFragments etherStatsJabbers RMON Counters: (10 only) etherStatsCollisions/ rptrMonitorTransmitCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets Reserved rptrMonitorTotalOctets(Lower/Upper) 32 32 32 32 32 32 32 32 32 R/W R/W R/W R/W R/W R/W R/W R/W R/W BD BE BF C0 C1 C2 C3 C4 C5 97 97 97 97 97 97 97 97 97 Register Size (Bits) 32 32 32 32 32 32 32 32 32 Access 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Offset (Hex) B4 B5 B6 B7 B8 B9 BA BB BC Page Ref. 97 97 97 97 97 97 97 97 97 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) 90 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 45. Register Map (Continued) Class Register etherStatsOctets(Lower/Upper) etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts etherStatsCRCAlignErrors etherStatsUndersizePkts etherStatsOversizePkts etherStatsFragments etherStatsJabbers RMON Counters: (100 only) etherStatsCollisions/ rptrMonitorTransmitCollisions etherStatsPkts64Octets etherStatsPkts65to127Octets etherStatsPkts128to255Octets etherStatsPkts256to511Octets etherStatsPkts512to1023Octets etherStatsPkts1024to1518Octets Reserved rptrMonitorTotalOctets(Lower/Upper) rptrAddrTrackNewLastSrcAddress - port 1 rptrAddrTrackNewLastSrcAddress - port 2 rptrAddrTrackNewLastSrcAddress - port 3 rptrAddrTrackNewLastSrcAddress - port 4 rptrAddrTrackNewLastSrcAddress - port 5 Port Addresses rptrAddrTrackNewLastSrcAddress - port 6 rptrAddrTrackNewLastSrcAddress - port 7 rptrAddrTrackNewLastSrcAddress - port 8 48 48 48 R/W R/W R/W E4, E5 E6, E7 E8, E9 99 99 99 32 32 32 32 32 32 32 32 64 48 48 48 48 48 R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W D0 D1 D2 D3 D4 D5 D6 D7 D8, D9 DA, DB DC, DD DE, DF E0, E1 E2, E3 98 98 98 98 98 98 98 98 98 99 99 99 99 99 Size (Bits) 64 32 32 32 32 32 32 32 32 Access1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Offset (Hex) C6, C7 C8 C9 CA CB CC CD CE CF Page Ref. 98 98 98 98 98 98 98 98 98 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 91 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 45. Register Map (Continued) Class Register Authorized SA port 1 Authorized SA port 2 Authorized SA port 3 Authorized SA port 4 Authorized Addresses Authorized SA port 5 Authorized SA port 6 Authorized SA port 7 Authorized SA port 8 Search Addresses (10 or 100) Search Address Search Match Address Port Link Control Enable Port Alternate Partition Algorithm Control Port Enable Repeater Port Control Port Learn Enable Reserved Port Link Status Port Polarity Status Repeater Port Status Port Partition Status Port Speed Status Port Isolation Status (TX) 8 8 10 10 10 Size (Bits) 48 48 48 48 48 48 48 48 48 10 8 10 10 20 Access 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R(/W) 2 R/W R/W R/W R/W R/W R R R R R Offset (Hex) EE, EF F0, F1 F2, F3 F4, F5 F6, F7 F8, F9 FA, FB FC, FD 102, 103 104 105 108 109 10A 10B 10C 10D 10E 110 111 Page Ref. 99 99 99 99 99 99 99 99 100 100 102 101 101 102 102 103 103 103 103 103 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) 92 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 45. Register Map (Continued) Class Register Auto Negotiate Link Partner Advertisement (port 1) Auto Negotiate Link Partner Advertisement (port 2) Auto Negotiate Link Partner Advertisement (port 3) Auto Negotiate Link Partner Advertisement (port 4) Auto Negotiate Link Partner Advertisement (port 5) Auto Negotiate Link Partner Advertisement (port 6) Auto Negotiate Link Partner Advertisement (port 7) Auto Negotiate Link Partner Advertisement (port 8) Auto Negotiate Expansion (port 1) PHY Port Status Auto Negotiate Expansion (port 2) Auto Negotiate Expansion (port 3) Auto Negotiate Expansion (port 4) Auto Negotiate Expansion (port 5) Auto Negotiate Expansion (port 6) Auto Negotiate Expansion (port 7) Auto Negotiate Expansion (port 8) PHY Port Status Register (port 1) PHY Port Status Register (port 2) PHY Port Status Register (port 3) PHY Port Status Register (port 4) PHY Port Status Register (port 5) PHY Port Status Register (port 6) PHY Port Status Register (port 7) PHY Port Status Register (port 8) Size (Bits) 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access1 R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W Offset (Hex) 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 Page Ref. 104 104 104 104 104 104 104 104 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 105 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 93 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 45. Register Map (Continued) Class Register Auto Negotiate Advertise (ports 1) Auto Negotiate Advertise (ports 2) Auto Negotiate Advertise (ports 3) Auto Negotiate Advertise (ports 4) Auto Negotiate Advertise (ports 5) Auto Negotiate Advertise (ports 6) Auto Negotiate Advertise (ports 7) Auto Negotiate Advertise (ports 8) PHY Port Control PHY Port Control Register (port 1) PHY Port Control Register (port 2) PHY Port Control Register (port 3) PHY Port Control Register (port 4) PHY Port Control Register (port 5) PHY Port Control Register (port 6) PHY Port Control Register (port 7) PHY Port Control Register (port 8) Repeater Configuration Repeater Serial Configuration Device/Rev ID Reserved Reserved Reserved Repeater Port Control/ Status Global LED Control Register Port LED Control Register LED Timer Control Register MII Status Repeater Reset Software Reset Interrupt Status Interrupt Mask Serial Controller Assign Address PROM Address 16 16 16 16 16 16 16 16 32 8 32 32 32 32 6 20 16 2 1 1 16 16 32 32 R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R/W R/W R/W R W W R(/W) R/W W R 2 Size (Bits) 16 16 16 16 16 16 16 16 Access 1 R/W R/W R/W R/W R/W R/W R/W R/W Offset (Hex) 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 188, 189 190, 191 Page Ref. 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 107 108 108 108 108 108 108 108 108 108 103 108 109 113 113 108 108 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) 94 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.2 Counter Registers All counters power up to zero. When reading a 64-bit counter, read the lower address (lower 32 bits of counter) first, followed by the upper address. The first read causes all 64 bits to be simultaneously latched into an internal holding register. The second read is directed to this holding register. The statistics bit must be set off to write to the counters. A write operation of the counters is non-atomic for the 64 bit counters. For further definitions refer to RFC 1757 and clause 30 of IEEE 802.3. The ReadableFrame counter max size threshold can either be 1518 or 1522. All counters expecting a Maximum Transmission Unit (MTU) size of 1518 can be changed to a new value of 1522 by setting the Extended Frame bit (13) in the Repeater Configuration Register. 6.2.1 Port Counter Registers The Port Counter descriptions in Table 46 are intended to be illustrative. For the exact definition of these counters, refer to the Repeater MIB, RFC 1516. All counters count packets, octets or events that were received at each port. In the descriptions, the length of a packet never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.), but an "event" does include these items. All Port Counters are Read-Only. Table 46. Port Counter Registers Name Offset Addr1,2 Description Counts valid-length (64 to 1518 bytes), valid-CRC, collision-free packets. Depending on the state of the UnicastFrameCount bit (6) in the Repeater Configuration Register, this counter counts either all packets (UnicastFrameCount = 0) or only Unicast Packets (UnicastFrameCount = 1). See Note 3. Counts the number of octets in all valid-length (64 to 1518 bytes), valid-CRC, collision-free packets, not including preamble and framing bits. This register is not affected by the UnicastFrameCount bit. See Note 3. Counts valid length, collision-free packets that had FCS errors, but were correctly framed (had an integral number of octets). If a framing error occurs, this counter does not increment. Counts valid length, collision-free packets that had FCS errors and were incorrectly framed (had a non-integral number of octets). rptrMonitorPortReadableFrames 0X0 rptrMonitorPortReadableOctets (Lower/Upper) 0X1, 0X2 rptrMonitorPortFrameCheckSequence 0X3 rptrMonitorPortAlignmentErrors 0X4 1. All offset addresses are expressed in hex. 2. Replace "X" in address with specific port to be addressed (offsets 0 through 9 correspond to Ports 1 through 10). 3. The ReadableFrame counter max size threshold can either be 1518 or 1522. All counters expecting a MTU size of 1518 can be changed to a new value of 1522 by setting the Extended Frame bit (13) in the Repeater Configuration Register. 4. For 100 Mbps: the "Short Events" register counts events < 88 bit times; the "Port Runts" register counts events > 92. A 4-bit-time differential exists because 100 Mbps operates with nibble boundaries, so data packets < 4 bits are counted as 4. 5. A0 - A7 corresponds to Port 1 - Port 8. 6. AA - B1 corresponds to Port 1 - Port 8. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 95 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 46. Port Counter Registers (Continued) Name rptrMonitorPortFramesTooLong Offset Addr1,2 0X5 Description Counts packets that had a length greater than 1518 octets. Counts events < `ShortEventMax'. 10 Mbps: 74-82 bit times. 100 Mbps: 74-84 bit times. See Note 4. Counts events > `ShortEventMax', but <512 bits. See Note 4. Counts the number of collisions that occurred, not including late collisions. Counts the number of times a collision is detected after the `LateEventThreshold' time (480-565 bits). This event is counted here and also in the `collisions' attribute. Counts the number of times the transmitter is active for greater than the MJLP time. Counts the number of times the frequency or data rate of the incoming signal is detectably different from that of the local transmit frequency. Counts the number of times this port has been partitioned from the network. Counts the number of times the source address has changed. Counts the number of good broadcast packets received by this port. Counts the number of good multicast packets received by this port. Counts the number of times a port auto isolates. NOTE: When these counters increment, none of the other port counters increment, since the frame never had a valid start. Counts the number of time a packet contained symbol errors. Only one symbol error is counted per packet. On the MII ports this counter is invalid. rptrMonitorPortShortEvents 0X6 rptrMonitorPortRunts rptrMonitorPortCollisions 0X7 0X8 rptrMonitorPortLateEvents 0X9 rptrMonitorPortVeryLongEvents 0XA rptrMonitorPortDataRateMismatches 0XB rptrMonitorPortAutoPartitions rptrTrackSourceAddrChanges rptrMonitorPortBroadcastPkts rptrMonitorPortMulticastPkts 0XC 0XD 0XE 0XF rptrMonitorPortIsolates 0A0-0A75 rptrMonitorSymbolErrorDuringPacket 0AA-0B16 1. All offset addresses are expressed in hex. 2. Replace "X" in address with specific port to be addressed (offsets 0 through 9 correspond to Ports 1 through 10). 3. The ReadableFrame counter max size threshold can either be 1518 or 1522. All counters expecting a MTU size of 1518 can be changed to a new value of 1522 by setting the Extended Frame bit (13) in the Repeater Configuration Register. 4. For 100 Mbps: the "Short Events" register counts events < 88 bit times; the "Port Runts" register counts events > 92. A 4-bit-time differential exists because 100 Mbps operates with nibble boundaries, so data packets < 4 bits are counted as 4. 5. A0 - A7 corresponds to Port 1 - Port 8. 6. AA - B1 corresponds to Port 1 - Port 8. 6.2.2 RMON Counter Registers The interface counter descriptions in Table 47 are intended to be illustrative. For the exact definition of these counters, refer to the RMON MIB, RFC 1757. All counters count events, octets or packets that were received from the interface. Packet length never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.). 96 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 47. RMON Counter Registers - 10 Mbps Name etherStatsOctets Addr 0B4 Description Counts total umber of data octets including those in bad packets and octets in FCS fields, but does not include preamble or other framing bits. Total number of packets received from network, including errored packets. Total number of good broadcast packets received. Total number of good multicast packets received. This number does not include broadcast packets. Total number of valid-length packets (64 to 1518 bytes inclusive) that did not contain an integral number of octets or had a bad Frame Check Sequence (FCS). Total number of well-formed packets that were smaller than 64 octets (excluding framing bits but including FCS octets). Total number of well-formed packets that were longer than 1518 octets (excluding framing bits but including FCS octets). Total number of packets received that were not an integral number of octets in length or that had a bad Frame Check Sequence (FCS) or Frame Alignment Error(FAE), and were less than 64 octets in length (excluding framing bits, but including FCS octets). Note: a packet without SFD or 0 length is counted here. Total number of packets received that were longer than 1518 octets (excluding framing bits, but including FCS octets), and were not an integral number of octets in length or had a bad Frame Check Sequence (FCS). The best estimate of the total number of collisions on this segment. Total number of packets (including error packets) received that were 64 octets in length (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 65 and 127 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 128 and 255 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 256 and 511 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including FCS octets). The total number of packets (including error packets) received that were between 1024 and 1518 octets in length inclusive (excluding framing bits but including FCS octets). Total number of octets contained in valid frames received on this segment. etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts 0B5 0B6 0B7 etherStatsCRCAlignErrors 0B8 etherStatsUndersizePkts etherStatsOversizePkts 0B9 0BA etherStatsFragments 0BB etherStatsJabbers 0BC etherStatsCollisions/ rptrMonitor Transmit Collisions etherStatsPkts64Octets 0BD 0BE etherStatsPkts65to127Octets 0BF etherStatsPkts128to255Octets 0C0 etherStatsPkts256to511Octets 0C1 etherStatsPkts512to1023Octets 0C2 etherStatsPkts1024to1518Octets Reserved rptrMonitorTotalOctets 0C3 0C4 0C5 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 97 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 48. RMON Counter Registers - 100 Mbps Name etherStatsOctets (Lower/Upper) etherStatsPkts etherStatsBroadcastPkts etherStatsMulticastPkts Addr 0C6 0C7 0C8 0C9 0CA Description Counts total umber of data octets including those in bad packets and octets in FCS fields, but does not include preamble or other framing bits. Total number of packets received from network, including errored packets. Total number of good broadcast packets received. Total number of good multicast packets received. This number does not include broadcast packets. Total number of valid-length packets (64 to 1518 bytes inclusive) that did not contain an integral number of octets or had a bad Frame Check Sequence (FCS). Total number of well-formed packets that were smaller than 64 octets (excluding framing bits but including FCS octets). Total number of well-formed packets that were longer than 1518 octets (excluding framing bits but including FCS octets). Total number of packets received that were not an integral number of octets in length or that had a bad Frame Check Sequence (FCS) or Frame Alignment Error(FAE), and were less than 64 octets in length (excluding framing bits, but including FCS octets). Note: A packet without SFD or 0 length is counted here. Total number of packets received that were longer than 1518 octets (excluding framing bits, but including FCS octets), and were not an integral number of octets in length or had a bad Frame Check Sequence (FCS). The best estimate of the total number of collisions on this segment. Total number of packets (including error packets) received that were 64 octets in length (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 65 and 127 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 128 and 255 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 256 and 511 octets in length inclusive (excluding framing bits but including FCS octets). Total number of packets (including error packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including FCS octets). The total number of packets (including error packets) received that were between 1024 and 1518 octets in length inclusive (excluding framing bits but including FCS octets). Total number of octets contained in valid frames received on this segment. etherStatsCRCAlignErrors 0CB etherStatsUndersizePkts etherStatsOversizePkts 0CC 0CD etherStatsFragments 0CE etherStatsJabbers 0CF etherStatsCollisions/ rptrMonitor Transmit Collisions etherStatsPkts64Octets 0D0 0D1 etherStatsPkts65to127Octets 0D2 etherStatsPkts128to255Octets 0D3 etherStatsPkts256to511Octets 0D4 etherStatsPkts512to1023Octets 0D5 etherStatsPkts1024to1518Octets Reserved rptrMonitorTotalOctets (Lower/Upper) 0D6 OD7 0D8, 0D9 98 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.3 Ethernet Address Registers All Ethernet address registers consist of two 32-bit registers that together contain a 48-bit Ethernet address. Address values are unknown on power up. Table 49. Ethernet Address Register Bit Assignments Upper Address Lower Address Bits 31:16 Reserved. Bits 15:0 contain bits 47:32 of the Ethernet Address. Bits 31:0 contain bits 31:0 of the Ethernet Address. 6.3.1 Port Address Registers The port address register set is described in Table 50. The tracking registers continuously monitor the source addresses of packets emanating from the corresponding ports. The authorized address registers can be used for security functions. Table 50. Port Address Tracking Registers Name Type1 Port 1 2 3 4 rptrAddrTrackNewLastSrcAddress RW 5 6 7 8 9 10 1 2 3 4 authorizedSourceAddress R/W 5 6 7 8 Addr2 0DA, 0DB 0DC, 0DD 0DE, 0DF 0E0, 0E1 0E2, 0E3 0E4, 0E5 0E6, 0E7 0E8, 0E9 0EA, 0EB 0EC, 0ED 0EE, 0EF 0F0, 0F1 0F2, 0F3 0F4, 0F5 0F6, 0F7 0F8, 0F9 0FA, 0FB 0FC, 0FD Used for security address comparisons. An auto learn mode is available. Typically, this address matches: rptrAddrTrackNewLastSrcAddress register. These addresses power up unknown, but can be zeroed by software. Description Stores the value of the last Source Address received. Attribute is 6 bytes long. Can also act as NewLastSourceAddress via SW. These addresses power up unknown, but can be zeroed by software. Example Address: 00-20-7B-03-02-01 First Read: msb037B2000lsb. msb Second Read: XXXX0102lsb All addresses or address pairs must read in order. Only the first read updates the holding register. X's are currently defined as zeros. 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. All offset addresses are expressed in hex. 6.3.2 Search Address Registers The LXT98x0 offers an on-board address search mechanism. Should the user wish to find out if a particular source address has been seen on any of the ports, on any of the segments, this register would be used. Each port within a LXT98x0 chip is checked for traffic originating from the source address matching the Search Address register. If a match is found, the port number where the traffic originated is saved, thus allowing software to determine where the address is located. The Search Address Match register contains the port from the Search Address match function. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 99 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management The Search Address and Search Address Match Registers are described in Table 51; bit assignments are provided in Table 53; Search Address Match bit definitions are given in Table 54. Table 51. Search Address/Search Address Match Register Name Search Address R/W Search Match Address 104 This register reflects Search Address Match status Type Addr 102, 103 Description This register reflects Search Address Table 52. Search Address Register Bit Assignments Upper Address Lower Address Bits 31:16 Reserved. Bits 15:0 contain bits 47:32 of the Address. Bits 31:0 contain bits 31:0 of the Address. Table 53. Search Match Address Bit Assignments 31:10 Rsvd 9 Port 10 (MII 2) 8 Port 9 (MII 1) 7 Port 8 6 Port 7 5 Port 6 4 Port 5 3 Port 4 2 Port 3 1 Port 2 0 Port 1 Table 54. Search Match Address Bit Definitions Name Reserved Port 10 (MII 2) Port 9 (MII 1) Port 8 Port 7 Type1 R R/W R/W R/W R/W 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. 1 = Address in Search Address register matched on this port. 0 = Address did not match Search Address on this port. Description Default 0 0 0 0 0 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 100 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.4 Repeater Port Control Registers The Control Register set includes general port control as well as link and learn enable registers. 6.4.1 General Port Control Registers The General Port Control Register bit assignments are described in Table 55. Refer to Table 56 for the General Port Control Register descriptions. Table 55. Port Control Register Bit Assignments 31:10 Rsvd 9 Port 10 (MII 2) 8 Port 9 (MII 1) 7 Port 8 6 Port 7 5 Port 6 4 Port 5 3 Port 4 2 Port 3 1 Port 2 0 Port 1 1. Bits 8 and 9 (MII Ports) are not used by the Link Control Register. Table 56. General Port Control Registers Name Type1 Addr Description Un-partition. The LXT98x0 twisted-pair ports support two un-partition algorithms: The alternative un-partition algorithm, which complies with IEEE specification 802.3aa, un-partitions a port on either transmit or receive of at least 450-560 bits without collision.2 Port Alternate Partition Algorithm Control (100 Mbps Only) R/W 108 The normal algorithm, which complies with the IEEE specification 802.3u, is available through the management interface. This algorithm un-partitions a port only when data is transmitted to the port for 450-560 bit times without a collision. Provides per-port selection of partition algorithms. 0 = normal 1 = alternate This register controls whether a port is enabled/disabled. If the MGR_PRES signal is Low on power up, then all ports are disabled until such time that management software re-enables them. Otherwise, the ports are enabled at power-up. 0 = disable 1 = enable 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 2. Alternate partition mode also causes port to partition after a single long collision. 1 Default Port Enable R/W 109 1 6.4.2 Port Link Control Register The Port Link Control Register bit assignments are described in Table 57. Refer to Table 58 for the Port Link Control Register description. Table 57. Port Link Control and Status Register Bit Assignments 31:8 Rsvd 7 Port 8 6 Port 7 5 Port 6 4 Port 5 3 Port 4 2 Port 3 1 Port 2 0 Port 1 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 101 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 58. Port Link Control Register Name Type1 Addr Description This register controls the link function of the twisted-pair ports. Port Link Control Enable R/W 105 1 = Use Normal Link Control. The port only remains connected to the network so long as link pulses or IDLEs are being received. 0 = Disable Normal Link Control. The port is no longer disconnected due to Link Fail. 1. R = Read only; W = Write only; R/W = Read/Write; LH = Latch High; LL = Latch Low; SC = Self Clearing. 1 Default 6.4.3 Port Learn Enable Register The Port Learn Enable Register bit assignments are described in Table 59. Refer to Table 60 for the Port Learn Enable Register description. Table 59. Port Learn Enable Register 31:20 Rsvd 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Port 10 (MII 2) Port 9 (MII 1) Port 8 Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Table 60. Port Learn Enable Register Name Type Addr Description This register sets the level of learning each port uses. The Learn Settings are as follows: Bit 1 0 Port Learn Enable R/W 10A 0 1 Bit 0 0 Function Learn each new source addresses. Next Lock. Learn only the first source address encountered. After a port learns its first address, it changes the Authorized Learn bits (for that port) to a "10" to lock down the address. Lock. Hardware locked-down the address. Only software can write to this address. Reserved. 00 Default 1 1 0 1 6.5 Repeater Port Status Registers The Port Status Register bit assignments are described in Table 61. Refer to Table 62 for the Port Status Register descriptions. 102 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 61. Port Status Register Bit Assignments 31:10 Rsvd 9 Port 10 (MII 2) 8 Port 9 (MII 1) 7 Port 8 6 Port 7 5 Port 6 4 Port 5 3 Port 4 2 Port 3 1 Port 2 0 Port 1 1. Not all Status Registers use bits 8 and 9. Table 62. Port Status Registers Name Port Link Status2 Description Reflects the current link status of each twisted-pair port. 1 = Link Up. 0 = Link Down. Reflects the current polarity status of each twisted-pair port. Port Polarity Status2 1 = Polarity Reversed. 0 = Polarity Normal. Reflects the current partition status of each twisted-pair port. Port Partition Status 1 = Port is Partitioned. 0 = Port is Not Partitioned. Indicates the current speed status of each port. Port Speed Status 1 = Port is connected at 100 Mbps. 0 = port is connected at 10 Mbps. Indicates the current isolation status of each twisted-pair port. 1 = Port is Isolated. 0 = Port is Not Isolated. Individual per-port status registers. Refer to Table 68 on page 105 for addressing and other details. R 110 0 R 10E 0 R 10D 0 R 10C 0 Type1 Addr Default Port Isolation Status R 111 0 PHY Port Status (Summary) R/W - 1. R = Read Only 2. Register does not track MII port status. Bits 8 and 9 reserved. Table 63. MII Speed Status Bit Assignments 31:10 Rsvd 9 Rsvd 8 Rsvd 7 Rsvd 6 Rsvd 5 Rsvd 4 Rsvd 3 Rsvd 2 Rsvd 1 MII 2 0 MII 1 Table 64. MII Status Bit Definitions Name Description Individual MII port speed status registers. MIISpeed Status 1 = 100 Mbps 0 = 10 Mbps 1. R = Read only; W = Write only, R/W = Read/Write, LOR = Latch on Reset, LL = Latch Low, SC = Self Clearing R 143 LOR Type 1 Addr Default Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 103 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management 6.6 PHY Port Status Registers The port auto-negotiation registers are described in Table 65 through Table 71. Table 65. Auto-Negotiation Registers Name Auto-Negotiate Link Partner Advertisement #1 (Port 1) Auto-Negotiate Link Partner Advertisement #1 (Port 2) Auto-Negotiate Link Partner Advertisement #1 (Port 3) Auto-Negotiate Link Partner Advertisement #1 (Port 4) Auto-Negotiate Link Partner Advertisement #1 (Port 5) Auto-Negotiate Link Partner Advertisement #1 (Port 6) Auto-Negotiate Link Partner Advertisement #1 (Port 7) Auto-Negotiate Link Partner Advertisement #1 (Port 8) Auto-Negotiate Expansion #1 (Port 1) Auto-Negotiate Expansion #1 (Port 2) Auto-Negotiate Expansion #1 (Port 3) Auto-Negotiate Expansion #1 (Port 4) Auto-Negotiate Expansion #1 (Port 5) Auto-Negotiate Expansion #1 (Port 6) Auto-Negotiate Expansion #1 (Port 7) Auto-Negotiate Expansion #1 (Port 8) Size Bits 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Addr 112 113 114 115 116 117 118 119 11A 11B 11C 11D 11E 11F 120 121 Type R R R R See Table 66 on page 104. R R R R R R R R See Table 67 on page 105. R R R R Description Table 66. Auto-Negotiate Link Partner Advertisement Bit Definitions Bit 31.16 15 14 13 12:10 9 8 7 Name Reserved Next Page Reserved Remote Fault Reserved 100BASE-T4 100BASE-TX FD 100BASE-TX Reserved. 1 = Link partner has ability to send multi pages. 0 = Link partner has no ability to send multi pages. Reserved. 1 = Remote fault. 0 = No remote fault. Reserved. 1 = Link partner is 100BASE-T4 compatible. 0 = Link partner is not 100BASE-T4 compatible. 1 = Link partner is 100BASE-TX FD capable. 0 = Link partner is not 100BASE-TX FD capable. 1 = Link partner is 100BASE-TX capable. 0 = Link partner is not 100BASE-TX capable. Description Type 1 R R R R R R R R Default 0 0 0 0 0 0 0 0 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing 104 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 66. Auto-Negotiate Link Partner Advertisement Bit Definitions (Continued) Bit 6 5 4:0 Name 10BASE-T FD 10BASE-T Selector Field Description 1 = Link partner is 10BASE-T FD capable. 0 = Link partner is not 10BASE-T FD capable. 1 = Link partner is 10BASE-T capable. 0 = Link partner is not 10BASE-T capable. IEEE 802.3 Type 1 R R R Default 0 0 00000 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing Table 67. Auto-Negotiate Expansion Bit Definitions Bit 31.5 4 3 2 1 Name Reserved Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner Auto Negotiate Able Reserved. 1 = More than one of the PMAs detects a valid link. 0 = No conflict. 1 = Link partner is next page able. 0 = Link partner is not next page able. 0 = Local device is not next page able. 1 = 3 identical and consecutive link code words are received. 0 = 3 identical and consecutive link code words have not been received. 1 = Link partner is auto negotiate able. 0 = Link partner is not auto negotiate able. Description Type 1 R R/LH R R R/LH Default 0 0 0 0 0 0 R/LH 0 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing Table 68. PHY Port Status Register Summary Name Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Size 32 32 32 32 32 32 32 32 Addr 122 123 124 125 126 127 128 129 Type R R R R Per port register indicating current status of operating conditions. R R R R Description Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 105 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 69. PHY Port Status Register Bit Definitions Bit 31:16 15 14 13 12 11 10 9 8 7 6 Name Reserved 100BASE-T4 100BASE-X Full Duplex 100BASE-X Half Duplex 10 Mbps Full Duplex 10 Mbps Half Duplex 100BASE-T2 Full Duplex 100BASE-T2 Half Duplex Reserved Reserved MF Preamble Suppression Auto-Negotiation complete Remote Fault Auto-Negotiation Ability Link Status Reserved Reserved Reserved. 1 = Port able to perform 100BASE-T4. 0 = Port not able to perform 100BASE-T4. 1 = Port able to perform full-duplex 100BASE-X. 0 = Port not able to perform full-duplex 100BASE-X. 1 = Port able to perform half-duplex 100BASE-X. 0 = Port not able to perform half-duplex 100BASE-X. 1 = Port able to operate at 10 Mbps in full-duplex mode. 0 = Port not able to operate at 10 Mbps full-duplex mode. 1 = Port able to operate at 10 Mbps in half-duplex mode. 0 = Port not able to operate at 10 Mbps in half-duplex. 1 = Port able to perform full-duplex 100BASE-T2. 0 = Port not able to perform full-duplex 100BASE-T2. 1 = Port able to perform half duplex 100BASE-T2. 0 = Port not able to perform half-duplex 100BASE-T2. Reserved. Tie to ground. Ignore when read. 1 = Port accepts management frames with preamble suppressed. 0 = Port does not accept management frames with preamble suppressed. 1 = Auto-Negotiation process completed. 0 = Auto-Negotiation process not completed. 1 = Remote fault condition detected. 0 = No remote fault condition detected. 1 = PHY is able to perform Auto-Negotiation. 0 = PHY is not able to perform Auto-Negotiation. 1 = Link is up. 0 = Link is down. Reserved. Read as 0. Reserved. Read as 0. Description R/W R R R R R R R R R R R Default 0 0 0 1 0 1 0 0 0 0 0 5 4 3 2 1 0 R R/LH R R/LL R R 0 0 1 0 0 0 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing 106 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.7 PHY Port Control Registers Name Auto-Negotiate Advertisement #1 (Port 1) Auto-Negotiate Advertisement #1 (Port 2) Auto-Negotiate Advertisement #1 (Port 3) Auto-Negotiate Advertisement #1 (Port 4) Auto-Negotiate Advertisement #1 (Port 5) Auto-Negotiate Advertisement #1 (Port 6) Auto-Negotiate Advertisement #1 (Port 7) Auto-Negotiate Advertisement #1 (Port 8) Size Bits 32 32 32 32 32 32 32 32 Addr 12A 12B 12C 12D 12E 12F 130 131 Type R R R R See Table 71 on page 107. R R R R Description Table 70. Auto-Negotiation Advertisement Registers Table 71. Auto Negotiate Advertisement Bit Definitions Bit 31.16 15 14 13 12:10 9 8 7 6 5 4:0 Name Reserved Next Page Reserved Remote Fault Reserved 100BASE-T4 100BASE-TX FD 100BASE-TX 10BASE-T FD 10BASE-T Selector Field Reserved. 1 = Port has ability to send multi pages. 0 = Port has no ability to send multi pages. Reserved. 1 = Remote fault. 0 = No remote fault. Reserved. 1 = Port is 100BASE-T4 compatible. 0 = Port is not 100BASE-T4 compatible. 1 = Port is 100BASE-TX Full-Duplex capable. 0 = Port is not 100BASE-TX Full-Duplex capable. 1 = Port is 100BASE-TX capable. 0 = Port is not 100BASE-TX capable. 1 = Port is 10BASE-T FD capable. 0 = Port is not 10BASE-T FD capable. 1 = Port is 10BASE-T capable. 0 = Port is not 10BASE-T capable. IEEE 802.3. Description Type 1 R R R R/W R R R R/W R R/W R Default 0 0 0 0 0 0 0 1 0 1 00001 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing Table 72. PHY Port Control Register Name Port Control Register Type1 R/W Addr 132 - 139 Description Refer to Table 73 for bit assignments. 1. R = Read only; W = Write only; R/W = Read /Write. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 107 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 73. PHY Port Control Bit Definitions Bit 31:16 15 14 13 12 11 10 9 8 7 6:0 Name Reserved Reserved Loopback Speed Selection Auto-Negotiation Enable Reserved Reserved Restart Auto-Negotiation Duplex Mode Collision Test Reserved Reserved Write as 0; ignore on read. Value is "O" only. 1 = 100 Mbps. 0 = 10 Mbps. 1 = Enable Auto-Negotiation Process. 0 = Disable Auto-Negotiation Process. Write as 0; ignore on read. Write as 0; ignore on read. 1 = Restart Auto-Negotiation Process. 0 = Normal operation. 1 = Full-Duplex. 0 = Half-Duplex. 1 = Enable COL signal test. 0 = Disable COL signal test. Write as 0, ignore on Read. Description Type 1 R R/W R R/W R/W R/W R/W R/W SC R R/W R/W Default 0 0 0 0 1 0 0 0 0 0 0000000 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing 6.8 Repeater Port Control/Status Registers The Configuration Register set is described in Table 74. Configuration Register definitions and bit assignments are shown in Table 73 through Table 76. Table 74. Configuration Registers Name Repeater Configuration Register Repeater Serial Configuration Register Type1 R/W Addr 13A Description Refer to Table 75 for bit assignments. This register holds user-defined data. These bits may be used to indicate the type of board configuration, port count or other vendor-related data. Default is set by pins. Refer to Table 76 for bit assignments. This register follows the IEEE 1149.1 specification. Refer to Table 77 for bit assignments. Device/Revision ID register R 13C The upper 4 bits identify the device revision level. The next 16 bits store the Part ID Number. The next 11 bits contain a JEDEC Manufacturer ID, which for Intel is hexadecimal `FE'. The lowest bit (0) is set only for the first device in a chain. The encoding scheme used for the Product ID field is implementation dependent. - R 13B Reserved Reserved Reserved R R R 13D 13E 13F 1. R = Read only; W = Write only; R/W = Read /Write. 108 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 74. Configuration Registers (Continued) Name Global LED Control Register Type1 R/W Addr 140 Description This register reflects the LED Mode set by hardware pins, and provides software control for the Global Fault LED. Refer to Table 78. This register provides a measure of software control over the port LEDs. Refer to Table 81 for bit assignments. During reset, the state of this register is all 1s. If a manager is present, this register remains in the all 1s state after reset. Otherwise, the bits default to hardware control. Refer to "LED Timer Control Register" on page 112 for details. Bits 15:8 of this register set the slow blink frequency of the LEDs. Bits 7:0 set the fast blink frequency. Writing any data value to this register with the Least Significant Bit (LSB) = 1 causes the repeater logic to reset. (All bits other than LSB do not matter.) The counters and configuration information are held static and is not reset. Refer to Table 83 on page 113 for details. Writing any data value to this register with the Least Significant Bit (LSB) = 1 is identical to a hardware reset. (All bits other than LSB do not matter.) Refer to Table 84 on page 113 for details. Writing a valid 48-bit ID (one that matches the PROM ID) to this register causes the device to change its Hub ID to the contents of the PROM ID register listed below. This register cannot be read. Refer to Table 89 and Table 90, "Assign Addr 2" on page 116 for details. These two registers contain the 48-bit ID read in from PROM at power-up. Refer to Table 91 and Table 92, "PROM Addr 2" on page 116 for details. Port LED Control Register R/W 141 LED Timer Control Register R/W 142 Repeater Reset Register W 144 Software Reset Register W 145 Assign Address Register (1 and 2) W 188, 189 PROM Address Register (1 and 2) R 190, 191 1. R = Read only; W = Write only; R/W = Read /Write. Table 75. Repeater Configuration Register Bit 31:15 14 Name Reserved Configuration Mode Select Description Reserved - Write as 0's, ignore on Read Configuration Mode Select 0 = 2 bit direct input mode (using CONFIG[1:0]) 1 = 8 bit serial bus mode (using CFG_CLK, CFG_DT, CFG_LD) Extended Frame counting mode 13 Extended Frame 1 = all relevant counters allow max size frames up to 1522 bytes, etherstats counter change from 1518 to 1522 0 = normal mode 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until the "zero counter" bit has been reset back to `0'. This time period is roughly 15 s. R/W 0 R/W 0 Type 1 R/W Default 0 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 109 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 75. Repeater Configuration Register (Continued) Bit Name Enable Port Late Event 12 Enable Port Late Event 0 = does not allow out of window collisions to increment port Late Event counters. 1 = does allow out of window collisions to increment port Late Event counters. Register Clear 11 Register Clear 0 = clears appropriate registers upon serial read. 1 = requires that appropriate register bits be written to be cleared. (Write a `1' to the bit(s) that are to be cleared.) 10 9 8 7 Statistics Enable Send /T/R Isolate100 Isolate10 Statistics Enable-Turns statistics gathering on and off. Send /T/R - Forces a good /T/R after each 100 Mbps transmission Isolate100 - Isolates the IR100CFS stack signal and provides an output pin for disabling an external backplane transceiver Isolate10 - Same as for 100 except also isolates stack IR10COLBP and IR10CFSBP signal. Unicast Frame count 6 5 Unicast Frame count Arbitration Value 1 = portReadableFrames count only Unicast Frames. 0 = portReadableFrames count all Frames. Arbitration Input Value-as read from input pin Zero Counters 4 Zero Counters 1 = LXT98x0 sequentially walks through each counter location and zero its contents. When all counter locations have been cleared, this bit is reset to `0'.2 0 = normal Enable FIFO error 3 Enable FIFO error 1 = LXT98x0 enters transmit collision upon detection of a data rate mismatch. 0 = Normal 2 Reserved Reserved - Write as `0', ignore on Read. R/W 0 R/W 1 R/W 0 R 0 R/W 0 R/W R/W R/W R/W 1 0 0 0 R/W 0 R/W 0 Description Type 1 Default 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 2. While the zeroing operation is in progress, the CPU is locked out from accessing the statistics RAM until the "zero counter" bit has been reset back to `0'. This time period is roughly 15 s. Table 76. Repeater Serial Configuration Bit 31:8 7:2 1:0 Name Reserved RptrSerConfig RptrSerConfig Reserved. Bits 7:2 of Configuration Interface data. (8-bit mode). Refer to Table 75, bit 14 description. Bits 1:0 of Configuration Interface data. Refer to Table 75, bit 14 description. Description Type 1 R R R Default 0 0 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 110 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.8.1 Device/Revision Register The value of this register follows the same scheme as the device identification register found in the IEEE 1149.1 specification. The upper 4 bits correspond to silicon stepping. The next 16 bits store a Part ID Number. The next 11 bits contain a JEDEC Manufacturer ID. Bit zero is `1' if the chip is the first in a stack. The encoding scheme used for the Product ID field is implementation dependent. Table 77. Device/Revision Register Bit Assignment 31:28 Version 0000 6-port = 0010 0110 1000 0100 1. The JEDEC ID is an 8-bit identifier. However, the MSB is for parity only and is ignored. Intel's JEDEC ID is FE (1111 1110) which becomes 111 1110. 2. First Chain Bit = 0 if ChipID 00. First Chain Bit = 1 if ChipID = 00. 27:12 Part No. 8-port = 0010 0110 1001 1000 0000 111 1110 See Note 2 11:8 Jedec Continuation Characters 7:1 JEDEC ID 1 0 1st in Chain2 6.8.2 LED Control Registers The LED Control Registers and bit assignments are described in Table 78. 6.8.3 LED Global Control Register This register allows software to have a measure of control over the Global Fault LED; it can read status of LED mode. If a manager is present the default for the Global Fault LED is 11, else it is 01. Bits (5:4) state what LED mode the chip is in ("00" = mode 1, 01" = mode 2, "10" = mode 3 and "11"= mode 4). These bits are read-only because the LED mode is set only via pins. When writing this register, all other bits in this register are reserved and may have default = 1 or 0. Table 78. Global Fault LED Bit Assignments 31:6 Reserved Bit 31:8: Write as 1; Ignore on read Bit 7: Write as 0; Ignore on read Bit 6: Write as 1; Ignore on read Mode Select Global Fault Reserved Write as 0; Ignore on read 5:4 3:2 1:0 6.8.4 Port LED Control Register This register (refer to Table 80) is used to encode the measure of control software has over the port LEDs. The LED control encodings are listed in Table 81. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 111 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 80. LED Configuration Bit 31:20 19:18 17:16 15:14 13:12 11:10 9:8 7:6 5:4 3:2 1:0 Name Reserved MII2LED MII1LED PortLED7 PortLED6 PortLED5 See Table 81 for Bit Definitions. PortLED4 PortLED3 PortLED2 PortLED1 PortLED0 R/W R/W R/W R/W R/W 10 10 10 10 10 Reserved Description Type 1 R/W R/W R/W R/W R/W R/W Default 0s 10 10 10 10 10 1. R = Read only; W = Write only, R/W = Read/Write, LH = Latch High, LL = Latch Low, SC = Self Clearing 2. During reset, the state of this register is all 1s. If a manager is present within the system, this register stays in the all 1s state following reset. Otherwise, they default to hardware control (10). Table 81. Port LED1, 2, 3 Control Encodings Port LED1 Port Conf. Bits 00 01 10 11 Modes 1, 3 and 4 Function LED off Reserved LED fast blink Mode 2 Function Port LED2 Modes 1 and 4 Function LED off LED Off Reserved Hardware control LED off Hardware control Hardware control LED Off Hardware control Hardware control LED off LED on Modes 2 and 3 Function Port LED 3 Modes 1, 3, 4 Mode 2 LED Off 6.8.5 LED Timer Control Register The upper 8 bits serves as a register for programming the slow blink frequency of the LEDs. The lower 8 bits program the fast LED blink rate. In both registers, the maximum blink frequency is 128 Hz while the minimum frequency is 0.5 Hz. The slow LED blink rate only applies to LED Mode 2, while the fast LED blink rate is applicable to all LED schemes. Table 82. LED Timer Control Register Bit Assignments 31:16 Reserved 15:8 Slow Blink Frequency Default is xCC, 1.6 s Period = 7.8125 ms x (Register Value + 1) Frequency = 1 / 7.8125 ms x (Register Value + 1) 7:0 Fast Blink Frequency Default is x32, 0.4 s 112 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 6.8.6 Repeater Reset Register Table 83. Repeater Reset Bit 31:1 0 Name Reserved RPTRRS T Reserved. Writing a `1' to this bit causes the repeater logic to be reset. Counter and configuration logic does NOT reset. Description Type 1 R W Default 0 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 6.8.7 Software Reset Register Table 84. Software Reset Bit 31:1 0 Name Reserved SWRST Reserved. Writing a `1' to this bit causes the chip logic to be reset. Software Reset is the same as a Hardware Reset. Description Type 1 R W Default 0 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 6.8.8 Interrupt Registers Table 85. Interrupt Status/Mask Register Name Interrupt Status Register Interrupt Mask Register Type R/W R/W Addr 146 147 Description This register captures status bits within the LXT98x0 and holds them. This register allows masking of individual interrupts. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 113 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 86. Interrupt Status Register Bit Definitions Bit 31:6 Name Reserved Type 1, 2 R/W Reserved Jabber Interrupt A `1' indicates that a port is in jabber state. During 100 Mbps operation, jabber occurs when any receiver remains active for more than 57,500 bit times. The LXT98x0 exits this state when all receivers return to the idle condition. During 10 Mbps operation, jabber occurs when any port remains actively transmitting for longer than 40,000 to 75,000 bit times. The LXT98x0 asserts a minimum-IFG idle period when a port is jabbering. Isolate Interrupt A `1' indicates that a port has been isolated (100 Mbps only). 4 ISOLINT R/W The LXT98x0 isolates any port transmitting more than two successive false carrier events. A false carrier event is defined as a packet not starting with a /J/K symbol pair. Partition Interrupt A `1' indicates a port has been partitioned. In 100 Mbps operation, the LXT98x0 partitions any port participating in excess of 60 consecutive collisions. 3 PARTINT R/W In 10 Mbps operation, the LXT98x0 partitions any port participating in excess of 31 consecutive collisions. Once partitioned, the LXT98x0 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. 2 FCCINT R/W False Carrier Count Interrupt A `1' indicates a port has received too many false carrier events. Source Address Change Interrupt 1 SACHNGINT R/W A `1' indicates that a port address changed from that stored in the last Source Address register. Speed Change Interrupt A `1' indicates a port speed change was detected. 0 0 0 0 Description Default 0 5 JABINT R/W 0 0 SPDCHNGINT R/W 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing 2. If Register Clear bit is set to `1', then clearing of the associated bit is done by writing `1' to it, otherwise this register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register. (Refer to Table 75 on page 109.) 114 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 Table 87. Interrupt Mask Bit Definitions Bit 31:6 5 Name Reserved JABMSK Type 1 R/W R/W Reserved Jabber Mask Set 0 = do not mask 1 = mask Isolate Mask Set 4 ISOLMSK R/W 0 = do not mask 1 = mask Partition Mask Set 3 PARTMSK R/W 0 = do not mask 1 = mask False Carrier Count Mask Set 2 FCCMSK R/W 0 = do not mask 1 = mask Source Address Change Mask Set 1 SACHNGMSK R/W 0 = do not mask 1 = mask Speed Change Mask Set 0 SPDCHNGMSK R/W 0 = do not mask 1 = mask 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing. 0 0 0 0 0 0 Description Default 0 6.9 Serial Controller Registers Table 88. Configuration Registers Name Type1 Addr Description Writing a valid 48-bit ID (one that matches the PROM ID) to this register causes the device to change its Hub ID to the contents of the PROM ID register listed below. This register cannot be read. Refer to Table 89 and Table 90, "Assign Addr 2" on page 116 for details. These two registers contain the 48-bit ID read in from PROM at power-up. Refer to Table 91 and Table 92, "PROM Addr 2" on page 116 for details. Assign Address Register (1 and 2) W 188, 189 PROM Address Register (1 and 2) R 190, 191 1. R = Read only; W = Write only; R/W = Read /Write. Table 89. Assign Addr 1 Bit 31.0 Name ASSIGN4716 Description Bits (47:16) of the PROM serial number Type 1 W Default 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing. Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 115 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Table 90. Assign Addr 2 Bit 31.21 20:16 15:0 Name Reserved Hub ID ASSIGN150 Reserved Bits (4:0) of the Hub ID Bits (15:0) of the PROM serial number Description Type 1 W W W Default 0 0 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing. Table 91. PROM Addr 1 Bit 31.0 Name PROM4716 Description Bits (47:16) of the PROM serial number Type 1 R Default 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing. Table 92. PROM Addr 2 Bit 31.16 15:0 Name Reserved PROM150 Reserved Bits (15:0) of the PROM serial number Description Type 1 R R Default 0 0 1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing. 116 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 Advanced 10/100 Repeater with Integrated Management -- LXT9860/9880 7.0 Mechanical Specifications Figure 42. LXT98x0 Package Specifications for Commercial Temperature 208-Pin Plastic Quad Flat Package * Part Number LXT98x0HC, LXT98x0AHC * Commercial Temperature Range (0C to 70C) D D1 Millimeters Dim Min A A1 e Max 4.10 3.60 0.27 30.90 28.30 30.90 28.30 .50 BASIC 0.25 3.20 0.17 30.30 27.70 30.30 27.70 A2 b D e E1 E /2 D1 E E1 e 2 L1 A A2 A1 L b 3 L L1 q 2 3 0.50 1.30 0 5 5 REF 0.75 7 16 16 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 117 LXT9860/9880 -- Advanced 10/100 Repeater with Integrated Management Figure 43. LXT98x0 Package Specifications for Extended Temperature 208-Pin Plastic Quad Flat Package Heat Slug * Part Number LXT9880AGE * Extended Temperature Range (-40C to +85C) 118 Datasheet Document #: 248987 Revision#: 003 Rev Date: 08/07/01 This datasheet has been downloaded from: www..com Datasheets for electronic components. |
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