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E2I0022-17-Y1
Semiconductor MSM52V1017LP
Semiconductor 65,536-Word 16-Bit CMOS STATIC RAM
This version: Jan. 1998 MSM52V1017LP Previous version: Aug. 1996
DESCRIPTION
The MSM52V1017LP is a 65,536-word by 16-bit CMOS static RAM featuring 3.0 V to 3.6 V power supply operation in the range of -40C to 85C and direct LVCMOS input/output compatibility. Since the circuitry is completely static, external clock and refreshing operations are unnecessary, making this device very easy to use. The MSM52V1017LP can be used in the high-speed operation of an access time 100 ns due to adopting a high-performance CMOS technology and in the low current consumption of a standby current max. 50 mA when there is no chip selection. In addition, the MSM52V1017LP is provided with a chip enable signal (CE) suited to the expansion of a memory capacity, an output enable signal (OE) suited to the I/O bus line control, and a byte select signal (LB, UB) that can independently control the input/output of a lower byte and an upper byte.
FEATURES
* 65,536-word 16-bit configuration * Power supply voltage: 3.0 V to 3.6 V * Fully static operation * Operating temperature range: Ta = -40C to 85C * (Input/Output) LVCMOS compatible * 3-state output * Data retention available at power supply voltage 2 V * Equal to Mask ROM/OTP in supply pin layout * Package options: 44-pin 400 mil plastic TSOP (Type II) (TSOPII44-P-400-0.80-K) (Product : MSM52V1017LP-xxTS-K) (TSOPII44-P-400-0.80-L) (Product : MSM52V1017LP-xxTS-L) xx indicates speed rank.
PRODUCT FAMILY
Family MSM52V1017LP-10 MSM52V1017LP-12 Access Time (Max.) 100 ns 120 ns Power Dissipation Operating (Max.) 180 mW 144 mW Standby (Max.) 0.18 mW
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Semiconductor
PIN CONFIGURATION (TOP VIEW)
NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 CE 11 NC 12 VSS 13 OE 14 I/O1 15 I/O2 16 I/O3 17 I/O4 18 I/O5 19 I/O6 20 I/O7 21 I/O8 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
28 27 26 25 24 23
MSM52V1017LP
NC LB UB A14 A15 A13 WE A8 A9 A11 A10 NC VSS I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 VCC
NC 44 LB 43 UB 42 A14 41 A15 40 A13 39 WE 38 A8 37 A9 36 A11 35 A10 34 NC 33 VSS 32 I/O16 31 I/O15 30 I/O14 29 I/O13 28 I/O12 27 I/O11 26 I/O10 25 I/O9 24 VCC 23
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22
NC A12 A7 A6 A5 A4 A3 A2 A1 A0 CE NC VSS OE I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
44-Pin Plastic TSOP (II) (K Type)
44-Pin Plastic TSOP (II) (L Type)
Pin Name A0 - A15 I/O1 - I/O16 CE WE OE LB, UB VCC, VSS NC
Function Address Input Data Input/Output Chip Enable Write Enable Output Enable Byte Data Select Power Supply No Connection
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Semiconductor
MSM52V1017LP
BLOCK DIAGRAM
A2 A3 A0 A1 A8 A9 A11 A10 I/O1 : : I/O8 I/O9 : : I/O16 V CC V SS
Row Select
Memory Array 256 Rows 256 Columns 16 Blocks
Input Data Control
Column I/O Circuits Column Select
A12 A14 A4 A6 A7 A15 A5 A13 : CE LB UB :
WE
OE
FUNCTION TABLE
Operating Mode Non Selectable CE L X H H Read Cycle H H H H H Write Cycle H H LB X H L L H L L H L L H UB X H L H L L H L L H L WE X X H H H H H H L L L OE X X L L L H H H X X X I/O1 - I/O8 High-Z High-Z Data Read Data Read High-Z High-Z High-Z High-Z Data Write Data Write High-Z I/O9 - I/O16 High-Z High-Z Data Read High-Z Data Read High-Z High-Z High-Z Data Write High-Z Data Write Power Mode Standby Standby Active Active Active Active Active Active Active Active Active
X: Don't Care ("H" or "L")
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Semiconductor
MSM52V1017LP
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power Supply Voltage Pin Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VT PD Topr Tstg Condition Ta = 25C, for VSS Ta = 25C -- -- Rating -0.5 to 4.6 -0.5* to VCC + 0.5 0.7 -40 to 85 -55 to 125 Unit V V W C C
* -1.2 V Min. for pulse width less than 30 ns. Recommended Operating Conditions
Parameter Power Supply Voltage Data Retention Voltage Input High Voltage Input Low Voltage Load Capacitance Fan Out Symbol VCC VSS VCCH VIH VIL CL N Condition -- -- VCC = 3.0 V to 3.6 V -- LVCMOS Min. 3.0 0 2 2.4 -0.3* -- -- Typ. -- 0 -- -- -- -- -- Max. 3.6 0 3.6 VCC + 0.3 0.4 100 1 Unit V V V V V pF --
* -1.2 V Min. for pulse width less than 30 ns. Capacitance
(Ta = 25C, f = 1 MHz) Parameter Input Capacitance Input/Output Capacitance Symbol CI CI/O Condition VI = 0 V VI/O = 0 V Min. -- -- Max. 10 10 Unit pF pF
Note:
This parameter is periodically sampled and not 100% tested.
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Semiconductor DC Characteristics
MSM52V1017LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Symbol ILI ILO VOH VOL Condition VIN = 0 to VCC CE = VIL or LB, UB = VIH or OE = VIH or WE = VIL, VOUT = 0 to VCC IOH = -100 mA IOL = 100 mA LB, UB VCC - 0.2 V, CE VCC - 0.2 V or 0 V CE 0.2 V, VIN = 0 to VCC LB, UB = VIH or CE = VIL LB, UB = VIL, CE = VIH, VIN = VIH / VIL, TCYC = Min. cycle, IOUT = 0 mA Operating Power Supply Current ICCA LB, UB 0.2 V, CE VCC - 0.2 V, VIH VCC - 0.2 V, VIL 0.2 V, TCYC = 1 ms, IOUT = 0 mA MSM52V1017LP Min. -1.0 -1.0 VCC - 0.2 -- Typ. -- -- -- -- Max. 1.0 1.0 -- 0.2 Unit mA mA V V
Standby Power Supply Current
ICCS
--
--
50
mA
ICCS1
--
--
0.6
mA
--
--
q
mA
--
--
15
mA
q 52V1017LP-10 50 mA 52V1017LP-12 40 mA
AC Characteristics Test Conditions
Parameter Input Pulse Level Input Rise and Fall Times Input/Output Timing Level Output Load Condition VIH = 2.4 V, VIL = 0.4 V 5 ns 1.4 V CL = 100 pF, 1 LVCMOS
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Semiconductor Read Cycle
Parameter Read Cycle Time Address Access Time LB, UB Access Time CE Access Time OE Access Time LB, UB to Output in Low-Z CE to Output in Low-Z OE to Output in Low-Z LB, UB to Output in High-Z CE to Output in High-Z Symbol tRC tAA tLB tUB tCO tOE tLBLZ tUBLZ tCLZ tOLZ tLBHZ tUBHZ tCHZ tOH tOHZ
MSM52V1017LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) MSM52V1017LP-10 Min. 100 -- -- -- -- -- 10 10 10 5 -- -- -- -- Max. -- 100 100 100 100 50 -- -- -- -- 35 35 35 35 MSM52V1017LP-12 Min. 120 -- -- -- -- -- 10 10 10 5 -- -- -- -- Max. -- 120 120 120 120 60 -- -- -- -- 35 35 35 35 Unit ns ns ns ns ns ns ns ns ns ns
ADDRESS
, , , ,
OE to Output in High-Z ns Output Hold Time from Address Change 10 -- 10 -- ns
tRC
tAA
tLBHZ, tUBHZ
LB, UB
tLB, tUB
tLBLZ, tUBLZ tCO
CE
tCLZ
tCHZ
OE
tOE
tOHZ
DOUT
Valid Data-out
tOLZ
tOH
Notes:
1. A read cycle occurs during the overlap of LB = "L" (or UB = "L"), CE = "H", OE = "L" and WE = "H". 2. tLBHZ, tUBHZ, tCHZ and tOHZ are specified by the time when DATA is floating, not defined by the output level.
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Semiconductor Write Cycle
Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time LB, UB to End of Write CE to End of Write Address Valid to End of Write WE to Output in High-Z Symbol tWC tAS tWP tWR tDS tDH tLBW tUBW tCW tAW tWHZ tWLZ
MSM52V1017LP
(VCC = 3.0 V to 3.6 V, Ta = -40C to 85C) MSM52V1017LP-10 Min. 100 0 75 5 40 0 90 90 90 90 5 -- Max. -- -- -- -- -- -- -- -- -- -- -- 35 MSM52V1017LP-12 Min. 120 0 90 5 50 0 100 100 100 100 -- 5 Max. -- -- -- -- -- -- -- -- -- -- -- 35 Unit ns ns ns ns ns ns ns ns ns ns ns
, , ,
Output Active from End of Write
tWC ADDRESS tLBW, tUBW LB, UB CE tCW tAW WE tAS tWR tWP tWLZ DOUT tWHZ tDS tDH DIN Data-in
Notes:
1. A write cycle occurs during the overlap of LB = "L" (or UB = "L"), CE = "H" and WE = "L". 2. OE may be either of "H" or "L" in the write cycle. 3. tAS is specified from LB = "L" (or UB = "L"), CE = "H" or WE = "L", whichever occurs last. 4. tWP is an overlap time of LB = "L" (or UB = "L"), CE = "H" and WE = "L". 5. tWR, tDS and tDH are specified from LB = "H" (or UB = "H"), CE = "L" or WE = "H", whichever occurs first. 6. tWHZ is specified by the time when DATA output is floating, not defined by the output level. 7. When I/O pins are in the output mode, don't apply the inverted input signal to the output pins. 7/9
Semiconductor Data Retention Characteristics
Parameter Symbol Condition LB, UB VCC - 0.2 V, CE VCC - 0.2 V or 0 V CE 0.2 V, VIN = 0 to VCC VCC = 3 V, LB, UB VCC - 0.2 V, CE VCC - 0.2 V or 0 V CE 0.2 V, VIN = 0 to VCC -- -- Min. Typ.
MSM52V1017LP
(Ta = -40C to 85C) Max. Unit
Data Retention Power Supply Voltage
VCCH
2.0
--
--
V
Data Retention Power Supply Current
ICCH
--
--
40*
mA
Chip Deselect to Data Retention Time Operation Recovery Time
tCDR tR
0 50
-- --
-- --
ns ms
* 5 mA Max. when Ta = 0C to 40C. LB, UB Control
tCDR VCC 3.0 V VIH VCCH LB, UB 0V LB, UB VCC - 0.2 V Data Retention Mode tR
CE Control
Data Retention Mode VCC 3.0 V tCDR CE VCCH VIL 0V CE 0.2 V tR
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Semiconductor
MSM52V1017LP
PACKAGE DIMENSIONS
(Unit : mm)
TSOPII44-P-400-0.80-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.54 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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