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E2D0020-27-44 Semiconductor
Semiconductor MSM9810
8-channel Mixing OKI ADPCM Type Voice LSI
This version: Jan. 1998 MSM9810 Previous version: May. 1997
Pr el ar in im y
GENERAL DESCRIPTION
The MSM9810 is an 8-channel mixing voice synthesis IC, to which up to 128 Mbits of ROM and/ or EPROM storing voice data can directly be connected externally. The device is straight 8-bit PCM playback, non-linear 8-bit PCM playback, 4-bit ADPCM playback, and 4-bit ADPCM2 playback selectable and provides 2-channel stereo output and volume control. The MSM9810 contains a 14-bit D/A converter and LPF. The MSM9810 can easily configure a system by connecting voice data storage memory, power amplifier, and CPU externally.
FEATURES
* Non-linear 8-bit PCM / straight 8-bit PCM / 4-bit ADPCM / 4-bit ADPCM2 * Serial input or parallel input selectable * Built-in edit ROM function * 8-channel mixing function * Master clock frequency : 4.096 MHz * Sampling frequency : 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.7 kHz, 12.8 kHz, 16.0 kHz, 21.3 kHz, 25.6kHz, 32.0kHz * Maximum number of phrases : 256 * Output channel : L/R 2 channels * Built-in volume control function (for each output channel) * Built-in 14-bit D/A converter * Built-in low-pass filter * Package : 64-pin plastic QFP(QFP64-P-1414-0.80-BK)(Product name : MSM9810GS-BK)
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RA23
RA0
ROE
Semiconductor
BLOCK DIAGRAM
RD7
RD0
8bit LATCH D7/SD D6/SI D5/SO D4/UD D3/SR3 D2/SR2 D1/SR1 D0/SR0 CS WR RD CMD SERIAL NCR/BUSY 8 23bit MultiPlexer 8
CPU interface
DATA Controller 23bit Address Counter
ADPCM Synthesizer
PCM Synthesizer 16
TEST1 TEST2 TEST3
8
PAN ROM
16*9 MPY
XT OSC XT Timing Controller 14bit DAC 14bit DAC
MSM9810
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RESET
DVDD DGND
LDAO
AVDD AGND RDAO
Semiconductor
MSM9810
PIN CONFIGURATION (TOP VIEW)
64 RA23
63 RA22
62 RA21
61 RA20
59 RA17
58 RA16
57 RA15
56 RA14
55 RA13
54 RA12
53 RA11
52 RA10
50 RA19
49 RA18
48 DVDD 47 RA8 46 RA7 45 RA6 44 RA5 43 RA4 42 RA3 41 RA2 40 RA1 39 ROE 38 RD0 37 RD1 36 RD2 35 RD3 34 RD4 33 RD5
60 RA0
DGND AGND LDAO RDAO NC AVDD DVDD RCS TEST1
1 2 3 4 5 6 7 8 9
TEST2 10 XT 11 XT 12 TEST3 13 SERIAL 14 CMD 15 RD 16
NC 17
WR 18
NCR/BUSY 19
CS 20
D0/SR0 21
D1/SR1 22
D2/SR2 23
D3/SR3 24
D4/UD 25
D5/SO 26
D6/SI 27
D7/SD 28
RESET 29
RD7 30
54 RA9
RD6 31
NC: No connection 64-pin Plastic QFP
DGND 32
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Semiconductor
MSM9810
PIN DESCRIPTIONS
Pin 40-47, 49-64 30, 31, 33-38 39 8 Symbol RA0-RA23 RD7-RD0 ROE RCS Type O I O O when RCS pin is "H". Data pin for external memory. These pins are fixed to "L" when RCS pin is a "H". Output enable pin for external memory. When this pin is "L", RA23 to RA0 and ROE pins output data. When this pin is "H", RA23 to RA0 and ROE pins become high impedance. Command data select pin for CPU interface. 15 16 18 20 CMD RD WR CS I I I I When this pin is "H", subcomand input is selected. When this pin is "L", command input is selected. Read pin for CPU interface. Write pin for CPU interface. Chip select pin for CPU interface. When CS is "H", RD and WR signals are not entered in this IC. CPU interface select pin. When SERIAL is "H", serial input interface is 14 SERIAL I selected. When it is "L", parallel input interface is selected. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 28 D7/SD I/O When RD is "L", this pin serves as channel status data output pin. When serial input interface is selected, this pin serves as serial data input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 27 D6/SI I/O When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as serial clock input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. 26 D5/SO I/O When RD is "L", this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status output pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. When RD is "L", this pin serves as channel status output pin. 25 D4/UD I/O When serial input interface is selected, this pin serves as channel status output pin. When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively. When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively. Description Address pins for external memory. These pins become high impedance
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Semiconductor
MSM9810
Pin 24 23 22 21 3 4 11
Symbol D3/SR3 D2/SR2
Type
Description Data bus pin for CPU interface when parallel input interface is selected. When WR is "L", this pin serves as data input pin. When RD is "L", this pin serves as channel status output pin.
I/O D1/SR1 D0/SR0 LDA0 RDA0 XT O O I
When serial input interface is selected, this pin serves as channel status output pin. When UD is "H", channels 8 thru 5 are output to SR3 thru SR0, respectively. When UD is "L", channels 4 thru 1 are output to SR3 thru SR0, respectively. LEFT side D/A output pin. RIGHT side D/A output pin. X'tal or ceramic oscillator connection pin. A feedback resistor of about 1MW is connected between XT and XT. If necessary, enter external clocks into this pin. X'tal or ceramic oscillator connection pin. When external clocks are used, leave this pin open. When this pin is "L", the IC is initialized. At that time, oscillation stops and D/A outputs go to GND level. This pin has built-in resistor. Channel status select pin. When this pin is "H", NCR signal is output. When it is "L", BUSY signal is output. Pin for IC testing. Apply "L" level to this pin.
12 29
XT RESET
O I
19 9 10 13 7, 48 6 1 2
NCR/BUSY TEST1 TEST2 TEST3 DVDD AVDD DGND AGND
I
I Power supply pin. GND pin.
-- --
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Semiconductor
MSM9810
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Symbol VDD VIN TSTG Condition Ta=25C -- Rating -0.3 to +7.0 -0.3 to VDD+0.3 -55 to +150
(GND=0 V) Unit V V C
RECOMMENDED OPERATING CONDITIONS
(GND=0 V) Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Symbol VDD Top fOSC Condition -- -- -- Range 3.5 to 5.5 -40 to +85 4.096 Unit V C MHz
ELECTRICAL CHARACTERISTICS
DC Characteristics
(DVDD=AVDD=4.5 to 5.5 V, DGND=AGND=0 V, Ta=-40 to +85C) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage High-level Input Current Low-level Input Current Output Leakage Carrent Operating Current Standby Current Symbol VIH VIL VOH VOL IIH IIL ILO IDD IDS Condition -- -- IOH = -1mA IOL = 2mA VIH = VDD VIL = GND 0 VOUT VDD -- -- Min. 0.84VDD -- VDD-0.4 -- -- -10 -10 -- -- Typ. -- -- -- -- -- -- -- 6 -- Max. -- 0.16VDD -- 0.4 10 -- +10 10 10 Unit V V V V mA mA mA mA mA
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Semiconductor AC Characteristics
MSM9810
(VDD=3.5 to 5.5V, GND=0 V, Ta=-40 to +85C) Parameter Master Clock Duty Cycle RESET Input Pulse Width RESET Delay Time From Raising of Power Supply CS Set-up Time before RD Low RD Pulse Width Output Data Valid Time after Fall of RD Data Hold Time after RD High Setup and Hold Time of CMD for WR Setup and Hold Time of CS for WR WR Pulse Width Data Setup Time before Rise of WR Data Hold Time after Rise of WR CS-CS Pulse Interval Serial Data Setup Time Serial Data Hold Time Serial Clock Pulse Width Symbol Min. 40 fduty 1 tw(RST) tD(RST) 0 tCR tRR tDRE tDRF tDW tCW tWW tDWS tDWH tCC tSDS tSSD tW(SCK) 30 200 -- -- 50 30 200 100 30 100 30 30 200 Typ. 50 -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- Max. 60 -- -- -- -- 100 50 -- -- -- -- -- -- -- -- -- Unit % ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns
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Semiconductor
MSM9810
TIMING DIAGRAMS
Power on Timing
VDD tD(RST) RESET (I) tW(RST)
Data Read Timing
CS(I) tCR RD(I) tRR D7 - D0(I/O) tDRE Dataout Valid tDRF tCR
Data Write Timing
CMD(I) tDW CS(I) tCW WR(I) tWSS D7 - D0(I) Data in Stable tWW Data in Stable tDWS tDWH tCW tDW
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Semiconductor
MSM9810
FUNCTIONAL DESCRIPTION
1. User Specification Phrase A maximum of 256 phrases can be selected with user specification phrases. User specification phrases are stored in the voice management area of external ROM. Merely by selecting a phrase, sampling frequency and the start and stop address of voice are controlled. The MSM9810 can directly specify a start address or stop address externally without using user specification phrases. Only channels 1 to 4 can be used for directly specifying a start address or stop address externally. 2. Playback Time and Memory Capacity Table 2.1 shows the configuration of external ROM. The capacity of an actual voice data ROM is different from the indicated ROM capacity. Table 2.1 ROM Configuration
Address management area (16Kbits)
Voice data area or edit area
Disabled area
Playback time depends on external memory capacity, sampling frequency, and the playback system. The relationship is shown below.
Playback time = 1024 (memory capacity (Kbits) -16) Sampling frequency (kHz) bit length (Seconds)
(Bit length is ADPCM, ADPCM2...4bits, PCM...8bits)
For example, when one 8 Mbits ROM is used with a 16 kHz sampling frequency in a 4-bit ADPCM type, the playback time becomes as follows.
Playback time= 1024 (8192-16) 16 4 =130 seconds
In the above equation, the 16 Kbit memory area of the address management area is subtracted from total memory capacity. The edit function is not used.
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Semiconductor 3. Sampling Frequency
MSM9810
Sampling frequency can be specified for each phrase in the address management area of external ROM. For the sampling frequency, the following ten types can be selected when voice data is created. 4.0 kHz, 8.0 kHz, 16.0 kHz, 32.0 kHz (Group 1) 5.3 kHz, 10.6 kHz, 21.3 kHz (Group 2) 6.4 kHz, 12.8 kHz, 25.6 kHz (Group 3) When channels are synthesized, the sampling frequency group of the first vocalizing channel (one of the above groups 1 to 3) is selected. If the sampling frequency group other than the selected group is used for channel synthesis, playback becomes fast or slow. Figure 3.1 and Figure 3.2 show examples.
Channel 1 Channel 2 Channel 3 fS=16.0kHz fS=32.0kHz (Valid) fS=25.6 kHz (Invalid, playback with fS=32.0 kHz)
Table 3.1 When different sampling frequency is played back while channel 1, 2 and 3 are playing back
Channel 1 Channel 2
fS=16.0kHz fS=25.6kHz (Valid) Channel 1 ends
Table 3.2 When different sampling frequency is played back after another channel ends
When multiple channels are played back simultaneously, the sampling frequency group of the smallest channel has priority.
fS=8.0 kHz (Sampling frequency group of channel 3 is selected.) fS=25.6 kHz (Invalid, playback with fs=32.0 kHz) fS=32.0 kHz (Valid)
Channel 3 Channel 4 Channel 8
Table 3.3 When channel 3, 4 and 8 are played back simultaneously.
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Semiconductor 4. Reset Function
MSM9810
When "L" is input to the RESET pin, LSI enters power down state, stopping oscillation and minimizing current consumption. At the same time, the control circuit is reset and initialized. Power down status is as follows. (1) Oscillation stops and all internal circuits stop operation. (2) Current consumption is minimized (MAX: 1 mA). When an external clock is in use, input "L" level to the XT pin in power down status, so that current does not flow into the oscillation circuit. (3) When a crystal oscillator is in use, "L" level is output to the XT pin. (4) GND level is output to the D/A output pin (LDAO, RDAO). Be certain to input "L" level to the RESET pin when power is turned on. 5. Playback System This LSI has four types of playback systems to support various voices: 4-bit ADPCM, 4-bit ADPCM2, 8-bit straight PCM, and 8-bit non-linear PCM. 5-1 4-bit ADPCM ADPCM (Adaptive Differential Pulse Code Modulation) system adaptively changes the quantization width and encodes 4-bit data for each sampling, so that the follow up to a voice waveform improves. Conversion to ADPCM data is performed by an analysis tool. For a human voice, animal voice and natural sounds, it is better to use the ADPCM system because the voice data capacity decreases. 5-2 4-bit ADPCM2 In 4-bit ADPCM 2, the follow-up characteristics to a voice waveform is even better than the 4-bit ADPCM. This system is not compatible with other OKI voice LSIs. Conversion to ADPCM data is performed by an analysis tool. 5-3 8-bit Straight PCM The follow-up characteristics to a voice waveform to all voice areas is the best of all four types. This system is suitable for sound effects, where waveforms change rapidly, and for pulse shape waveforms. 5-4 8-bit Non-linear PCM This system plays back the center of a waveform to be a voice quality equivalent to 10 bits. This system is to improve the voice quality of low volume sounds. Conversion to an 8-bit non-linear PCM is performed by an analysis tool.
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Semiconductor 6. Voice Output
MSM9810
The voice is output as 14-bit D/A converter output in stereo (LDAO, RDAO), with L/R in phase. The output amplitude from the D/A converter has a maximum (16383/16384) VDD, and the output waveform has a step waveform synchronized with sampling frequency. The command option has been set for voice output. x4 oversampling output and voltage follower output can be selected by option. 7. Microcomputer Interface There are two types of microcomputer; one is parallel input interface and the other is serial input interface. Either of the two interfaces can be selected with the SERIAL pin. The parallel input interface is selected when SERIAL is at a "L" level. The serial input interface is selected when SERIAL is at "H" level. When the parallel input interface is selected, the MSM9810 is controlled by nine different commands using D7 to D0 (data buses) and control pins CMD, CS, WR, and RD. The internal status register is used to know the status of the IC. When the serial input interface is selected, the MSM9810 is controlled by nine different commands using serial data input pin SD and serial clock input pin SI, and control pins CMD, CS, WR, and RD. The SO, SR3, SR2, and SR1 pins are used to know the status of the IC. The pins 21 to 28 function differently according to whether the parallel input interface is selected or the serial input interface is selected. The table 7-1 shows the pin names. See "PIN DESCRIPTIONS" for their functions. Table 7-1 Difference between parallel input and serial input pins
Pin number Parallel input Serial input 21 D7 SD 22 D6 SI 23 D5 SO 24 D4 25 D3 26 D2 27 D1 28 D0
UD SR3 SR2 SR1 SR0
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Semiconductor 7-1 Parallel Input Interface
MSM9810
In the parallel input interface, the microcomputer controls the LSI via 13 pins of RESET, CMD, CS, WR, RD and D7-D0. Command and subcommand data are input from D7-D0 by control of CMD, CS and WR, as shown in Figure 7-1, and the status is output from D7-D0 by control of CS and RD, as shown in Figure 7-2.
CMD(I) tDW CS(I) tCW WR(I) tWSS D7 - D0(I) Data in Stable tWW Data in Stable tDWS tDWH tCW tDW
Figure 7-1 Parallel input write cycle timing
CS(I) tCR RD(I) tRR D7 - D0(I/O) tDRE Dataout Valid tDRF tCR
Figure 7-2 Parallel input read cycle timing
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Semiconductor 7-2 Serial Input Interface
MSM9810
In the serial input interface, the microcomputer controls the LSI via 8 pins of RESET, CMD, CS, WR, RD, SD, SI and SO. In parallel input, data is output from D7-D0, but in serial input, data for D7-D0 is input in serial from MSB using SD and SI. Figure 7-3 shows the command and subcommand input timing, and Figure 7-4 shows read timing.
CMD(I) tDW tCC CS(I) tCW WR(I) tCW tDW
SD(I) tSDS SI(I) tW(SCK) tSSD
Figure 7-3 Serial input write cycle timing
CS(I) tCR RD(I) tCR
SO(I) SI(I)
Figure 7-4 Serial input read cycle timing
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Semiconductor 8. Channel Status
MSM9810
There are two types of signals to be output as channel status: BUSYn (n = 1-8) signals and NCRn signals. These two types are selected by the NCR/BUSY pin. When the NCR/BUSY pin is at "H" level, NCR is output, and when at "L" level, BUSY is output. The NCR signal is the command and subcommand input status signal (Next Command Request) of each channel, and the WR signal input is enabled at "H" level. The BUSY signal outputs "L" level while each channel is executing voice synthesis. Each channel status signal is output from D7-D0 pins in parallel input interface, and from D5/ S0 pins and D3/SR3-D0/SR0 pins in serial input interface by control of CS and RD. Table 8-1 shows the relationship between D7-D0 and channels, and Figure 8-1 shows read timing in the parallel input interface.
Data bus D7 D6 D5 D4 D3 D2 D1 D0
Corresponding channel CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
Table 8-1 Correspondence between D7-D0 and channels
CS(I) tCR RD(I) tRR D7 - D0(I/O) tDRE Dataout Valid tDRF tCR
Figure 8-1 Read timing in parallel input interface In serial input interface, serial output from D5/SO pins by control of CS and RD, and D3/SR3D0/SR0 parallel output (constantly output) can be selected. For serial output from D5/S0 pin, D7-D0, shown in Table 8-1, are output from MSB in serial at the rise of the SI pin when the RD pin is at "L" level. Figure 8-2 shows this timing.
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Semiconductor
RD(I)
MSM9810
SI(I) SO(O)
D7 D6 D5 D4 D3 D2 D1 D0 Status signal is output in serial at rise of SI
Figure 8-2 Read timing in serial input interface In serial input interface, status signals are constantly output from D3/SR3 to D0/SR0 pins. Selection of NCR and BUSY is controlled by the NCR/BUSY pin. Since there are only four D3/ SR3 to D0/SR0 pins, 8 channels of status signals are selected by control of the D4/UD pin. Table 8-2 shows the relationship between D4/UD pin and D3/SR3 to D0/SR0 pins.
D4/UD="L" D3/SR3 D2/SR2 D1/SR1 D0/SR0 Channel 4 Channel 3 Channel 2 Channel 1
D4/UD="H" Channel 8 Channel 7 Channel 6 Channel 5
Table 8-2 Correspondence between D4/UD and D3/SR3 to D0/SR0
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Semiconductor 9. Command Data and Subcommand Data
MSM9810
In parallel input, command data and subcommand data are controlled by the data bus of D7-D0 pins and by CMD, CS and WR control pins. In serial input, command data and subcommand data are controlled by data input/output of SD, SI and S0 pins and by CMD, CS and WR control pins. This LSI reads data to the internal register (TMP register) by executing the subcommand, and transfers data of the TMP register to the register of each command function and executes data by executing the command. A subcommand and command are distinguished by the level of the CMD pin. "H" level indicates a subcommand, and "L" level indicates a command. Table 9-1 shows the command data list, Table 9-2 shows details of C2-C0 of Table 9-1 (channel specification), and Table 9-3 shows subcommand data list corresponding to command data.
1 2 3 4 5 6 7 8 9
START STOP LOOP OPT MUON FADR DADR CVOL PAN
Function D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 X X X Starts playack of the channel for which data stored in the register is "H". 0 0 0 0 1 X X X Stops playback of channel for which data stored in the register is "H". 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 10 11 X X X X Repeats playback of channel for which data stored in the regiter is "H". X X Changes option by command.
0 0 C2 C1 C0 Inserts silence corresponding to the length of data stored in the register. 0 1 C2 C1 C0 Transfers phrase address stored in the register to the phrase register of the specified channel. 1 0 C2 C1 C0 Transfers the 4-byte start and stop address stored in the register to the start and stop address registers of the specified channel. 1 1 C2 C1 C0 Changes volume of the specified channel to the volume of data stored in the register. 0 0 C2 C1 C0 Changes volume of the right and left D/A converter to volume of data stored in the register.
(X - - - don't care. For C1, C2 and C0, see Table 9-2.) Table 9-1 Command Data List
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Semiconductor
MSM9810
C2 C1 C0 000 00 01 01 10 10 11 11 1 0 1 0 1 0 1
Channel control Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8
Table 9-2 Channel Specification List
Command START STOP LOOP OPT MUON FADR DADR
D7 CH8 CH8 CH8 X M7 FA7
D6 CH7 CH7 CH7 X M6 FA6
D5 CH6 CH6 CH6 X M5 FA5
D4 CH5 CH5 CH5 X M4 FA4
D3 CH4 CH4 CH4 O3 M3 FA3
D2 CH3 CH3 CH3 O2 M2 FA2
D1 CH2 CH2 CH2 O1 M1 FA1
D0 CH1 CH1 CH1 O0 M0 FA0
Subcommand funciton Channel setting Channel setting Channel setting Option setting Silence time setting Phrase address setting (1st byte) address setting (2nd byte) (3nd byte) (4nd byte) (5nd byte) (6nd byte) (7nd byte) Volume setting Volume setting
SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 ST23 ST22 ST21 ST20 ST19 ST18 ST17 ST16 ST15 ST14 ST13 ST12 ST11 ST10 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 S3 S2 X L2 S1 X L1 S0 X L0 P1 V3 R3 P0 V2 R2 X V1 R1 X V0 R0
CVOL PAN
X L3
(X - - - don't care.) Table 9-3 Subcommand Data List
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Semiconductor 9-1 START Command
MSM9810
The START command starts voice synthesis of the channel corresponding to the data stored in the TMP register. Table 9-4 shows the correspondence between data input (D7-D0) and channels. For serial input, the sequence of D7-D0 and serial input data is shown in Figure 8-2.
Data bus D7 D6 D5 D4 D3 D2 D1 D0
Corresponding channel CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
Table 9-4 Correspondence between D7-D0 and Channels When the START command is input, data stored in the TMP register is set at the start register, and voice synthesis processing starts. For example, when all " 1" is written from the data bus to the TMP register and the START command is input, all channels start voice synthesis simultaneously. Input the START command when the status signal (NCR or BUSY) of the channel to be started is at "H". When NCR is "L", input is disabled. Figure 9-1 shows the flowchart when the START command is input.
RD pulse input NO
NCRn corresponding to each channel is output to D7-D0 Check that D7-D0 corresponding to the channel to start voice synthesis is "H".
NCRn="H" YES Subcommand input START command input
After setting "H" to D7-D0 corresponding to the channel to start voice synthesis from the data bus, input the WR pulse. (Set CMD to "H".)
Figure 9-1 START Command Input Flow 9-2 STOP Command
The STOP command stops voice synthesis processing of the channel corresponding to data stored in the TMP register. Table 9-5 shows the correspondence between data input (D7-D0) and channels.
Data bus D7 D6 D5 D4 D3 D2 D1 D0
Corresponding channel CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
Table 9-5 Correspondence between D7-D0 and channels
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Semiconductor
MSM9810
When the STOP command is input, the LSI stops processing of voice synthesis of the corresponding channel at the rise of the WR pulse. When voice synthesis stops, the PCM value of that channel is cleared to 1/2 VDD, and the NCR and BUSY channel status signals become "H". When "H" has been set at the START register, the START register is cleared to "L". 9-3 LOOP Command
The LOOP command repeats a playback of voice synthesis of the channel corresponding to data stored in the TMP registers. Table 9-6 shows the correspondence between data input (D7-D0) and channels.
Data bus D7 D6 D5 D4 D3 D2 D1 D0
Corresponding channel CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
Table 9-6 Correspondence between D7-D0 and channels When the LOOP command is input, the LSI writes data of the TMP register to the LOOP register at rise of WR pulse, and repeats a playback of the channel where "H" is set. Once "H" is set at the LOOP register, playback continues until "L" is set from the outside. If the edit function has been used for a phrase address, the edited voice is repeatedly played back. To end a repeating playback, set the register of the channel to end the repeat to "L" using the LOOP command again. When the register is set to "L", repeating ends with the current playback phrase. If the START register has been set to continue the playback of another phrase, another phrase is played back continuously after repeating ends. Figure 9-2 shows an example.
Channel 1 1 phrase 1 phrase 1 phrase 2 phrase
LOOP start
LOOP end
Figure 9-2 LOOP Command Execution Example
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Semiconductor 9-4 OPT Command
MSM9810
The OPT command changes the setting inside the LSI according to data stored in the TMP register. Table 9-7 shows the correspondence between data input (D7 to D0) and options.
D4 D3 0 0 1 1 0 1 0 1 D2 0 1 D1 0 1 D0 0 1 Option Sets volume of all channels to VDD(P-P). Sets volume of all channels to 1/2VDD(P-P). Sets volume of all channels to 1/4VDD(P-P). Sets volume of all channels to 1/8VDD(P-P). Option Executes oversampling. Does not execute oversampling. Option Executes 2nd oversampling. Executes 1st oversampling. Option Output via a voltage follower. Output directly from the D/A converter.
(Input "L" to D7-D4.) Table 9-7 Correspondence between D7-D0 and options When the OPT command is input, the LSI changes the option at the rising edge of the WR pulse. When power is turned on, or when the RESET pulse is input, the registers corresponding to D3D0 have been set to "L". If the option is changed when voice synthesis is in execution, voice quality may change. Oki recommends to set the option after power is turned on or after RESET is input. 1) Volume Option Volume can be set by the CVOL command and PAN command, but a waveform may be clamped when channel synthesis is executed. If the CVOL command and PAN command are used to prevent a waveform from being clamped, the number of steps used for actual volume decreases, and effective voice synthesis may not be performed. If it is known that a waveform will be clamped, this option can set the volume of all channels to low, so that the number of steps of the volume can be utilized to the maximum level. 2) Oversampling This LSI has a built-in oversampling circuit. This oversampling system evenly generates four times more points of sampling frequencies. When power is turned on or if the RESET pulse is input, those pulses have been set to pass through the oversampling circuit. If oversampling is unnecessary, change this setting by the OPT command.
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Semiconductor
MSM9810
3) Analog Output When power is turned on, it has been set that the output of the D/A converter is output via the voltage follower. To change this setting, use the OPT command. The output impedance of analog signals being output via the voltage follower is about 500W. The output impedance of analog signals directly output from the D/A converter is about 30kW. 9-5 MUON Command The MUON command inserts silence into the specified channel at the rise of the WR pulse. The length of silence is according to the size of data stored in the TMP register. The length of silence data is input in advance, before executing the MUON command. Silence length can be set for 255 steps, 4 ms to 1024 ms, in 4 ms intervals. Silence time can be set as follows. tmu = (27 (D7) + 26 (D6) + 25 (D5) + 24 (D4) + 23 (D3) + 22 (D2) + 21 (D1) + 20 (D0) 4.096 ms The operation of the MUON command is similar to the START command to start voice synthesis. When the MUON command is input, "H" is set to the START register, and NCR and BUSY signals becomes "L". If the MUON command is input when voice synthesis is in execution, silence time is inserted after voice synthesis ends. Input the MUON command when the status signal (NCR or BUSY) of the channel to start voice synthesis is at "H". When NCR is "L", input is disabled. Figure 9-3 shows a flow chart example when the MUON command is input.
RD pulse input NO
NCRn corresponding to each channel is output to D7-D0. Check that D7-D0 corresponding to the channel to insert silence is "H".
NCRn="H" YES Subcommand input MUON command input
After setting time of inserting silence from the data bus, input WR pulse (set CMD to "H"). Specify channel by silence command.
Figure 9-3 MUON Command Input Flow
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Semiconductor 9-6 FADR Command
MSM9810
The FADR command transfers data stored in the TMP register to the phrase address register of the corresponding channel at the rise of the WR pulse. For the phrase address, the user specification phrases have been set by an analysis tool, and the playback system, sampling frequency and start and stop address of voice data have been registered to the address management area. When the phrase address is set and the START command is input, the LSI reads data of the address management area, and starts voice synthesis. Since the phrase address is set by D7-D0, a maximum of 256 phrases can be set. The edit function can be used for phrase addresses, so not only one phrase but combinations with other phrases are possible. 9-7 DADR Command The DADR command transfers data stored in the TMP (1-7) register to the start and stop address register of the corresponding channel at the rise of the WR pulse. For the direct address, the playback system, sampling frequency, and start and stop address of voice data is directly input from the microcomputer without using the address management area. Direct address playback system is available with channel 1 to 4, and not available with channel 5 to 8. Since the phrases that can be set at a phrase address is a maximum of 256, if voice data exceeds 256 phrases, use this command. Data on the playback system, sampling frequency, and start and stop address of voice data is displayed when an analysis tool is used. Data on the playback system, sampling frequency, and start and stop address of voice data is input to the TMP1 to TMP7 registers divided in 7 steps, unlike the data input of other commands. Figure 9-4 shows the input method.
CMD(I)
CS(I)
WR(I)
D7 - D0(I) Stores TMP1 Stores TMP3 Stores TMP7 Stores TMP5 register data register data register data register data Stores TMP6 Stores TMP2 Stores TMP4 Executes command register data register data register data
Figure 9-4 DADR Input Timing 23/27
Semiconductor
MSM9810
As Figure 9-4 shows, CS and WR pulses are input 7 times when CMD is in "H" status, to input data to the TMP1 to TMP7 registers. The LSI increments the registers at the rise of the WR pulse when CMD is "H". CMD must not be "L" while inputting data. When CMD becomes "L" while inputting data, the increment of registers is cleared. Table 9-8 shows the configuration of data to be input to TMP1 to TMP7 registers.
D7 TMP1 register TMP2 register TMP3 register TMP4 register TMP5 register TMP6 register TMP7 register
D6
D5
D4
D3
D2
D1 A9 A1 T17 T9 T1 0
D0 A8 A0 T16 T8 T0 0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A7 T23 T15 T7 S3 A6 T22 T14 T6 S2 A5 T21 T13 T5 S1 A4 T20 T12 T4 S0 A3 T19 T11 T3 P1 A2 T18 T10 T2 P0
Table 9-8 TMP Register Data Configuration Input the start address of voice data to TMP1 to TMP3 registers. Input the stop address of voice data to TMP4 to TMP6 registers. Input the playback system and sampling frequency to the TMP7 register. Table 9-9 shows the input data configuration of the playback system and sampling frequency.
S3 S2 S1 S0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 Sampling frequency 4.0kHz Sampling frequency 8.0kHz Sampling frequency 16.0kHz Sampling frequency 32.0kHz Sampling frequency 6.4kHz Sampling frequency 12.8kHz Sampling frequency 25.6kHz Sampling frequency 5.3kHz Sampling frequency 10.6kHz Sampling frequency 21.3kHz
P1 P0 0 0 1 1 0 1 0 1 Playback system: 4-bit ADPCM Playback system: 4-bit ADPCM2 Playback system: 8-bit non-linearPCM Playback system: 8-bit straight PCM
Table 9-9 Data Configuration of Playback System and Sampling Frequency
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Semiconductor 9-8 CVOL Command
MSM9810
The CVOL command adjusts the volume of the specified channel to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. Volume can be set in 16 steps up to -30 dB in -2dB step units. Set data as shown in Table 9-10.
D3 D2 D1 D0 Volume (dB) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB
(D7-D4 : Don't care) Table 9-10 Volume Setting Data Configuration When power is turned on and the RESET pulse is input, all channels are set to 0dB.
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Semiconductor 9-9 PAN Command
MSM9810
The PAN command adjusts the volume of the specified channel for the left and right respectively, to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. This command enables stereo output. When volume is controlled by the OPT command and CVOL command, volume to be output is the volume stored in ROM multiplied by volume set by the OPT command, CVOL command, and PAN command respectively. This volume is output from LDAO and RDAO. Volume can be set in 16 steps up to -30 dB in -2 dB step units. Set data as shown in Table 9-11.
Volume at left side D3 D2 D1 D0 Volume at right side 0dB 0000 -2dB 0001 D7 D6 D5 D4 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -22dB -24dB -26dB -28dB -30dB
Table 9-11 PAN Data Configuration
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Semiconductor
MSM9810
PACKAGE DIMENSIONS
(Unit : mm)
QFP64-P-1414-0.80-BK
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.87 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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