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LSIs for MPEG
MN85560
MPEG2 Video Encoder
I Overview
The MN85560 is an MPEG2 video encoder that outputs encoded data that conform to the ISO/IEC 1318-2 (MPEG2 video) Main Profile@Main Level and ISO/IEC 1172-2 (MPEG1 video) standards.
I Features
* Incorporates the image input filters used for front-end processing. * Supports PAL size images with just two external 16M synchronous DRAMs (SDRAM). * The back-end code output buffer is allocated in SDRAM and can be controlled from microcode. * Provides image quality improvement functions: * Multiple-mode high-performance motion vector detection * Original rate control techniques implemented in microcode * Intra-slice functions for low delay modes and PES output to reduce the system encoding load * Clock input * Three clocks: system clock SCLK (27 MHz), video input clock VCLK, and code output clock RCLK. * An internal PLL circuit is used to generate an 81 MHz clock from SCLK (27 MHz). This clock is used for internal circuits and the synchronous DRAM. * Supply voltages: 3.3 V (I/O supply voltage and internal PLL circuit supply voltage) 1.8 V (internal circuit supply voltage)
I Applications
* DVD recorders, multimedia personal computers, MPEG2 cameras etc.
1
MN85560
I Block Diagram
exec, end parameters
code code
VRBM
LSIs for MPEG
bit count
VWBM
VLC
QVDM
instructions/exec, end
HIF/CIF
operands/parameters
quant. MB
rec Y,C
ROBM
MDDM MRDM
DCTQ
CBP exec, end parameters
control signal
HIF/CIF
32
[SDRAM I/F (16 M-bit SDRAM(16 bit) ) x 2]
MDQ
32
diff. / curr. Y,C reference Y,C
SMBM
MA
nomcMB Y
12
MYDM MCDM ZMBM
sum
MSP
MIF
operands
SDRAM control signal
SMBM
reference Y reference C mv, sae
MCBM
ME2
reference C reference Y
SMBM
exec, end
greg
MCLKIN
SMBM
MYBM
parameters
@81 MHz
MCLK
MSBM
reference Y source Y, C
ME1
SMBM
exec, end parameters
SMBM
field end vsync, fsync, hcnt
DM
VIF
parameters
@27 MHz (max.)
8
@27 MHz
VCLK
PLL control signal
SCLK
IRAM
[Digital Video I/F] 2
(81 MHz)
VIN
NRST
4 : 2 : 0 Y, C
freg
core-reg
mv, sae
ERISC
HD
instructions, end
[Host & Code out I/F]
@33 MHz (max.)
RCLK
Memory Register
core
LSIs for MPEG
I Pin Assignment
GND 3.3 V-VDD MDQ17 MDQ16 GND MDQ15 MDQ14 3.3 V-VDD 1.8 V-VDD MDQ13 MDQ12 GND MDQ11 MDQ10 3.3 V-VDD MDQ9 MDQ8 GND MDQ7 MDQ6 1.8 V-VDD 3.3 V-VDD MDQ5 MDQ4 GND MDQ3 MDQ2 3.3 V-VDD MDQ1 MDQ0 GND NRST BUSY NHINT 1.8 V-VDD 3.3 V-VDD HSTMD NHDACK NRE *1 NHDREQ GND RCLK NHDS NHCS NHAS HRW 1.8 V-VDD 3.3 V-VDD HA3 HA2 HA1 HA0 GND
MN85560
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
GND GND MNTMD MDQ18 MDQ19 3.3 V-VDD MDQ20 MDQ21 1.8 V-VDD GND MDQ22 MDQ23 3.3 V-VDD MDQ24 MDQ25 GND MDQM NMWE 3.3 V-VDD NMCS 1.8 V-VDD MCLKIN GND NMRAS NMCAS 3.3 V-VDD MCLK GND MDQ26 MDQ27 1.8 V-VDD 3.3 V-VDD MDQ28 MDQ29 GND MDQ30 MDQ31 3.3 V-VDD MA0 MA1 GND MA2 MA3 1.8 V-VDD 3.3 V-VDD MA4 MA5 GND MSOE TMIN 3.3 V-VDD GND
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
GND 3.3 V-VDD HD31 HD30 GND HD29 HD28 3.3 V-VDD 1.8 V-VDD HD27 HD26 GND HD25 HD24 3.3 V-VDD HD23 HD22 GND HD21 HD20 1.8 V-VDD 3.3 V-VDD HD19 HD18 GND HD17 HD16 3.3 V-VDD HD15 HD14 GND HD13 HD12 1.8 V-VDD 3.3 V-VDD HD11 HD10 GND HD9 HD8 3.3 V-VDD HD7 HD6 GND 1.8V-VDD HD5 HD4 3.3 V-VDD HD3 HD2 GND GND
NEMPTY *1 8 bit CIF *1 8 bit CIF *1 8 bit CIF *1 8 bit CIF *1 8 bit CIF *1 8 bit CIF *1 8 bit CIF *1 8/1 bit CIF *1
Note) *1: Pins names shown in italic refer to CIF serial mode pins.
GND MA6 MA7 3.3 V-VDD MA8 MA9 1.8 V-VDD GND MA10 MA11 3.3 V-VDD VIN0 VIN1 VIN2 VIN3 GND VIN4 VIN5 VIN6 VIN7 3.3 V-VDD 1.8 V-VDD VCLK GND AGND TCPOUT AVDD PLLAS GND NPLLRSET GND SCLK 1.8 V-VDD 3.3 V-VDD RSVD GND SCMOD SCCTL OPRND0 3.3 V-VDD OPRND1 OPRND2 GND 1.8 V-VDD HD0 HD1 3.3 V-VDD TEST1 PLLTEST MINTC MINTIN GND
(TOP VIEW)
3
MN85560
I Pin Functions
Pin No. SCLK VCLK RCLK NRST VIN[7 : 0] MCLK MCLKIN NMCS NMRAS NMCAS NMWE MDQM MA[11 : 0] MDQ[31 : MSOE 0]*4 I/O I I I I I O I O O O O O O I/O I
Output at reset Number
LSIs for MPEG
Function System clock Video input clock Code output clock (Used in single-bus parallel mode and serial mode.) Chip initialization reset input signal Video input Clock output*1 for external memory (SDRAM) Transfer clock input*1 between external memory/MN85560 Chip select output for external memory (SDRAM) RAS output for external memory (SDRAM) CAS output for external memory (SDRAM) Write enable output for external memory (SDRAM) Data I/O buffer control for external memory (SDRAM) Address output for external memory (SDRAM) Data I/O for external memory (SDRAM) OE control for external memory (SDRAM) (0: MDQ (I/O) are set to input mode and the SDRAM output pins are set to the high-impedance state.) Host interface address signals Host interface read/write signal Host interface address strobe Host interface chip select signal Host interface data strobe DMA transfer request signal Code output enable signal Host interface interrupt generation notification signal Host interface mode (1 : 32-bit hostmode, 0 : 16-bit hostmode) Host interface data I/O At HSTMD = 1: HD[31:16] function in input mode At HSTMD = 0: HD[31:16] function in output mode) (At reset, HD16 functions as the 1-bit CIF output, and HD24: empty)
clock*3 "H" *3 "H" "H" "H" "H"
*3 *3 *3 *3 *3 *3
1 1 1 1 8 1 1 1 1 1 1 1 12 32 1
all "L" all "H"
HA[3 : 0] HRW NHAS NHCS NHDS NHDREQ NHDACK NHINT HSTMD HD[15 : 0] HD[31 : 16]
I I I I I O I O I I*2/O I*2/O O* 2
"H" "H" all "L"
4 1 1 1 1 1 1 1 1 16 16
Note) *1: MCLK and MCLKIN should be connected externally with a delay of 1 ns or less. *2: The bold notation in the HD pin I/O column indicates the I/O state immediately following a chip reset. *3: Items in italic indicate values immediately after a chip reset when MSOE is high. *4: The MD[31:0] values (all high) immediately following a chip reset are due to these lines being pulled up internally in the IC. Therefore, no problems will occur if the SDRAM is driving MD[31:0].
4
LSIs for MPEG
I Pin Functions (continued)
Pin No. OPRND[2 : 0] SCMOD SCCTL BUSY TEST1 MNTMD TMIN MINTC MINTIN RSVD PLLAS NPLLRSET TCPOUT PLLTEST AVDD AGND I/O O I I O I I I I I I I I O I I I
Output at reset Number
MN85560
Function open Must be held low. Must be held low. Chip status output signal Must be held low. Must be held low. Must be held low. Must be held low. Must be held low. Must be held low. PLL assert input signal (1: The PLL circuit operates. 0: The PLL circuit is stopped.) PLL reset input signal open Must be held low. PLL power supply PLL ground
"L"
3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
5
MN85560
I Architecture
* Chip State Transitions
LSIs for MPEG
The MN85560 has three internal states: run, hold, and slave. In the run state, the MN85560 executes microcode, in the hold state, it does not execute microcode, and in the slave state, it does not execute microcode and allows all of its internal resources to be accessed. The registers that are mapped to direct addresses can be read or written in any of these states. Resources that are mapped to indirect addresses can only be accessed when the MN85560 is in the slave state. The only exception to this is hifreg0 to hifreg5, which can be accessed in the run state. The indirectly addressed resources cannot be accessed in the hold state. In addition to the above three states, the chip also has a reset state which is a chip initialization state. There are two techniques for switching the MN85560 to the reset state: hardware reset using the NRST pin, and software reset using the direct address registers. During a hardware reset, none of the internal resources can be read or written. During a software reset, only the CHIPCTL0 direct address register can be written. Figure 1 shows the MN85560 chip state transition diagram.
Reset state:
Chip initialization state.
RUN POWER ON
Hold state:
Chip inactive state (BUSY = 0)
Slave state: BUSY = 0 unkown NRST = L NRST = H and CHIPCTL0 soft reset = 0 RESET NRST= L or CHIPCTL0 soft reset = 1 CHIPCTL0 slave en = 1 CHIPCTL0 slave en = 0 HOLD CHIPCTL0 erisc en (auto clear) or CHIPCTL0 erisc stop (auto clear)*1
Internal resources accessible state (BUSY = 0)
Run state:
Chip active state (BUSY = 1)
When the BUSY pin is low:
This indicates that the chip is in an inactive state. This is equivalent to the whole core, including the scheduler and the ERISC block, being in the inactive state. (Note that this does not apply to the SDRAM refresh operation.)
CHIPCTL0:
Chip control register This is one of the direct address registers.
SLAVE
*1 : After BUSY goes low, external access is allowed. After an erisc stop, you should set once the chip to the reset state. (This is because the internal state is not guaranteed.)
Figure 1. Chip State Transition Diagram
6
LSIs for MPEG
I Architecture (continued)
* Chip State Transitions (continued)
MN85560
The slave state is a state in which the external circuit can read and write instruction memory (IRAM), data memory (DM), and the global registers. This state is mainly used for downloading microcode, encoding parameters, and other data. After reading out instruction memory (IRAM), for example to verify program download, you should reset the MN85560. In particular, you should switch the MN85560 from the slave to the hold state and then set it to the reset state. Then you should return the MN85560 to the hold state. After applying power, supplying the clock, and starting the PLL oscillator with the prescribed procedure, the MN85560 can be set to the reset state by asserting the NRST pin (hardware reset). Alternatively, you may switch the MN85560 from the hold state to the reset state by setting the direct address register CHIPCTL0[0] (soft reset) to 1 (software reset). Note that the contents of direct address register CHIPCTL0 are not reset after a software reset. After a hardware reset, the MN85560 is switched from the reset state to the hold state by negating the NRST pin. After a software reset, this is performed by setting direct address register CHIPCTL0[0] (soft reset) to 0. The MN85560 is switched from the hold state to the slave state by setting direct address register CHIPCTL0[1] (slave en) to 1. You should perform the following register initializations when the MN85560 is in the slave state. Indirect address resource initreg0 ($1309A) = $0000 Indirect address resource initreg1 ($1309B) = $00c0 Note that these values return to the default values when the MN85560 switches to the reset state. This means that they must be set back to the above values. The MN85560 is switched from the slave state to the hold state by setting direct address register CHIPCTL0[1] (slave en) to 0. The MN85560 is switched from the hold state to the run state by setting direct address register CHIPCTL0[4] (erisc en) to 1. Note that erisc en is automatically cleared to 0 immediately after it is set. The transition from the run state to the hold state occurs automatically when microcode execution completes and operation of all MN85560 blocks (see the block diagram) terminates except for SDRAM refresh operations. At this point the BUSY pin will go to the low level. Alternatively, the MN85560 can be forcibly switched from the run state to the hold state by setting direct address register CHIPCTL0[5] (erisc stop) to 1. In this case, after the processing being performed by all blocks that were executing when CHIPCTL0[5] (erisc stop) was set to 1 completes, the BUSY pin goes low and the MN85560 switches to the hold state. Note that erisc stop is automatically cleared to 0 immediately after it is set to 1. If the MN85560 is forcibly switched to the hold state, we recommend that you set the MN85560 to the reset state, and then set it to the slave state and once again download the microcode, encoding parameters, and other settings before executing another encode operation. This is because the states of the internal resources cannot be guaranteed in this case. SDRAM refresh is started by executing the startup sequence using microcode. After that, the MN85560 continues to manage the number refresh operations regardless of whether it is in the run, hold or slave state. Since refresh operations are stopped in the reset state, you should restart the refresh operation by running the microcode that starts the refresh operation again.
7
MN85560
I Electrical Characteristics
1. Absolute Maximum Ratings Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Input voltage Output voltage Average output current Power dissipation Operating temperature Storage temperature Symbol VDD VDDI AVDD VI VO IO PD Topr Tstg Conditions - 0.3 to +4.6 - 0.3 to +3.6 - 0.3 to +4.6 - 0.3 to VDD + 0.3 (Upper limit: 4.6) - 0.3 to VDD + 0.3 (Upper limit: 4.6) 24 3.3 (layer 4) 0 to +70 -40 to +125
LSIs for MPEG
Unit V V V V V mA W C C
Note) 1. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. All of the VDD and VSS pins must directly connected to the power supply or ground, respectively. 3. Insert bypass capacitors of at least 0.1 F between the VDD and VSS pins as close as possible to the IC itself. 4. Power should be applied in the order first the 3.3 V system (VDD and AVDD ) and then the 1.8 V system (VDDI). Power should be turned off in the order first the 1.8 V system (VDDI) and the 3.3 V system (VDD and AVDD ).
2. Recommended Operating Conditions at Ta = 0C to 70C, VSS = 0 V, AVSS = 0 V Parameter Supply voltage 1 Supply voltage 2 Supply voltage 3 Ambient temperature System clock frequency Symbol VDD VDDI AVDD Ta SCLK VDD = 3.0 V to 3.6 V AVDD = 3.0 V to 3.6 V DUTY : 50% 10% VDD = 3.0 V to 3.6 V DUTY : 50% 10% VDD = 3.0 V to 3.6 V DUTY : 50% 10% Conditions Min 3.0 1.65 3.0 0 Typ 3.3 1.80 3.3 Max 3.6 1.95 3.6 70 27.0 Unit V V V C MHz
System clock frequency System clock frequency
VCLK RCLK

27.0 33.0
MHz MHz
8
LSIs for MPEG
I Electrical Characteristics (continued)
3. DC Characteristics at Ta = 0C to 70C, VSS = 0 V, AVSS = 0 V, VDD = 3.0 V to 3.6 V, VDDI = 1.65 V to 1.95 V, AVDD = 3.0 V to 3.6 V Parameter Operating current drain Symbol IDDO Conditions VI = VDD or VSS SCLK = 27.0 MHz VCLK = 27.0 MHz RCLK = 40.5 MHz With output pins open. Min Typ
MN85560
Max VDDI 750 VDD 90
Unit mA mA
Input pins (TTL level)
: SCLK, VCLK, RCLK, NRST, VIN7 to VIN0, MCLKIN, MSOE, HA3 to HA0, HRW, NHAS, NHCS, NHDS, NHDACK, HSTMD, SCMOD, SCCTL, TEST1, MNTMD, MINTC, MINTIN, PLLAS, NPLLRSET, PLLTEST, RSVD
High-level input voltage Low-level input voltage Input leakage current Input pins (LVCMOS) High-level input voltage Low-level input voltage Input leakage current Pull-down resistance Input pins (LVCMOS) High-level input voltage Low-level input voltage Input leakage current Output pins (LVTTL) : TMIN
VIH VIL ILI VI = VDD or VSS VDD = 3.3 V 0.3 V
2.0 0 -5

VDD 0.8 5
V V A
VIH VIL ILI RIL : MINTC, MINTIN VIH VIL ILI VI = VDD or VSS VI = VSS VI = VDD
VDD x 0.7 0 -10 10
30
VDD VDD x 0.3 10 90
V V mA k
VDD x 0.7 0 -5

VDD VDD x 0.3 5
V V A
: MCLK, NMCS, NMRAS, NMCAS, NMWE, MDQM, MA11 to MA0, NHDREQ, NHINT, OPRND2 to OPRND0, BUSY VOH VOL IOZ : MDQ31 to MDQ0 VIH VIL VOH VOL IOZ RIH IO = -8.0 mA IO = 8.0 mA VO: high-impedance state VO = VDD VI = VSS 2.0 0 2.4 -10 10 30 VDD 0.8 0.4 10 90 V V V V A k IO = -8.0 mA IO = 8.0 mA VO: high-impedance state VO = VDD or VSS 2.4 -5 0.4 5 V V mA
High-level output voltage Low-level output voltage Output leakage current I/O pins (LVTTL) High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current Pull-up resistance
9
MN85560
I Electrical Characteristics (continued)
LSIs for MPEG
3. DC Characteristics at Ta = 0C to 70C, VSS = 0 V, AVSS = 0 V, VDD = 3.0 V to 3.6 V, VDDI = 1.65 V to 1.95 V, AVDD = 3.0 V to 3.6 V Parameter Input pins (LVTTL) High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current Symbol : HD31 to HD0 VIH VIL VOH VOL IOZ IO = -8.0 mA IO = 8.0 mA VO: high-impedance state VO = VDD or VSS 2.0 0 2.4 -5 VDD 0.8 0.4 5 V V V V A Conditions Min Typ Max Unit
10
LSIs for MPEG
I Electrical Characteristics (continued) 4. AC Characteristics
The signal reference level for AC characteristics measurement is 1.4 V as shown in the figure. Clock signal period High-level period VIH 1.4 V VIL setup VIH Input signal 1.4 V VIL delay VOH Output signal 1.4 V VOL hold Low-level period
MN85560
hold
Note) The AC characteristics are values for the case where the internal PLL circuit is used to supply a 27 MHz clock signal to the SCLK pin, and to provide 27 MHz and 33 MHz signals to the VCLK and RCLK pins, respectively. Note that the AC characteristics values may differ when this IC is used under conditions other than those described above.
* Timing Charts VCLK
tsu(VIN) valid
th(VIN) valid
VIN7-VIN0
Parameter VIN7:0 setup time to the VCLK rising edge VIN7:0 hold time to the VCLK rising edge
Symbol tsu(VIN) th(VIN)
Min 10.0 1.0
Typ
Max
Unit ns ns
11
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter MCLK cycle time MCLK high-level pulse width MCLK low-level pulse width NMCS setup time to the MCLK rising edge NMCS hold time from the MCLK rising edge NMRAS setup time to the MCLK rising edge NMRAS hold time from the MCLK rising edge NMCAS setup time to the MCLK rising edge NMCAS hold time from the MCLK rising edge NMWE setup time to the MCLK rising edge NMWE hold time from the MCLK rising edge MA11-0 setup time to the MCLK rising edge MA11-0 hold time from the MCLK rising edge MDQM setup time to the MCLK rising edge MDQM hold time from the MCLK rising edge MDQ31-0 setup time to the MCLK rising edge MDQ31-0 hold time from the MCLK rising edge MCLKIN cycle time MCLKIN high-level pulse width MCLKIN low-level pulse width MCLKIN rising edge delay from the MCLK rising edge MDQ31:0 setup time to the MCLK rising edge MDQ31:0 hold time from the MCLK rising edge Symbol tc(MCK) tw(MCKH) tw(MCKL) tsu(NMC) th(NMC) tsu(NMRA) th(NMRA) tsu(NMCA) th(NMCA) tsu(NMWE) th(NMWE) tsu(MA) th(MA) tsu(MDQM) th(MDQM) tsu(MDQ-MCK) th(MDQ-MCK) tc(MCKI) tw(MCKIH) tw(MCKIL) td(MCK-MCKI) tsu(MDQ-MCKI) th(MDQ-MCKI) Min 3.5 3.5 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.0 2.0 3.5 3.5 0 2.0 2.0 Typ 12.3 12.3
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Max 1.0
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note) The allowable values of the MCLK and MCLKIN cycle times are listed in the "Typ" column. This is because the MN85560 directly inputs the clock output from MCLK to MCLKIN.
12
Commands
3 cycles Min. 8 cycles 4 cycles
PRE
ACT READ
tc(MCK)
3 cycles
tw(MCKH)
tw(MCKL)
LSIs for MPEG
MCLK
tsu(NMC)
th(NMC)
NMCS
tsu(NMRA)
th(NMRA)
NMRAS
tsu(NMCA) th(NMCA)
* Timing Charts (Basic burst read operation)
NMCAS
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
tsu(NMWE)
th(NMWE)
NMWE
tsu(MA)
th(MA)
MA11 BK BK Row Row Col
BK
MA10
MA9-MA0
tc(MCKI) td(MCK-MCKI)
tw(MCKIH)
tw(MCKIL)
MCLKI
tsu(MDQ-MCKI) th(MDQ-MCKI)
DQ15-DQ0 (driven by SDRAM) Row : Row address Col : Column address
MN85560
13
* BK : Bank number
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
14
Commands
3 cycles 8 cycles
PRE
ACT
WRIT
tc(MCK)
3 cycles
tw(MCKH)
tw(MCKL)
MCLK
tsu(NMC)
th(NMC)
NMCS
tsu(NMRA)
th(NMRA)
NMRAS
tsu(NMCA) th(NMCA)
* Timing Charts (Basic burst write operation)
NMCAS
tsu(NMWE)
th(NMWE)
NMWE
tsu(MA)
th(MA)
MA11 Row Row Col
BK BK BK
MA10
MA9-MA0
tsu(MDQ-MCK)
th(MDQ-MCK)
DQ15-DQ0 DQ31-DQ16 D1 Row: Row address
D2
D3
D4
D5
D6
D7
D8 D1 to D8 : Write data
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* BK : Bank number
Col : Column address
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I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter Serial mode HD24 (NEMPTY) fall time from the RCLK rising edge NHDACK (NRE) setup time to the RCLK rising edge NHDACK (NRE) hold time from the RCLK rising edge HD16 (HD23:16) data setup time to the RCLK rising edge HD16 (HD23:16) data hold time from the RCLK rising edge Parallel mode (single bus cycle mode) NHDACK setup time to the RCLK rising edge NHDACK hold time from the RCLK rising edge HD31:0 drive time from the NHDACK falling edge HD31:0 data setup time to the RCLK rising edge HD31:0 data hold time from the NHDACK rising edge Parallel mode (two bus cycle mode) HA3:0 setup time to the NHAS falling edge HA3:0 hold time from the NHAS rising edge NHAS pulse width NHAS setup time to the NHDS falling edge NHCS setup time to the NHDS falling edge NHCS hold time from the NHDS rising edge NHDS pulse width HRW setup time to the NHDS falling edge HRW hold time from the NHDS rising edge tsu(HA-NHAS) th(HA-NHAS) tw(NHAS) tsu(NHAS-NHDS) tsu(NHCS-NHDS) th(NHCS-NHDS) tw(NHDS) tsu(HRW-NHDS) th(HRW-NHDS) 15 15 30 15 15 15 100 15 15 tsu(NHDACK-RCLK) th(NHDACK-RCLK) td(HD-NHDACK) tv(HD-RCLK) th(HD-NHDACK) 10 10 1 1 20 th(NEMPTY) tsu(NHDACK) th(NHDACK) tv(HD) th(HD) 3 3 4 3 25 Symbol Min Typ Max
MN85560
Unit
ns ns ns ns ns
ns ns ns ns ns
ns ns ns ns ns ns ns ns ns
15
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter Symbol Min Typ
LSIs for MPEG
Max
Unit
Parallel mode (two bus cycle mode) (continued) HD31:0 drive time from the NHCS falling edge HD31:0 drive time from HWR transitions HD31:0 data setup time to the NHDS falling edge HD31:0 data hold time from the NHCS rising edge HD31:0 data hold time from HWR transitions NHDS recovery time td(HD-NHCS) td(HD-HRW) tv(HD-NHDS) th(HD-NHCS) th(HD-HRW) tr 1 1 1 1 40 100 ns ns ns ns ns ns
16
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I Electrical Characteristics (continued) 4. AC Characteristics (continued)
MN85560
* Interface operation timing (Serial mode) The only difference between the 1-bit mode and the 8-bit mode is the bit width: the operation timing is identical. In 1-bit mode, code is output from HD16, and in 8-bit mode code is output from HD23:16. 1. HD24 (NEMPTY) goes high at tv(NEMPTY) after the RCLK rising edge. 2. When HD24 (NEMPTY) is high, NHDACK (NRE) should be set low tsu(NHDACK) before the RCLK rising edge. 3. Code data is output at the point tv(HD) after the first RCLK rising edge after NHDACK (NRE) was set low. The code data is held for just the period th(HD) from at the next RCLK rising edge. The next code data is output after that. 4. Following NHDACK (NRE) being set low, code data is output continuously in synchronization with RCLK. 5. When HD24 (NEMPTY) goes low, we recommend that you hold NHDACK (NRE) low until after th(NHDACK) has elapsed from the next RCLK rising edge and then set it high. Code data output stops on the next RCLK cycle after that. (This is not valid code data, rather the pin merely remains in the driving state.) However, note that HD24 (NEMPTY) goes low at th(NEMPTY) after the RCLK rising edge.
* Timing Chart (Serial mode)
(n > = 1) RCLK x n cycle
RCLK th(NEMPTY) HD24(NEMPTY) tsu(NHDACK) NHDACK(NRE) tv(HD) HD16 (HD23-HD16) code data th(HD) code data code data code data th(NHDACK)
17
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
LSIs for MPEG
* Interface operation timing (Parallel mode) While the following describes 32-bit mode, 16-bit mode only differs in the bit width: the operation timing is identical. 1. When NHDREQ is low, NHDACK should be set low at tsu(NHDACK-RCLK) before the RCLK rising edge. The MN85560 starts drive of the HD31:0 pins at td(HD-NHDACK) after NHDACK is set low. 2. After NHDACK is set low, code data is output at tv(HD-RCLK) after the first RCLK rising edge. 3. NHDACK should be held low for one complete RCLK cycle. You should hold NHDACK low until after th(NHDACK-RCLK) from the RCLK rising edge, and then set NHDACK high. 4. After setting NHDACK high, the code data is held just the period th(HD-NHDACK). After that, HD31:0 go to the highimpedance state. 5. After that, NHDACK should be held high for at least one complete RCLK cycle.
* Timing Chart (Parallel mode: single bus cycle mode)
(n > = 1) RCLK x n cycle RCLK (m > = 1) RCLK x m cycle
NHDREQ tsu(NHDACK-RCLK) NHDACK td(HD-NHDACK) HD31-HD0 (HD15-HD0) tv(HD-RCLK) code data th(HD-NHDACK) th(NHDACK-RCLK)
18
LSIs for MPEG
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
* Timing Chart (Parallel mode: two bus cycle mode)
MN85560
NHDREQ tsu(HA-NHAS) HA3-HD0 invalid HA[3:0] = 4'b1110 tw(NHAS) tsu(NHAS-NHDS) tsu(NHCS-NHDS) NHCS tw(NHDS) NHDS tsu(HRW-NHDS) HRW HD31-HD0 (HD15-HD0) td(HD-HRW) tv(HD-NHDS) don't care td(HD-NHCS) code data th(HD-NHCS) th(HRW-NHDS) don't care th(HD-HRW) tr th(NHCS-NHDS) th(HA-NHAS) invalid
NHAS
19
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter Read operations H3:0 setup time to the NHAS falling edge H3:0 hold time from the NHAS rising edge NHAS pulse width NHAS setup time to the NHDS falling edge NHCS setup time to the NHDS falling edge NHCS hold time from the NHDS rising edge NHDS pulse width HRW setup time to the NHDS falling edge HRW hold time from the NHDS rising edge HD31:0 drive time from the NHCS falling edge HD31:0 drive time from HRW transitions Read access time from the NHDS falling edge HD31:0 hold time from the NHCS rising edge HD31:0 hold time from HRW transitions NHDS recovery time Read cycle time Write operations HA3:0 setup time to the NHAS falling edge HA3:0 hold time from the NHAS rising edge NHAS pulse width NHAS setup time to the NHDS falling edge tsu(HA-NHAS) th(HA-NHAS) tw(NHAS) tsu(NHAS-NHDS) 15 15 30 15 tsu(HA-NHAS) th(HA-NHAS) tw(NHAS) tsu(NHAS-NHDS) tsu(NHCS-NHDS) th(NHCS-NHDS) tw(NHDS) tsu(HRW-NHDS) th(HRW-NHDS) td(HD-NHCS) td(HD-HRW) ta(HD-NHDS) th(HD-NHCS) th(HD-HRW) trr(NHDS) tCR 15 15 30 15 15 15 200 15 15 1 1 1 1 40 255 Symbol Min Typ
LSIs for MPEG
Max
Unit
200
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ns ns ns ns
20
LSIs for MPEG
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter Write operations (continued) NHCS setup time to the NHDS falling edge NHCS hold time from the NHDS rising edge NHDS pulse width HRW setup time to the NHDS falling edge HRW hold time from the NHDS rising edge HD31:0 setup time to the NHDS rising edge HD31:0 hold time from the NHDS rising edge NHDS recovery time Write cycle time tsu(NHCS-NHDS) th(NHCS-NHDS) tw(NHDS) tsu(HRW-NHDS) th(HRW-NHDS) tsu(HD-NHDS) th(HD-NHDS) trw(NHDS) tCW 15 15 100 15 15 20 20 90 205 Symbol Min Typ Max
MN85560
Unit
ns ns ns ns ns ns ns ns ns
* Timing Chart (Read operation)
tCR tsu(HA-NHAS) HA3-HA0 invalid valid tw(NHAS) NHAS tsu(NHAS-NHDS) tsu(NHCS-NHDS) NHCS tw(NHDS) NHDS HRW tsu(HRW-NHDS) don't care td(HD-NHCS) HD31-HD0 td(HD-HRW) ta(HD-NHDS) valid th(HD-NHCS) trr(NHDS) th(HRW-NHDS) don't care th(HD-HRW) th(NHCS-NHDS) th(HA-NHAS) invalid
21
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
* Write Operation
LSIs for MPEG
The operation timing is as follows: 1. The value of the address to be written in HA3:0 must be set up before setting NHAS low. However, NHAS must be set low at tsu(NHAS-NHDS) before NHDS is set low. 2. Hold NHAS low for the period tw(NHAS). After that, NHAS may be set high. However, HA3:0 must be fixed within the period th(HA-NHAS) from the point NHAS is set high. 3. Set NHCS low at tsu(NHCS-NHDS) before NHDS is set low. Also, HRW must be set low at tSU(HRW-NHDS) before NHDS is set low. HD31:0 will remain in the high-impedance state in case of setting HRW low even if NHCS is low. 4. Hold NHDS low for the period tw(NHDS). Set up the value of the data to be written in HD31:0 before setting NHDS high. 5. Set NHDS high. Hold HD31:0 fixed for the period th(HD-NHDS) after setting NHDS high. After setting NHDS high, hold NHDS fixed at the high level for the period trw(NHDS) until the next read or write operation. 6. After setting NHDS high and at least the time th(NHCS-NHDS) has elapsed, set NHCS high. Note that HRW may be changed when at least the time th(HRW-NHDS) has passed after NHDS was set high.
* Timing Chart (Write operation)
tCW tsu(HA-NHAS) HA3-HA0 invalid valid tw(NHAS) NHAS tsu(NHAS-NHDS) tsu(NHCS-NHDS) NHCS tw(NHDS) NHDS HRW don't care valid data tsu(HD-NHDS) th(HD-NHCS) tsu(HRW-NHDS) trw(NHDS) th(HRW-NHDS) don't care th(NHCS-NHDS) th(HA-NHAS) invalid
HD31-HD0
22
LSIs for MPEG
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter SCLK cycle time SCLK high-level pulse width SCLK low-level pulse width VCLK cycle time VCLK high-level pulse width VCLK low-level pulse width RCLK cycle time RCLK high-level pulse width RCLK low-level pulse width Symbol tc(SCLK) tw(SCLKH) tw(SCLKL) tc(VCLK) tw(VCLKH) tw(VCLKL) tc(RCLK) tw(RCLKH) tw(RCLKL) Min 14.0 14.0 37.0 14.0 14.0 30.0 12.0 12.0 Typ 37.0 Max
MN85560
Unit ns ns ns ns ns ns ns ns ns
Note) The reason the allowable value of the SCLK cycle time is listed in the "Typ" column is to indicate that the MN85560 only has the SCLK cycle time specification of 37.0 ns (27.0 MHz). Thus, a frequency of over 27 MHz cannot be used. Furthermore, note that use of a frequency of less than 27 MHz involves changes to certain of the AC characteristics, and such specifications cannot be guaranteed for this product.
* Clock Signal Timing Chart This section presents the timing of the clock signal input to the clock input pin. A fixed value can be input to the code output clock RCLK, but only when the code output mode is set to parallel mode two bus cycle DMA transfer mode.
tc(SCLK) tw(SCLKH) tw(SCLKL)
SCLK
tc(VCLK) tw(VCLKH) tw(VCLKL)
VCLK
tc(SCLK) tw(RCLKH) tw(FCLKL)
RCLK
23
MN85560
I Electrical Characteristics (continued) 4. AC Characteristics (continued)
Parameter PLL initialization operation wait time NPLLRSET low-level pulse width Chip hardware reset wait time NRST low-level pulse width Symbol tp(PLLASH-NPLLRSETL) tw(NPLLRSET) tp(NPLLRSETH-NRSTL) tw(NRST) Min 50.0 50.0 100 15 Typ
LSIs for MPEG
Max
Unit ns ns s cycle*
Note) *: A number of clock cycles for the clock with the lowest frequency of the SCLK, VCLK, and RCLK clocks. (However, this does not apply for code output in parallel mode two bus cycle mode.)
* Timing Chart VDD SCLK VCLK RCLK 0V
tp(PLLASH-NPLLRSETL)
PLLAS
tw(NPLLRSET)
tp(NPLLRSETH-NRSTL)
NPLLRSET
Position A
tw(NRST)
NRST
The MN85560 takes a 27 MHz signal input as the SCKL system clock and uses a PLL circuit to multiply that to 81 MHz. Therefore when powering up, the hardware reset signal must be asserted after the PLL oscillator has stabilized. The pins used to start PLL operation are the PLL assert pin (PLLAS) and the PLL reset input pin (NPLLRSET). Note that the signal that performs the chip hardware reset is the chip initialization reset input pin (NRST). The period that NRTS must be asserted is 15 cycles of the slowest of the SCLK, VCLK, and RCLK signals (for code output in parallel mode two bus cycle mode, the SCLK and VCLK signals). Stabilized signals must be provided to all input pins before asserting PLLAS (position A in the figure).
24
LSIs for MPEG
I Package Dimensions (Unit: mm)
* QFP208-P-2828A
MN85560
30.60.2 28.00.1 156 157 105
(1.25) 28.00.1 3.85max. 30.60.2
104
208 1 (1.25) 0.5 52
53
3.450.2
0.2 -0.05
+0.10
(1.3)
0.1 Seating plane
0.10.1
0.15 -0.05
+0.10
0 to 10 0.50.2
25
Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR

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