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CXP81120/81124
CMOS 8-bit Single Chip Microcomputer
Description The CXP81120/81124 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time base timer, PWM output, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also the CXP81120/81124 provides power-on reset function, sleep/stop function which enables to lower power consumption. 64 pin QFP (Plastic) 64 pin LQFP (Plastic)
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit operation/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 333ns at 12MHz operation (3.0 to 5.5V) * Incorporated ROM capacity 20K bytes (CXP81120) 24K bytes (CXP81124) * Incorporated RAM capacity 832 bytes * Peripheral functions -- A/D converter 8-bit, 8-channel, successive approximation system (Conversion time: 20s at 16MHz) -- Serial interface Incorporated buffer RAM (1 to 32 bytes auto transfer), 1 channel Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer), 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer -- PWM output 12 bits, 2 channels * Interruption 10 factors, 10 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 64-pin plastic QFP/LQFP * Piggyback/evaluator CXP81100 64-pin ceramic PQFP Structure Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E94414A69-PS
Block Diagram
AVREF
INT2
XTAL
AVss
EXTAL
RST
AVDD
SPC700 CPU CORE
CLOCK GENERATOR/ SYSTEM CONTROL
PORT A
AN0 to AN7
8
A/D CONVERTER
INT0
INT1
MP
VDD Vss
8
PA0 to PA7
CS0 SI0 SO0 SCK0 BUFFER RAM
SERIAL INTERFACE UNIT (CH0)
PORT B
8
PB0 to PB7
INTERRUPT CONTROLLER
SCK1 2
SERIAL INTERFACE UNIT (CH1) FIFO ROM 20K/24K BYTES
RAM 832 BYTES
PORT C
SI1 SO1
8
PC0 to PC7
TO
8BIT TIMER 1
PORT D
PORT E
PORT F
PORT G
-2-
EC
8BIT TIMER/COUNTER 0
8
PD0 to PD7
2 2 4 PRESCALER/ TIME BASE TIMER 4 2 3
PE0 to PE1 PE2 to PE3 PF0 to PF3 PF4 to PF7 PG3 to PG4 PG5 to PG7
PWM0
12BIT PWM GENERATOR CH0
PWM1
12BIT PWM GENERATOR CH1
CXP81120/81124
CXP81120/81124
Pin Configuration (Top View) 64-pin QFP
PG3/TO
PA2
PA5
PA0
PA3
PA1
64 63 62 61 60 59 58 57 56 55 54 53 52 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 PD5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PG5/SCK1 PG6/SO1 PG7/SI1/INT1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF AVSS SCK0
XTAL
MP
PA4
VSS
PD2
PD0
VSS
PA6
VDD
CS0
PA7
NC
SI0
Note) 1. 2. 3.
NC (Pin 58) is always connected to VDD. Vss (Pins 28 and 60) are both connected to GND. MP (Pin 25) is always connected to GND.
-3-
EXTAL
RST
SO0
PD4
PD3
PD1
PG4
CXP81120/81124
Pin Configuration (Top View) 64-pin LQFP
PG3/TO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD7 PD6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PG6/SO1 PG7/SI1/INT1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PF0/AN0 PF1/AN1 PF2/AN2 PF3/AN3 PF4/AN4 PF5/AN5 PF6/AN6 PF7/AN7 AVDD AVREF
XTAL
PD3
MP
VSS
CS0
SI0
EXTAL
SCK0
PD4
PD5
PD2
PD1
PD0
RST
SO0
PG4
PB7
PB6
PA1
PA2
PA3
PA4
PA5
PA0
VDD
VSS
NC
PA6
PA7
Note) 1. 2. 3.
NC (Pin 56) is always connected to VDD. Vss (Pins 26 and 58) are both connected to GND. MP (Pin 23) is always connected to GND.
-4-
AVSS
PG5/SCK1
CXP81120/81124
Pin Description Symbol PA0 to PA7 I/O Output (Port A) 8-bit output port. (8 pins) (Port B) 8-bit output port. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port D) 8-bit I/O port. I/O and function as standby release input can be set in a unit of single bits. (8 pins) Input to request external interruption. Active at the falling edge. (2 pins) External event input for timer/counter. 12-bit PWM output. (2 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input. (8 pins) Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial interface (CH0) chip select input. Timer/counter rectangular wave output. (Port G) 5-bit port. Lower 2 bits are for output; upper 3 bits are for I/O. I/O can be set in a unit of single bits. (5 pins) Description
PB0 to PB7
Output
PC0 to PC7
I/O
PD0 to PD7
I/O
PE0/INT0
Input/Input Input/Input/ Input Output/Output Output/Output Input/Input (Port E) 4-bit port. Lower 2 bits are for input; upper 2 bits are for output. (4 pins)
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PF0/AN0 to PF3/AN3 PF4/AN4 to PF7/AN7 SCK0 SO0 SI0 CS0 PG3/TO PG4 PG5/SCK1 PG6/SO1
Output/Input I/O Output Input Input Output/Output Output I/O/I/O I/O/Output
Analog input to A/D converter. (8 pins)
Serial clock (CH1) I/O. Serial data (CH1) output. Input to request external Serial data (CH1) interruption. Active at the input. falling edge.
I/O/Input PG7/SI1/INT1 Input EXTAL XTAL RST Input Output I/O
Connects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. System reset; active at Low level. RST pin is I/O pin, which outputs "Low" level by incorporated power-on reset function when power turns on. (Mask option)
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CXP81120/81124
Symbol NC MP AVDD AVREF AVSS VDD VSS Input Input
I/O
Description NC pin. Connect to VDD for normal operation. Test mode pin. Always connect to GND. Positive power supply of A/D converter. Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. GND. Connect both Vss pins to GND.
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CXP81120/81124
Input/Output Circuit Formats for Pins Pin Port A Port B PA0 to PA7 PB0 to PB7 Circuit format When reset
Ports A, B data
Hi-Z
Data bus
16 pins Port C
RD (Ports A, B)
Output becomes active from high impedance by data writing to port register.
Port C data
PC0 to PC7
Port C direction "0" when reset Data bus IP
Input protection circuit
Hi-Z
8 pins Port D
RD (Port C)
Port D data
PD0 to PD7
Data bus
Port D direction "0" when reset IP RD (Port D)
Hi-Z
Edge detection
8 pins Port E
Standby release
Schmitt input
PE0/INT0
IP
EC/INT2
Hi-Z
Data bus
1 pin Port E PE1/EC/INT2
IP
RD (Port E)
Schmitt input INT0
Hi-Z
Data bus
1 pin
RD (Port E)
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CXP81120/81124
Pin Port E
PWM Hi-Z control
Circuit format
When reset
MPX
PE2/PWM0 PE3/PWM1
Port E data
Hi-Z
Port E function selecton "0" when reset Data bus
2 pins Port F
RD (Port E)
input multiplexer IP A/D converter
PF0/AN0 to PF3/AN3
Data bus RD (Port F) Edge detection
Hi-Z
4 pins Port F
Standby release
PF4/AN4 to PF7/AN7
Port F data
Data bus RD (Port F) Port F function selection "0" when reset Input multiplexer
IP
Hi-Z
4 pins Port G
Port G function selection
A/D converter
PG3/TO
"0" when reset Timer/counter MPX Port G data "1" when reset
High level
1 pin
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CXP81120/81124
Pin Port G PG4
Port G data "1" when reset
Circuit format
When reset
H level
1 pin Port G
Port G function selection "0" when reset SCK1 out, SO1
PG5/SCK1 PG6/SO1
Serial clock 1/data 1 output enable Port G data Port G direction "0" when reset Data bus RD (Port G) SCK1 in
MPX
Hi-Z
MPX IP
1
2 pins Port G
Port G data
1 PG6 is not Schmitt input
PG7/SI1/INT1
Data bus
Port G direction "0" when reset IP RD (Port G)
Hi-Z
1 pin
INT1 SI1
Schmitt input
CS0 SI0 2 pins
Schmitt input IP CS0 SI0
Hi-Z
SO0
SO0 Serial data 0 output enable
Hi-Z
1 pin
-9-
CXP81120/81124
Pin
Circuit format
When reset
SCK0 out
SCK0
Serial clock 0 output enable SCK0 in IP
Hi-Z
1 pin
Schmitt input
EXTAL XTAL
EXTAL
IP
* Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during stop. XTAL becomes "High" level.
Oscillation
2 pins
XTAL
Pull-up resistor
RST
Mask option
Schmitt input
OP
IP From power-on reset circuit (Mask option)
Low level
1 pin MP
IP Test mode
Hi-Z
1 pin
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CXP81120/81124
Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS AVREF Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VIN VOUT IOH IOH IOL IOL Topr Tstg PD Rating -0.3 to +7.0 AVSS to +7.0 -0.3 to +0.3 AVSS to +7.0 -0.3 to +7.01 -0.3 to +7.01 -5 -50 15 130 -20 to +75 -55 to +150 600 380 Unit V V V V V V mA mA mA mA C C mW mW QFP-64P-L01
(Vss = 0V reference) Remarks
Total of output pins
Total of output pins
LQFP-64P-L01
1 VIN and VOUT should not exceed VDD + 0.3V. (CS0 and SI0 excluded.) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP81120/81124
Recommended Operating Conditions Item Symbol Min. 3.0 Supply voltage VDD 2.7 2.5 Analog voltage AVDD VIH High level input voltage VIHS VIHEX VIL Low level input voltage VILS VILEX Operating temperature Topr 1 2 3 4 5 6 7 3.0 0.7VDD 0.8VDD Max. 5.5 5.5 5.5 5.5 VDD VDD 5.5 Unit V V V V V V V V V V V V C
(Vss = 0V reference) Remarks Guaranteed operation range for 1/2 and 1/4 frequency dividing mode Guaranteed operation range for 1/16 frequency dividing mode Guaranteed data hold range during stop mode 1 2 CMOS Schmitt input3 CMOS Schmitt input4 EXTAL pin5 2, 7 2, 6 CMOS Schmitt input3, 4 EXTAL pin5
VDD - 0.4 VDD + 0.3 0 0 -0.3 -20 0.3VDD 0.2VDD 0.2VDD 0.4 +75
AVDD should be the same voltage as VDD. Normal input port (PC, PD, PF0 to PF3 and PG6 pins), MP pin. SCK0, RST, INT0, EC/INT2, SCK1 and SI1/INT1 pins. CS0 and SI0 pins. Specified only when the external clock is input. In case of 3.0 to 3.6V supply voltage (VDD). In case of 4.5 to 5.5V supply voltage (VDD).
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CXP81120/81124
DC Characteristics Supply voltage (VDD = 4.5 to 5.5V) Item High level output voltage Symbol VOH Pin PA to PE, PF4 to PF7, SO0, SCK0, RST1 (VOL only) PG3 to PG7 EXTAL RST2 Condition VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 -1.5 (Ta = -20 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 40 -40 -400 10 Typ. Max. Unit V V V V A A A A
Low level VOL output voltage IIHE Input current IILE IILR I/O leakage current IIZ
PA to PG, MP, VDD = 5.5V, CS0, SI0, SO0, VI = 0, 5.5V SCK0, RST2 1/2 frequency dividing mode
IDD1
VDD = 5V 0.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode VDD
20
40
mA
Supply current3
IDDS1
VDD = 5V 0.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) Stop mode
1
5
mA
IDDS3 PC, PD, PE0, PE1, PF, PG5 to PG7, RST, CS0, SI0, SCK0, EXTAL
VDD = 5.5V, termination of 16MHz oscillation
10
A
Input capacity
CIN
Clock 1MHz 0V other than the measured pins
10
20
pF
1 RST pin is specified only when the power-on reset circuit is selected with mask option. 2 For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. 3 When all output pins are open.
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CXP81120/81124
DC Characteristics Supply voltage (VDD = 3.0 to 3.6V) Item High level output voltage Symbol VOH Pin PA to PE, PF4 to PF7, SO0, SCK0, RST1 (VOL only) PG3 to PG7 EXTAL RST2 Condition VDD = 3.0V, IOH = -0.15mA VDD = 3.0V, IOH = -0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL = 0.3V VDD = 3.6V, VIL = 0.3V 0.3 -0.3 -0.9 (Ta = -20 to +75C, Vss = 0V reference) Min. 2.7 2.3 0.3 0.5 20 -20 -200 10 Typ. Max. Unit V V V V A A A A
Low level VOL output voltage IIHE Input current IILE IILR I/O leakage current IIZ
PA to PG, MP, VDD = 3.6V, CS0, SI0, SO0, VI = 0, 3.6V SCK0, RST2 1/2 frequency dividing mode
IDD2
VDD = 3.3V 0.3V, 12MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode VDD
10
20
mA
Supply current3
IDDS2
VDD = 3.3V 0.3V, 12MHz crystal oscillation (C1 = C2 = 15pF) Stop mode
0.5
2.5
mA
IDDS3 PC, PD, PE0, PE1, PF, PG5 to PG7, RST, CS0, SI0, SCK0, EXTAL
VDD = 5.5V, termination of 12MHz oscillation
10
A
Input capacity
CIN
Clock 1MHz 0V other than the measured pins
10
20
pF
1 RST pin is specified only when the power-on reset circuit is selected with mask option. 2 For RST pin, specifies the input current when the pull-up resistance is selected, and specifies leakage current when non-resistance is selected. 3 When all output pins are open.
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CXP81120/81124
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times 1 Symbol fC Pin XTAL EXTAL XTAL EXTAL EXTAL EC EC Fig. 1, Fig. 2 (Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V reference) Condition VDD = 4.5 to 5.5V Min. 1 1 28 37.5 200 4tsys1 20 ns ns ms Max. 16 12 ns Unit MHz
tXL, tXH tCR, tCF tEL, tEH tER, tEF
VDD = 4.5 to 5.5V Fig. 1, Fig. 2 (External clock drive) Fig. 1, Fig. 2 (External clock drive) Fig. 3 Fig. 3
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc VDD - 0.4V (VDD = 4.5 to 5.5V) VDD - 0.3V 0.4V (VDD = 4.5 to 5.5V) 0.3V tXH tCF tXL tCR
EXTAL
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock
EXTAL
XTAL
EXTAL
XTAL
C1
C2
74HC04
Fig. 3. Event count clock timing
0.8VDD EC 0.2VDD
tEH
tEF
tEL
tER
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CXP81120/81124
(2) Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 200 100 ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 8000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 100 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
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CXP81120/81124
Serial transfer (CH0) Item CS SCK delay time CS SCK floating delay time CS SO delay time CS SO floating delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ) SI input hold time (for SCK ) SCK SO delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V reference) Condition Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK input mode SI0 SCK output mode SCK input mode SI0 SCK output mode SCK input mode SO0 SCK output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 2tsys + 250 125 ns ns
tDCSK
tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200
2tsys + 200 8000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 150 -tsys + 100 200 2tsys + 100 100
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) CS, SCK, SI and SO represents CS0, SCK0, SI0, and SO0, respectively. Note 3) The load of SCK output mode and SO output delay time is 50pF.
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CXP81120/81124
Fig. 4. Serial transfer timing (CH0)
tWHCS
CSO 0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP81120/81124
Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Serial transfer (CH1) (SIO mode) Item SCK1 cycle time SCK1 high and low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Note 1) Symbol Pin SCK1
(Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V reference) Condition Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 2tsys + 200 16000/fc Max. Unit ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 150 100 200
tsys + 200
100
tsys + 250
125
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF.
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CXP81120/81124
Fig. 5. Serial transfer CH1 timing (SIO mode)
tKCY tKL tKH
SCK1 0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP81120/81124
Serial transfer (CH1) (Special mode) (Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SO1 cycle time SI1 data setup time SI1 data hold time 1 Symbol Pin SO1 SI1 SI1 SI1 1 2 2 Condition Min. Typ. 104 Max. Unit s s s
tLCY tLSU tLHD
tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is
set at 104s according to the system clock frequency. Note) The load of SO1 pin is 50pF + 1TTL.
Serial transfer (CH1) (Special mode) (Ta = -20 to +75C, VDD = 3.0 to 3.6V, Vss = 0V reference) Item SO1 cycle time SI1 data setup time SI1 data hold time 1 Symbol Pin SO1 SI1 SI1 SI1 1 2 2 Condition Min. Typ. 104 Max. Unit s s s
tLCY tLSU tLHD
tLCY is specified only when serial mode register (CH1) (SIOM1: 01FAH) lower 2 bits (SO1 clock selection) is
set at 104s according to the system clock frequency. Note) The load of SO1 pin is 50pF.
Fig. 6. Serial transfer CH1 timing (Special mode)
tLCY tLCY
SO1
Start bit
Output data bit
0.5VDD
tLCY/2 tLSU tLHD 0.8VDD 0.2VDD
SI1
Input data bit
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CXP81120/81124
(3) A/D converter characteristics (Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Only for A/D converter operation Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Symbol Pin Condition Min. Typ. Max. 8 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN7 Operating mode AVREF = 4.0 to 5.5V Sleep mode Stop mode VDD = AVDD = 4.5 to 5.5V AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10 Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN
Reference input voltage VREF Analog input voltage
AVREF current
IREF
AVREF
A/D converter characteristics Item Resolution Linearity error Absolute error Conversion time Sampling time
(Ta = -20 to +75C, VDD = AVDD = 3.0 to 3.6V, AVREF = 2.7 to AVDD, Vss = AVSS = 0V reference) Pin Condition Min. Typ. Max. 8 Only for A/D converter operation Ta=25C VDD = AVDD = AVREF = 3.3V VSS = AVSS = 0V 1 2 160/fADC1 12/fADC1 AVREF AN0 to AN7 Operating mode AVREF = 2.7 to 3.6V Sleep mode Stop mode VDD = AVDD = 3.0 to 3.6V AVDD - 0.3 0 0.4 AVDD AVREF 0.7 10 Unit Bits LSB LSB s s V V mA A
Symbol
tCONV tSAMP
VIAN
Reference input voltage VREF Analog input voltage
AVREF current
IREF
AVREF
Fig. 7. Definitions of A/D converter terms
FFH FEH
Digital conversion value
1 The value of fADC is as follows by interruption selection/
Linearity error 01H 00H VZT Analog input VFT
ADC operation clock selection regeister (MSC: 01FFH ) bit 0 (ADCCK). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc
- 22 -
CXP81120/81124
(4) Interruption, reset input Item External interruption high and low level widths Reset input low level width
(Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V reference) Symbol Pin INT0 INT1 INT2 PJ0 to PJ7 RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
Fig. 8. Interruption input timing
tIH tIL
INT0 INT1 INT2 PD0 to PD7 (During standby release input) (Falling edge)
0.8VDD 0.2VDD
Fig. 9. Reset input timing
tRSL
RST 0.2VDD
(5) Power-on reset1 Item Power supply rising time
(Ta = -20 to +75C, VDD = 3.0 to 5.5V, Vss = 0V reference) Symbol Pin Condition Power-on reset Min. 0.05 1 Max. 30 Unit ms ms
Repetitive power-on reset Power supply cut-off time 1 Specifies only when power-on reset function is selected.
tR tOFF
VDD
Fig. 10. Power-on reset
VDD
3.0V 0.2V 0.2V
tR The power supply should be turned on smoothly.
tOFF
- 23 -
CXP81120/81124
Appendix Fig. 11. SPC 700 Series recommended oscillation circuit
Main clock
EXTAL
XTAL Rd
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
10.00 HC-49/U03 12.00 16.00 8.00 22 (15) 15 12 22 (15) 5 5
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00 15 12
0
(i)
Mask Option Table Item Reset pin pull-up resistor Power-on reset circuit Non-existent Non-existent Content Existent Existent
- 24 -
CXP81120/81124
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 20
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical)
1/2 dividing mode 1/4 dividing mode 10
1/2 dividing mode 1/16 dividing mode
IDD - Supply current [mA]
Sleep mode 1.0
IDD - Supply current [mA]
15
1/4 dividing mode 10
5 1/16 dividing mode 0.1 Sleep mode
2
3 4 5 6 VDD - Supply voltage [V]
7
1
5
10
15
fc - System clock [MHz]
IDD vs. VDD
(fc = 12MHz, Ta = 25C, Typical) 20 1/2 dividing mode 10 1/4 dividing mode 1/16 dividing mode
IDD vs. fc
(VDD = 3.3V, Ta = 25C, Typical)
IDD - Supply current [mA]
Sleep mode 1.0
IDD - Supply current [mA]
15
10
1/2 dividing mode
5 0.1
1/4 dividing mode
1/16 dividing mode Sleep mode 2 3 4 5 6 7 1 5 10 15
VDD - Supply voltage [V]
fc - System clock [MHz]
- 25 -
CXP81120/81124
Package Outline
Unit: mm
64PIN QFP(PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1
51 33
+ 0.1 0.15 - 0.05 0.15
52
32
17.9 0.4
+ 0.4 14.0 - 0.1
64
20
+ 0.2 0.1 - 0.05
1 1.0 + 0.15 0.4 - 0.1
+ 0.35 2.75 - 0.15 0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-64P-L01 QFP064-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 1.5g
- 26 -
0.8 0.2
19
16.3
CXP81120/81124
64PIN LQFP (PLASTIC)
12.0 0.2 48 49 10.0 0.1 33 32
A 64 1 0.5 0.08 16 + 0.2 1.5 - 0.1 17 (0.22) + 0.08 0.18 - 0.03
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
0.5 0.2
NOTE: Dimension "" does not include mold protrusion. DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-64P-L01 LQFP064-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.3g
- 27 -
0.5 0.2
(11.0)

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