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| December 1996 NDH8502P Dual P-Channel Enhancement Mode Field Effect Transistor General Description SuperSOTTM-8 P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -2.2 A, -30 V. RDS(ON) = 0.11 @ VGS = -10 V RDS(ON) = 0.18 @ VGS = -4.5 V. Proprietary SuperSOTTM-8 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. ___________________________________________________________________________________________ 5 4 3 2 1 6 7 8 Absolute Maximum Ratings T A = 25C unless otherwise noted Symbol VDSS VGSS ID PD TJ,TSTG Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation Operating and Storage Temperature Range (Note 1) (Note 1) NDH8502P -30 20 -2.2 -10 0.8 -55 to 150 Units V V A W C THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1) (Note 1) 156 40 C/W C/W (c) 1997 Fairchild Semiconductor Corporation NDH8502P Rev.C ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current VGS = 0 V, ID = -250 A VDS = -24 V, VGS = 0 V TJ= 55C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse VGS = 20 V, VDS = 0 V VGS = -20 V, VDS= 0 V VDS = VGS, ID = - 250 A TJ= 125C Static Drain-Source On-Resistance VGS = -10 V, ID = -2.2 A TJ= 125C VGS = -4.5 V, ID = -1.7 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current VGS = -10 V, VDS = -5 V VGS = -4.5 V, VDS = -5 V Forward Transconductance VDS = -10 V, ID = -2.2 A VDS = -15 V, VGS = 0 V, f = 1.0 MHz DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance 340 218 100 pF pF pF -10 -4 3.8 S -1 -0.8 -1.5 -1.2 0.1 0.14 0.17 -30 -1 -10 100 -100 V A A nA nA ON CHARACTERISTICS (Note 2) Gate Threshold Voltage -3 -2.2 0.11 0.2 0.18 A V SWITCHING CHARACTERISTICS (Note 2) Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -15 V, ID = -2.2 A, VGS = -10 V VDD = -10 V, ID = -1 A, VGS = -10 V, RGEN = 6 8 18 28 20 10.9 1.4 3.6 15 35 50 35 14.5 ns ns ns ns nC nC nC NDH8502P Rev.C ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) Symbol Parameter Conditions Min Typ Max -0.67 (Note 2) Units A V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design. Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.67 A -0.76 -1.2 PD(t) = R JA(t) T J-TA = T J-TA R JC+RCA(t) = I 2 (t) x RDS(ON ) D TJ Typical RJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: 156oC/W when mounted on a 0.0025 in2 pad of 2oz copper. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%. NDH8502P Rev.C Typical Electrical Characteristics -10 3 VGS = -10V , DRAIN-SOURCE CURRENT (A) -6.0 -5.0 DRAIN-SOURCE ON-RESISTANCE -8 -4.5 R DS(on) NORMALIZED , 2.5 VGS = -3.5V -4.0 -6 -4.0 2 -4.5 -5.0 -5.5 -6.0 -10 -4 -3.5 1.5 -2 -3.0 1 I D 0 0 -1 V DS 0.5 -2 -3 -4 -5 0 -2 I D , DRAIN-SOURCE VOLTAGE (V) -4 -6 , DRAIN CURRENT (A) -8 -10 Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate Voltage and Drain Current. 1.6 1.8 DRAIN-SOURCE ON-RESISTANCE I D = -2.2A V GS = -10V 1.5 DRAIN-SOURCE ON-RESISTANCE 1.4 V GS = -10V 1.2 RDS(on) , NORMALIZED TJ = 125C R DS(ON), NORMALIZED 1.2 25C 0.9 1 -55C 0.6 0.8 0.6 -50 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 0.3 0 -2 -4 -6 -8 -10 I D , DRAIN CURRENT (A) Figure 3. On-Resistance Variation with Temperature. -10 GATE-SOURCE THRESHOLD VOLTAGE Figure 4. On-Resistance Variation with Drain Current and Temperature. 1.2 V DS = -10V -8 I D , DRAIN CURRENT (A) T J = -55C 25C 125C V GS(th), NORMALIZED 1.1 V DS = V GS I D = -250A -6 1 -4 0.9 0.8 -2 0 -1 -2 V GS 0.7 -50 -25 -3 -4 -5 , GATE TO SOURCE VOLTAGE (V) -6 0 25 50 75 100 T , JUNCTION TEMPERATURE (C) J 125 150 Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with Temperature. NDH8502P Rev.C Typical Electrical Characteristics 1.08 DRAIN-SOURCE BREAKDOWN VOLTAGE I D = -250A -I , REVERSE DRAIN CURRENT (A) 1.06 1.04 1.02 1 0.98 0.96 0.94 -50 10 5 1 VGS = 0V T J = 125C BV DSS , NORMALIZED 0 .1 25C -55C 0 .0 1 0 .0 0 1 S -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (C) 125 150 0 .0 0 0 1 0 0 .2 -V SD 0 .4 0.6 0 .8 1 , BODY DIODE FORWARD VOLTAGE (V) 1 .2 Figure 7. Breakdown Voltage Variation with Temperature. Figure 8. Body Diode Forward Voltage Variation with Current and Temperature. 1000 800 -V GS, GATE-SOURCE VOLTAGE (V) 600 400 10 I D = -2.2A 8 V D S= -10V -15V -20V CAPACITANCE (pF) Ciss Coss 6 200 4 100 f = 1 MHz V GS = 0 V Crss 2 50 0 .1 0 .2 -V 0 .5 1 2 5 10 , DRAIN TO SOURCE VOLTAGE (V) DS 20 30 0 0 2 4 Q g 6 8 10 12 , GATE CHARGE (nC) Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics. -VDD V IN D ton t off tr 90% RL V OUT t d(on) t d(off) 90% tf VGS R GEN VOUT G DUT 10% 10% 90% S V IN 10% 50% 50% PULSE WIDTH INVERTED Figure 11. Switching Test Circuit. Figure 12. Switching Waveforms. NDH8502P Rev.C Typical Electrical and Thermal Characteristics g FS, TRANSCONDUCTANCE (SIEMENS) 12 20 V DS = - 5V 10 8 6 4 2 0 0 -5 -10 TJ = -55C -I D , DRAIN CURRENT (A) 10 5 2 1 0.5 S RD (O N) LIM IT 25C 125C 100 us 1m s 10m s 10 0m s 1s 10s DC 0.1 0.05 VGS = -4.5V SINGLE PULSE R JA = See Note 1c A T = 25C A 0.2 0.5 1 2 5 10 20 30 50 -15 -20 0.01 0.1 I D , DRAIN CURRENT (A) - VDS , DRAIN-SOURCE VOLTAGE (V) Figure 13. Transconductance Variation with Drain Current and Temperature. Figure 14. Maximum Safe Operating Area. 1 TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 r(t), NORMALIZED EFFECTIVE R 0.1 0.1 0.05 0.02 (t) = r(t) * R JA JA R JA = See Notes 1 P(pk) 0.01 0.01 t1 TJ - T t2 Single Pulse = P * R JA (t) Duty Cycle, D = t1 / t2 A 0.001 0.0001 0.001 0.01 0.1 1 t , TIME (sec) 1 10 100 300 Figure 15. Transient Thermal Response Curve. Note: Thermal characterization performed using the conditions described in note 1. Transient thermal response will change depending on the circuit board design. NDH8502P Rev.C NDH8502P Rev.C |
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