| PART |
Description |
Maker |
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W631GG6KB-15 W631GG6KB12A W631GG6KB12I W631GG6KB12 |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M13L2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| AD1801JST |
1400 kbps DATA, MODEM-DATA/FAX/VOICE, PQFP128 TQFP-128
|
Analog Devices, Inc.
|
| HI-878306 |
ARINC INTERFACE DEVICE 8 bit parallel data converted to 429 & 561 serial data out
|
Holt Integrated Circuits
|
| HI-8788PQTF HI-8787 HI-8787_06 HI-8787PQI HI-8787P |
ARINC INTERFACE DEVICES 16 bit parallel data converted to 429 & 561 serial data out
|
HOLTIC[Holt Integrated Circuits]
|
| K4D26323RA K4D26323RA-GC2A K4D26323RA-GC33 K4D2632 |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
|
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
|
| S1A0905X01 |
RDS (RADIO DATA SYSTEM) DEMODULATOR IC Data Sheet
|
Samsung Electronic
|
| W972GG6JB W972GG6JB-25 |
16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| ST7FDALIF2B6 |
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI (DATA BRIEFING)
|
SGS Thomson Microelectronics
|
