| PART |
Description |
Maker |
| Z8036 Z8536 |
CAP POLYPROPYLENE .0015UF 50V 1%
Z-CIO AND CIO COUNTER/TIMER AND PARALLEL I/O UNIT
|
ZiLOG, Inc.
|
| IS61DDB21M36-250M3 IS61DDB22M18-250M3 |
36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs
|
Integrated Silicon Solution, Inc.
|
| K7K3236T2C K7K3218T2C |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
|
Samsung semiconductor
|
| K7I323682M K7I321882M K7M161825A-QCI65 |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM
512Kx36 & 1Mx18 Pipelined NtRAM
|
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
|
| IS61DDPB22M36A/A1/A2 IS61DDPB24M18A IS61DDPB24M18A |
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
|
Integrated Silicon Solution, Inc
|
| IS61DDPB42M18A IS61DDPB42M18A/A1/A2 IS61DDPB41M36A |
2Mx18, 1Mx36 36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
|
Integrated Silicon Solution, Inc
|
| IS61DDPB42M36A/A1/A2 IS61DDPB44M18A IS61DDPB44M18A |
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
|
Integrated Silicon Solution, Inc
|
| IS61DDP2B22M18A IS61DDP2B21M36A/A1/A2 IS61DDP2B22M |
2Mx18, 1Mx36 36Mb DDR-IIP (Burst 2) CIO SYNCHRONOUS SRAM
|
Integrated Silicon Solution, Inc
|
| K7I161882B-FC16 K7I161882B-FC20 K7I161882B-FC25 K7 |
512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM 512Kx36位，1Mx18位首席信息官b2DDRII的SRAM
GT 35C 35#16 PIN PLUG RTANG
|
Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
|
| MC14536 MC14536B MC14536BCP MC14536BDW MC14536BDWR |
Programmable Timer
Programmable Timer 1 TIMER(S), PROGRAMMABLE TIMER, PDSO16
Programmable Timer 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP DIVIDE BY N COUNTER, PDIP16
|
ONSEMI[ON Semiconductor]
|
| CY7C1568KV18-500BZXC CY7C1568KV18-500BZC CY7C1570K |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 2M X 36 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| ICM7240IPE |
8-Bit Binary, Programmable, RC Timer Counter PULSE; RECTANGULAR, TIMER, PDIP16
|
Maxim Integrated Products, Inc.
|
