| |
|
 |
Integrated Circuit Solu...
|
| Part No. |
IC42S16101-6T
|
| OCR Text |
.... features ? drive strength for low capacitive bus loading ? clock frequency: 200, 166, 143 mhz ? fully synchronous; all signals referenced ...latency (2, 3 clocks) ? burst read/write and burst read/single write operations capability ? burst t... |
| Description |
512K x 16 Bit x 2 Banks (16-MBIT) SDRAM
|
| File Size |
773.04K /
78 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
INTEGRATED SILICON SOLUTION INC
|
| Part No. |
IS43DR16640A-3DBLI
|
| OCR Text |
...ow 0.2 x v ddq and odt 1 at a low state (all other inputs may be undefined.) the vdd voltage ramp time must be no greater than 200 ms fr...latency, dll reset function, write recovery time (wr) are user de fined variables and must be progr... |
| Description |
64M X 16 DDR DRAM, 0.45 ns, PBGA84
|
| File Size |
1,220.66K /
28 Page |
View
it Online |
Download Datasheet |
| |
|
|
Integrated Silicon Solu...
|
| Part No. |
IS42S16100C1-6T IS42S16100C1-6TL
|
| OCR Text |
...uring other commands. if a10 is low during precharge command, the bank selected by a11 is precharged, but if a10 is high, both banks will be...latency = 3 com. -5 ? 170 ma burst length=1 com. -6 ? 160 ma t rc t rc (min.) com. -7 ? 140 ma ... |
| Description |
512K Words x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
|
| File Size |
926.26K /
81 Page |
View
it Online |
Download Datasheet |
| |
|
|
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
GVT71128ZC36T-6
|
| OCR Text |
...wa ?bwd ) control (may be tied low) cke pin to enable clock and suspend operations three chip enables for simple depth expansion sno...latency (zbl)/no bus laten- cy ? (nobl ? ). it integrates 131,072x36 sram cells with ad- vanced syn... |
| Description |
128K X 36 ZBT SRAM, 4.5 ns, PQFP100
|
| File Size |
268.98K /
16 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
