| Description |
Evaluation Board for ADXL346 - 3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital Accelerometer
50 MHz to 4.0 GHz RF/IF Gain Block; Package: 3-pin; Temperature Range: -40°C to 125°C
Triple Skew-Compensating Video Delay Line with Analog and Digital Control; Package: 32-LFCSP (5x5mm w/3.5mm exposed pad); Temperature Range: -40°C to 125°C
3-Axis, ±2 g/±4 g/±8 g/±16 g Ultralow Power Digital Accelerometer; Package: 16-LGA; Temperature Range: -40°C to 125°C
CPLDs at FPGA Densities CPLD器件在FPGA的密
CPLDs at FPGA Densities LOADABLE PLD, 8.5 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 7.2 ns, PQFP208
CPLDs at FPGA Densities LOADABLE PLD, 7.2 ns, PBGA256
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA388
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PQFP208
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA256
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA484
CPLDs at FPGA Densities LOADABLE PLD, 15 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA676
CPLDs at FPGA Densities LOADABLE PLD, 10 ns, PBGA256
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