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Seiko NPC, Corp.
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Part No. |
CY7C1307V25
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OCR Text |
... ) accounts for clock skew and flight time mis-matches single multiplexed address input bus latches address inputs for both read and write ports separate port selects for depth expansion synchronous internally self-timed writes 2.... |
Description |
Memory 内存
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File Size |
232.26K /
28 Page |
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it Online |
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Cypress Semiconductor, Corp.
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Part No. |
CY7C1420BV18-250BZC
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OCR Text |
...c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems synchronous internally self-timed writes ddr ii operates with 1.5 cycle read latency when dll is enabled ope... |
Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture 1M X 36 DDR SRAM, 0.45 ns, PBGA165
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File Size |
916.18K /
27 Page |
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it Online |
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C1418AV18-267BZC
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OCR Text |
...c ) to minimize clock skew and flight time mismatches echo clocks (cq and cq ) simplify data capture in high speed systems synchronous internally self timed writes 1.8v core power supply with hstl inputs and outputs variable drive hs... |
Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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File Size |
917.70K /
27 Page |
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it Online |
Download Datasheet
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Price and Availability
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