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Philips
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| Part No. |
SAA6713H/V1
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| OCR Text |
...a0 scl sda csg4/a1 hsda tdo int hscl jtag interface test control signals trst tms tdi rst tck control unit control signals pclk, csg0 to csg9, inva, invb, pwm, outen pa0 to pa7, pb0 to pb7, pc0 to pc7 pd0 to pd7, pe0 to pe7, pf0 to pf7 outp... |
| Description |
XGA dual input flat panel controller
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| File Size |
495.10K /
103 Page |
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it Online |
Download Datasheet
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Philips Semiconductors
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| Part No. |
SAA6703H
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| OCR Text |
...i 2 c-bus interface 2 hdcp data hscl hsda 44 43 control unit control signals pa0 to pa7, pb0 to pb7, pc0 to pc7 58 to 65, 68, 69, 72 to 77, 80 to 87 52 53, 54, 126 138, 139 92 to 99, 104 to 111, 114 to 121 pd0 to pd7, pe0 to pe7, pf0 to p... |
| Description |
Xga Dual Input Flat Panel Controller
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| File Size |
611.42K /
100 Page |
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it Online |
Download Datasheet |
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Philips
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| Part No. |
SAA6713H
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| OCR Text |
...6
CSG4/A1 CSG2/A0 SCL SDA HSDA hscl TRST CLK VCLK CLOCK GENERATOR: PANEL CLOCK PLL SAMPLE CLOCK PLL PHASE SHIFT syncs HSYNC VSYNC syncs SOGIN SYNCONGREEN SLICER data enable AUTOADJUSTMENT SYNC SELECTION AND CSYNC DECODER panel clock sample... |
| Description |
XGA dual input flat panel controller
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| File Size |
426.67K /
104 Page |
View
it Online |
Download Datasheet |
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Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
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| Part No. |
ICS9DB102GLFT ICS9DB102 ICS9DB102FLFT
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| OCR Text |
...mode differential output pairs (hscl) Key Specifications: * Cycle-to-cycle jitter < 35ps * Output-to-output skew < 25 ps Features/Benefits: * CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications * PLL or bypass mode/P... |
| Description |
2 Output PCI Express Buffer with CLKREQ Function
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| File Size |
124.26K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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