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pmc
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Part No. |
1991635
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OCR Text |
...1], ANSI/TIA/EIA-644-1995 [2]). 622 Mb/s minimum data rate per line. Source-synchronous double-edge clocking, 311 MHz minimum.
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Transmit / Receive FIFO Status Interface: * * * * * Maximum 1/4 data path clock rate for LVTTL I/O. CMOS ... |
Description |
From old datasheet system
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File Size |
800.13K /
50 Page |
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it Online |
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Xilinx
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Part No. |
XC3S5000 XC3S400 XC3S4000 XC3S2000
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OCR Text |
...ignaling - Up to 784 I/O pins - 622 Mb/s data transfer rate per I/O - 18 single-ended signal standards - 8 differential I/O standards including LVDS, RSDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to ... |
Description |
(XC3S50 - XC3S5000) Spartan-3 FPGA Family
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File Size |
1,763.79K /
204 Page |
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it Online |
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EUDYNA[Eudyna Devices Inc]
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Part No. |
F0100208B
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OCR Text |
...al output
F0100208B
3.3 V / 622 Mb/s Receiver
Transimpedance Amplifier
Applications * Preamplifier of an optical receiver circuit for OC-12/STM-4 (622 Mb/s)
Functional Description The F0100208B is a stable GaAs integrated tra... |
Description |
3.3 V / 622 Mb/s Receiver Transimpedance Amplifier
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File Size |
462.89K /
10 Page |
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it Online |
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Price and Availability
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