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Agilent (Hewlett-Packard)
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| Part No. |
HDMP-0452
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| OCR Text |
... HDMP-0452. All BYPASS pins are LVTTL and contain internal pull-up circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 k resistor. Otherwise, the BYPASS[n]- inputs should be left to float. In t... |
| Description |
HDMP-0452 · 1.0625-1.25 GBd Quad Port Bypass Circuit with CDR for Fibre Channel/Storage and GbE Applications
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| File Size |
272.00K /
12 Page |
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Optoway Technology Inc.
Optoway Technology, Inc.
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| Part No. |
NU-73H74H-RG NU-73H74H-PG
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| OCR Text |
...fferential Inputs and Outputs l LVTTL TX Laser DC Bias Control l High Speed Laser DC-Bias Turn-on and Turn-off l LVTTL RX Signal Detect Outp...to reject incoming high power 1550 nm video signal, where the rejection ratio is over 40 dB. The tra... |
| Description |
3.3V, 1.25 Gbps 1310 nm Burst-Mode TX / 1.25 Gbps 1490 nm Continuous RX 2X5 SFF Package, GE-PON 1000BASE-PX20-U ONU Transceiver 3.3.25 Gbps310纳米突发模式德克萨斯 1.25 Gbps490纳米连续收发2X5 SFF封装，GE - PON的个1000BASE - PX20 - ü的ONU收发
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| File Size |
154.28K /
5 Page |
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Integrated Device Techn...
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| Part No. |
8S89296 8S89296NLGI 8S89296NLGI8
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| OCR Text |
...0] can accept lvpecl, lvcmos or lvttl levels ? full 2.5v supply voltages ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package block diagram figure 1: block diagram q nq 0 1 512 gd 0 1 256 gd 0 1 128 gd 0 1 6... |
| Description |
LVDS Programmable Delay Line
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| File Size |
344.80K /
16 Page |
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Integrated Device Techn...
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| Part No. |
8S89200 8S89200BKILFT
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| OCR Text |
... additional information. lvcmos/lvttl interface levels. 3 in input non-inverting differen tial lvpecl clock input. r in = 50 ? termination to v t. 4 v t input termination center-tap input. 5 v ref_ac output reference voltage for ac-couple... |
| Description |
Low Skew, 2:1 LVDS MUX with 1:8 Fanout and Internal Termination
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| File Size |
419.19K /
20 Page |
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it Online |
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IDT
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| Part No. |
IDT5T93GL16
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| OCR Text |
...s. a single-ended 3.3v / 2.5v lvttl input can also be used to translate to lvds outputs. the redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. selectable inputs are ... |
| Description |
2.5V LVDS 1:16 Glitchless Clock Buffer Terabuffer II
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| File Size |
122.49K /
16 Page |
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Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
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| Part No. |
K7P401822B-HC16 K7P401822B-HC20 K7P401822B-HC25 K7P403622B-HC20 K7P403622B K7P403622B-HC16 K7P403622B-HC25 K7P401822B-HC160 K7P403622B-HC200 K7P401822B-HC20T
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| OCR Text |
...dd single ended or differential LVTTL clock Inputs on clock comment. - Change AC Characteristics tKHQV : 25 - 2.5ns, 20 - 2.7ns
Draft Dat...to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and quest... |
| Description |
SENSOR DIFF VACUUM GAGE 10 H2O 128K × 36
128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128K × 36
256K X 18 STANDARD SRAM, 2.7 ns, PBGA119 14 X 22 MM, BGA-119
128K X 36 STANDARD SRAM, 2.7 ns, PBGA119 14 X 22 MM, BGA-119
256K X 18 STANDARD SRAM, 3 ns, PBGA119 14 X 22 MM, BGA-119
SENSOR DIFF VACUUM GAGE 1PSI
SENSOR ABSOLUTE 0-15PSIA
128Kx36 & 256Kx18 Synchronous Pipelined SRAM
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| File Size |
278.02K /
13 Page |
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Integrated Device Techn...
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| Part No. |
87339AMI-11LFT 87339AGI-11LFT
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| OCR Text |
...gle ended input signal (lvcmos, lvttl, gtl) to lvpecl levels with resistor bias on nclk input ? output skew: 35ps (maximum) ? part-to-part skew: 385ps (maximum) ? bank skew: bank a - 20ps (maximum) bank b - 20ps (maximum) ? pr... |
| Description |
Low Skew, Differential-to-3.3V LVPECL Clock Generator
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| File Size |
193.97K /
15 Page |
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it Online |
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Price and Availability
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