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Integrated Device Technology, Inc.
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| Part No. |
IDT72T51236L6BB IDT72T51236L5BB IDT72T51246L5BB IDT72T51256 IDT72T51246L6BB IDT72T51246L6BBI IDT72T51246L5BBI
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| OCR Text |
...packet mode operation ? ? ? ? ? partial reset, clears data in single queue ? ? ? ? ? expansion of up to 8 multi-queue devices in parallel is available ? ? ? ? ? power down input provides additional power savings in hstl and ehstl modes. ? ?... |
| Description |
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits 32K X 36 OTHER FIFO, 3.7 ns, PBGA256
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits 32K X 36 OTHER FIFO, 3.6 ns, PBGA256
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits 16K X 36 OTHER FIFO, 3.7 ns, PBGA256
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| File Size |
617.12K /
62 Page |
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Download Datasheet
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Integrated Device Technology, Inc.
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| Part No. |
IDT72T51333 IDT72T51353 IDT72T51343
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| OCR Text |
...peration on read port ? ? ? ? ? partial reset, clears data in single queue ? ? ? ? ? expansion of up to 8 multi-queue devices in parallel is available ? ? ? ? ? power down input provides additional power savings in hstl and ehstl modes. ? ?... |
| Description |
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits
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| File Size |
539.63K /
55 Page |
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it Online |
Download Datasheet |
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Integrated Device Technology, Inc.
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| Part No. |
IDT72T51546 IDT72T51556
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| OCR Text |
...packet mode operation ? ? ? ? ? partial reset, clears data in single queue ? ? ? ? ? expansion of up to 8 multi-queue devices in parallel is available ? ? ? ? ? power down input provides additional power savings in hstl and ehstl modes. ? ?... |
| Description |
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits
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| File Size |
634.73K /
64 Page |
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it Online |
Download Datasheet |
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Integrated Device Technology, Inc.
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| Part No. |
IDT72T51553 IDT72T51543
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| OCR Text |
...peration on read port ? ? ? ? ? partial reset, clears data in single queue ? ? ? ? ? expansion of up to 8 multi-queue devices in parallel is available ? ? ? ? ? power down input provides additional power savings in hstl and ehstl modes. ? ?... |
| Description |
2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 18 BIT WIDE CONFIGURATION 2.5V的多队列流量控制器件2队列8位范围配
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| File Size |
558.69K /
57 Page |
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it Online |
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Osram Opto Semiconductors GmbH
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| Part No. |
LBE63C-S2U1-35
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| OCR Text |
...leds in lux mit der innovativem partial flux methode erolgt, wurden vergleichsmessungen an bauteilen jeweils mit dem "partial flux" testkopf und dem "standard led" testkopf (gem?? cie-127-b) durchgefhrt. der vergleich soll als orientierung ... |
| Description |
Power TOPLED with Lens Enhanced Optical Power LED (ATON)
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| File Size |
34.02K /
16 Page |
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it Online |
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Galileo Technology Services, LLC
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| Part No. |
GT-64012
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| OCR Text |
...wo types of reads: uncacheable (partial reads) and cacheable (block reads). all partial reads (syscmd[7:5] = 0 and syscmd[3] = 1), are forwarded to the system a cycle later than the issue cycle on the cpu bus. as both the sysad and sysc... |
| Description |
Secondary Cache Controller For the MIPS R4600/4650/4700/5000,(用于MIPS R4600/4650/4700/5000处理器的二级高速缓存控制器)
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| File Size |
606.58K /
24 Page |
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it Online |
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Fujitsu Microelectronics
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| Part No. |
MB82BDR08163A-70L
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| OCR Text |
...mode sleep, 16m-bit and 32m-bit partial
2 (ae2.0e) mb82dbr08163a -70l preliminary n n n n pin description n n n n block diagram pin name description a 22 to a 0 address input ce 1 chip enable (low active) ce2 chip enable (high active)... |
| Description |
Products psuedo-SRAM complying to COSMORAM standards
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| File Size |
919.24K /
52 Page |
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it Online |
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PMC-Sierra, Inc.
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| Part No. |
PM7380-PI
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| OCR Text |
... 9.4 receive hdlc processor / partial packet buffer...43 9.4.1 hdlc processor .....................................................44 9.4.2 partial packet buffer processor ..................44 9.5 receive dma controller ................ |
| Description |
FRAME ENGINE AND DATA LINK MANAGER 32P672 32 CHANNEL(S), 8.192M bps, SERIAL COMM CONTROLLER, PBGA329
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| File Size |
2,584.28K /
332 Page |
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it Online |
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